• 沒有找到結果。

Capacitances versus V GS for Different Layout Structures

Chapter 4 Capacitance Characteristics of RF LDMOS with Different

4.3 Capacitances versus V GS for Different Layout Structures

For the square structure, however, second peak in CGS+CGB and CGD are observed when biasing at high drain voltage (VDS=10 and 20 V) (see Fig. 4.2). But there are no additional peaks in CGS+CGB and CGD for circle structure that has ring shape like square structure. The same phenomenon is shown in Fig. 4.3, the CDG falls slowly at high drain voltages for square structure as gate voltage increases. From Fig. 4.3, the CDG almost equals to each other for three structures before the device entered the quasi-saturation regime. When gate voltage exceeds threshold voltage, the CDG starts to increase quickly due to the channel region is inverted to attract charges. As shown in Fig. 4.4, the currents flow from drain to source with uniform distribution in the full region of the fishbone and circle structures. However, in the square structure, the corner region of the drift shows lower current density than the edge region [36], [37], and thus it is needed higher gate voltage to enter quasi-saturation. At the first peak, although the edge of the square ring is operated in quasi-saturation region, the corner is still in pre-quasi-saturation. By keeping increasing the gate voltage, the current in the corner region is high enough to make the velocity of electrons in the drift saturated.

Therefore, the corner region operates in quasi-saturation and second peaks are generated in the CGS+CGB and CGD.

4.4 Summary

In this chapter, the capacitance characteristics of RF LDMOS transistors with different layout structures are studied. Since LDMOS transistor has a lateral non-uniform doping channel and a drift region, peaks in CGS+CGB and CGD have been observed. For the ring

structure, two peaks in a capacitance-voltage curve have been observed at high drain voltages due to the additional corner effect. Besides, the circle structure has the same capacitance characteristics as the fishbone structure that indicates only one peak in the capacitance curve.

We have to consider these parameters like the threshold voltage, quasi-saturation current and drift depletion capacitance that affect the capacitance in the LDMOS capacitance model.

0.0

Fig. 4.1 Extracted CGS+CGB, CGD and the drain current versus gate voltage at different drain biases for the fishbone structure.

-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

Fig. 4.2 Extracted CGS+CGB and CGD versus gate voltage at different drain biases for the (a) square and (b) circle structure.

-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 40.0f

80.0f 120.0f 160.0f 200.0f 240.0f 280.0f 320.0f 360.0f

VDS (V) 0.1 1 5 Capacitance (F) 20

Gate Voltage (V) Fishbone

Square Circle

Cdg

Fig. 4.3 Extracted CDG versus gate voltage at different drain biases for the fishbone, square and circle structure.

(a) (b) (c)

Fig. 4.4 Schematic view of layout structure and current distribution: (a) fishbone structure, (b) square structure and (c) circle structure.

Chapter 5

Modified MOS Model 20 (MM20) for LDMOS

5.1 Introduction

The MOS Model 20 (MM20) is a compact MOSFET model focusing on DC characteristics. It has been developed to describe the electrical behavior of the region under the thin gate oxide of a high-voltage MOS device, like an LDMOS device. MM20 combines MOS Model 9 (MM9) for the channel region and MOS Model 31 (MM31) for the drift region under the thin gate oxide. This model calculates the equations that are describing transistor electrical characteristics in surface-potential formulations. In order to improve the convergence behavior during circuit simulation, it uses an internal voltage at the transition (node Di) from the channel region to the drift region to calculate the surface potentials [38].

The surface potential as a function of the terminal voltages is obtained by the explicit expression as derived in ref. 39. Using these equations can describe the all operation regimes (accumulation, depletion, and inversion in both the channel region and the drift region). In addition, the MM20 also include several important physical effects like mobility reduction, velocity saturation, drain-induced barrier lowering, static feedback, channel length modulation, and weak avalanche (or impact ionization). If transistors have an additional thick field oxide, this model can be used in series with a separate model for the drift region under the thick field oxide. Consequently, the MM20 provides an accurate description in all operating regimes, ranging from subthreshold to superthreshold, in both the linear and saturation regime [40].

5.2 T-CAD Simulation

We simulate the quasi-saturation effect in the LDMOS by using the T-CAD simulation

software. The structure is built on measured device in 2D dimension, and we do our best to make the simulation factor as the same as real phenomenon. Fig. 5.1 shows the simulated structures showing lateral electric field and the depletion region at Vg = 2.5 V and Vd = 10 V.

The maximum lateral electric field occurs at the pinch-off region near the gate edge and the drift region under the FOX is inversion. At this condition, the device does not yet enter quasi-saturation and channel current still increases with increasing gate voltage. Under Vg = 10 V and Vd = 10 V, the space-charge distribution changes, and the maximum lateral electric field shifts toward the drain and occurs in the drift region (see Fig. 5.2). Additionally, the lateral electric field decreases near the gate edge and the drift region under the FOX becomes accumulation. At this condition, the drain current is dominated by drift region and the device enters quasi-saturation [41]. Above described device have the poly gate covering on FOX and this poly gate is called field plate. Next, we discuss the device only have poly gate on the channel region. Fig. 5.3 shows the device does not enter quasi-saturation and is biased at Vg = 2.5 V and Vd = 10 V. It is the same as Fig. 5.1 that the maximum lateral electric field occurs at the pinch-off region near the gate edge and the drift region under the FOX is inversion. As device is bias at Vg = 10 V and Vd = 10 V, the maximum lateral electric field still occurs in the channel region (see Fig. 5.4). In addition, the space-charge distribution does not change much and the most drift region under the FOX is still inversion. Therefore, the device with field plate can make the drift region transfer its type from inversion to accumulation and make the lateral electric field distribute uniformly. So, it would increase the device breakdown voltage.

5.3 Modeling Strategy

For simplicity, some physical effects like self-heating and weak avalanche are not concluded in the modified model. Besides, based on the T-CAD simulation results, we have modified the drift region current for better fitting our measured I-V and C-V curves.

The device DC model would be developed with analysis of carrier transport in the channel and drift regions. The drain current is separated from two elements, one is through the intrinsic MOS channel (Ich) and the other is through the drift region (Idrift), and the two currents are formulated respectively in terms of the external bias VG, VD, VS, VB and the unknown voltage VDi. Then, VDi is solved automatically by equating Ich to Idrift. Therefore, the drain current is expressed explicitly by the external terminal voltage. The channel current is expressed as follow: thin-gate-oxide capacitance per unit area, Vinv0 represents the inversion charge Qinv per unit area at the source side, and θ3 = μch / (Lchvsat) represents velocity saturation in the channel region, with μch the zero-field electron mobility in the channel region and vsat the saturated drift velocity of electrons. The factor ξ = (∂Qinv/ ∂ψs)/ Cox reflects the variation of inversion charge with surface potential, and is taken as ξ = [1+ (1/ 2 · γ0)] /√(V1 + ψs0) , where γ0 is the body factor at the source, V1 = 1 V, and ψs0 is the surface potential at the source. From Fig.

5.2 & Fig. 5.4, as the device enter quasi-saturation, the voltage drop in the drift region increases led to the maximum electric felid occurs in the drift region and drain current is dominated by drift region. The effective electron mobility ( ) is used to describes this effect. As electric felid increase in the drift region, the carrier velocity will enter saturation regime and θ

dr

μeff

3dr (=μeffdr/ (Ldrvsat)) can describes this effect. When device without field plate is biased gate voltage from 2.5 V to 10 V, the current have to pass through a depletion region under Fox. Therefore, the high resistance (Rdr) limits the current in the drift region when device enter quasi-saturation. In addition, the device with field plate has different

performance. As VG= 2.5V, the drift region under Fox is depletion region and like general performance (see Fig. 5.3 & 5.4). As VG= 10V, the drift region under Fox becomes electrons accumulated layer and the drain resistance is lower to enhance current (see Fig. 5.1& 5.2).

The parameter Rdr is concluded in VqDiand ξdr which simple equation is VqDi= Ldrflin/ (WμdrCoxRdr), where flin is a function about the depletion thickness. The drift region current can be represented by combining above descriptions and be expressed as follow:

DDieff

Where μeffdr is the effective electron mobility in the drift region, θ3dr represents the

occurrence of velocity saturation in the drift region, and VqDi= −Qdr / Cox, where Qdr is the charge density per unit area underneath the thin-gate oxide including accumulation and depletion in the drift region, for simplicity, ξdr represents the variation of accumulation charge with voltage.

In order to calculate the capacitance, we present nodal charges in the channel and drift region as follow:

⎟⎟

The model parameters of fishbone and circle devices were extracted from their I-V and C-V curves. The measured and simulated I-V curves are shown in Figs. 5.5 and 5.6. The simulated results show excellent consistency with the measured data for two structures except at high drain voltages. At high drain voltages, the drain current is influenced by self-heating and weak avalanche effects, which have been ignored in our model. Fig. 5.7 shows the simulated and measured Cgs+ Cgb and Cgd versus gate voltage with different drain voltages.

The simulated capacitance characteristics also show consistency with the measured data for two structures. Some extracted model parameters are listed in Table 5-1. For circle structure, the electron mobility in the drift region (μdr) is larger than fishbone structure due to lower drain parasitic resistance. The parameter Rdr in the circle structure is lower and enhances the drift region current. In the chapter 2, we also know the fishbone structure having high RD

which is extracted from small signal circuit model causes to the device enter the quasi-saturation earlier. In addition, the θ3dr is similar because effective drift length (Ldr)is longer for circle structure. From the C-V curves, we find that the flat band voltage occurs at

VG= -1.7~-2V and is smaller for circle structure. This is similar as the extracted model parameter VFB. Mover, the electron mobility in the channel region (μch) is lager for fishbone structure due to lower channel resistance. So, the fishbone device has larger transconductor and these performances are agreement with chapter 2.

5.5 Summary

The device models have been obtained for fishbone and circle structures by using the modified MM20. The quasi-saturation effect dominated in the drift region is also considered.

From I-V and capacitance characteristics, this model shows an accurate description in all operating regimes, and provides a good agreement between simulated and measured data. In addition, we confirm the device enters the quasi-saturation earlier due to higher drain parasitic resistance and the drain parasitic resistance is lower for circle structure. Consequently, the extracted model parameters have been analyzed and present the similar information as chapter 2.

Table 5-1 Extracted VFB, μch, μdr, θ3dr, Rdr and LD from modified MM20 for different layout structures.

VFB μch μdr θ3dr Rdr LD

Fishbone -1.832 194.6m 694.2u 330m 86.54 270n Circle -1.85 181.5m 782.7u 332.6m 76.31 280n

Fig. 5.1 The right figure shows the space charge distribution of LDMOS at Vg= 2.5V and Vd= 10V and the left figure shows the electric field along the channel region to drift region.

Fig. 5.2 The right figure shows the space charge distribution of LDMOS at Vg= 10V and Vd= 10V and the left figure shows the electric field along the channel region to drift region.

Fig. 5.3 The right figure shows the space charge distribution of LDMOS at Vg= 2.5V and Vd= 10V and the left figure shows the electric field along the channel region to drift region.

Fig. 5.4 The right figure shows the space charge distribution of LDMOS at Vg= 10V and Vd= 10V and the left figure shows the electric field along the channel region to drift region.

(a)

Fig. 5.5 Measured (mark) and simulated (line) drain current IDS versus gate voltage at different drain biases for the (a) fishbone and (b) circle structures.

0 5 10 15 20 25 30 35

Fig. 5.6 Measured (mark) and simulated (line) drain current IDS versus drain voltage at different gate biases for the (a) fishbone and (b) circle structures.

-4 -2 0 2 4 6

Fig. 5.7 Measured (mark) and simulated (line) CGS+CGB and CGD versus gate voltage at different drain biases for the (a) fishbone and (b) circle structures.

Chapter 6

Conclusions and Suggestion

6.1 Conclusion

We have investigated the DC, AC, high-frequency, RF power characteristics and DC model of LDMOS transistors with different layout designs. Based on the same distance of each cell, we find that the cutoff frequency, maximum oscillation frequency and power performance were improved using the ring structures. In the traditional design, the ring (also called enclosed, edgeless, or donut in other literatures) structures were used to lower the parasitic capacitances for more linear and faster devices [43-44]. For MOSFET, the conventional parasitic drain capacitance refers to the n+ drain to p-substrate junction capacitance. Hence, the drain was always surrounded by the transistor channel and source to reduce the area. In LDMOS, however, the parasitic drain capacitance refers to the deep n-well (DNW) to p-substrate junction capacitance. Therefore, drain outside or inside for ring structure has no impact on drain capacitance. Since larger area for output terminal could reduce the parasitic drain resistance, ring structures with drain outside layout would be the better choice for the LDMOS. This layout design can improve the performance without altering the process flow. In addition, we also find that the transconductance, on-resistance, cutoff frequency and linearity were improved except maximum oscillation frequency and power performance by using the circle structure. It is obvious that the circle structure success to compress the corner effect in the square structure and improve the DC performance. Finally, the modified MM20 shows an accurate description on DC and capacitance characteristics.

And the results are agreement with above descriptions.

In chapter 2 fishbone, square, octagon and circle structure were investigated. Fishbone and ring structures were compared. The fishbone structure has better on-resistance and

linearity due to lower channel resistance but it has larger RTH. The RF performance like fT, fmax and power were improved for the ring structures due to the lower drain parasitic resistance. If reducing the distance of each cell in the ring structure, the RF performance will be enhanced much due to decrease the parasitic capacitance and maintain the same DC performance as fishbone. In addition, square and circle structures were also compared. The DC performance like drain current and transconductance were enhanced for the circle structure due to lower drain parasitic resistance and uniform drain current density contributed by canceling the corner of drift region.

In chapter 3 square devices with various channel width were investigated. The device with larger Wch has better fT, fmax, RF power and linearity due to lower drain parasitic capacitance, but it also has larger on-resistance due to larger drain parasitic resistance. It shows a trade-off between the DC performance and the RF performance.

Capacitance characteristics were analyzed completely in chapter 4. For having a non-uniform doping channel, CGD exhibits a peak at the threshold voltage. For existence of the drift region, CGS+ CGB and CGD show a peak at the onset of quasi-saturation. In the square structure, the second peaks in a capacitance-voltage curve have been observed at high drain voltages due to the additional corner effect. Moreover, the circle structure only has the first peaks in a capacitance-voltage curve just like as fishbone.

In chapter 5 the modified MM20 is used to simulate the LDMOS with different layout design. This model provides an accurate description in all operating regimes, ranging from subthreshold to superthreshold, in both the linear and saturation regime and includes physical effects like mobility reduction, velocity saturation, drain-induced barrier lowering, static feedback and channel length modulation. A comparison with DC and capacitance measurements on LDMOS device shows a very good agreement. In addition, the extracted model parameters have been analyzed and show an agreement with chapter 2.

References

[1] P. Aaen, J. A. Plá, and J. Wood, Modeling and Characterization of RF and Microwave Power FETs, Cambridge University Press, 2007.

[2] F. van Rijs, and S. J. C. H. Theeuwen, “Efficiency improvement of LDMOS transistors for base stations towards the theoretical limit,” IEDM Tech. Dig., Dec. 2006, pp. 11–13.

[3] F. van Rijs, “Status and trends of silicon LDMOS base station PA technologies to go beyond 2.5 GHz applications,” RWS 2008, pp. 69-72, 2008.

[4] P.J. van der Wel, et al., “Wear out failure mechanisms in aluminium and gold based LDMOS RF power applications,” Microelectronics Reliability, 46, pp. 1279-1284, 2006.

[5] A. Wood and W. Brakensiek, “Application of RF LDMOS Power Transistor for 2.2 GHz Wideband-CDMA,” in Proc. IEEE Radio and Wireless Conf., 1998, pp. 309-312.

[6] J. J. Bouny, “Advantages of LDMOS in high power linear amplification,” Microwave Engineering Europe, April 1996, p. 37–40.

[7] B. Vassilakis, A. Cava, and W. Veitschegger, “Wireless base station technology evolution,”

in Proc. IEEE Compound Semiconductor Integrated Circuit Symp., 2004, pp. 3-7.

[8] M. Shindo, M. Morikawa, T. Fujioka, K. Nagura, K. Kurotani, K. Odaira, T. Uchiyama, and I. Yoshida, “High power LDMOS for cellular base station applications,” in Proc.

IEEE SISPAD, 2001, pp. 107-110.

[9] J. Cai, C. Ren, N. Balasubramanian, and J. K. O. Sin, “A novel high performance stacked LDD RF LDMOSFET,” IEEE Electron Device Lett., vol. 22, No. 3, pp. 236-238, May 2001.

[10] M. Kondo, N. Sugii, Y. Hoshino, W. Hirasawa, Y. Kimura, M. Miyamoto, T. Fujioka, S.

Kamohara, Y. Kondo, S. Kimura, and I. Yoshida, “High Performance RF Power LDMOSFETs for Cellular Handsets Formed in Thick-Strained-Si /Relaxed-SiGe Structure,” IEDM Tech. Dig., Dec. 2005, pp. 365-368.

[11] C. Anghel, Y. S. Chauhan, N. Hefyene, and A. Ionescu, “A physical analysis of HV

MOSFET capacitance behaviour,” in Proc. IEEE ISIE, Jun. 2005, vol. 2, pp. 473–477.

[12] R. Valtonen, J. Olsson, and P. De Wolf, “Channel length extraction for DMOS transistors using capacitance-voltage measurements,” IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1454–1459, Jul. 2001.

[13] Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, “Analysis and modeling of lateral non-uniform doping in high-voltage MOSFETs,” IEDM Tech. Dig., Dec. 2006, pp. 1–4.

[14] S. P. Voinigescu, S. W. Tarasewicz, T. MacElwee, and J. Ilowski, “An assessment of the state-of-the-art 0.5 μm bulk CMOS technology for RF applications,” IEDM Tech. Dig., Dec. 1995, pp. 721–724.

[15] C. S. Kim, H. K. Yu, H. Cho, S. Lee, and K. S. Nam, “CMOS layout and bias optimization for RF IC design applications,” IEEE MTT-S Digest, pp. 945-948. 1997.

[16] H. Lee, J. H. Lee, Y. J. Park, and H. S. Min, “Characterization issues of gate geometry in multifinger structure for RF-SOI MOSFETs,” IEEE Electron Device Lett., vol. 23, No. 5, pp. 288-290, May 2002.

[17] M. M. De Souza, G. Cao, E. M. Sankara Narayanan, F. Youming, S. K. Manhas, J. Luo, and N. Moguilnaia, “Progress in silicon RF Power MOS technologies - current and future trends,” in Proc. International Caracas Conf. Devices, Circuits and Systems (ICCDCS), 2002, pp. D047 (1 – 7).

[18] R. Yang, J. F. Li, H. Qian, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “A Short-Channel SOI RF Power LDMOS Technology With TiSi2 Salicide on Dual Sidewalls With Cutoff Frequency fT ~19.3GHz,” IEEE Electron Device Lett., vol. 27, No. 11, pp.

917-919, Nov. 2006.

[19] Hsin-Hui Hu, Kun-Ming Chen, Guo-Wei Huang, Chun-Yen Chang, Yii-Chian Lu, Yu-Chi Yang and Eric Cheng, “Characterization of RF LDMOS Transistors with Different Layout Structures,” SSDM, pp. 536-537, 2006.

[20] F. M. Rotella, G. Ma, Z. Yu, and R. W. Dutton, “Modeling, analysis, and design of RF LDMOS devices using harmonic-balance device simulation,” IEEE Trans. Microwave Theory Tech., vol. 48, No. 6, pp. 991-999, Jun 2000.

[21] M. A. Belaid, K. Ketata, H. Maanane, M. Gares, K. Mourgues, and J. Marcon, “Analysis and simulation of self-heating effects on RF LDMOS devices,” in Proc. IEEE SISPAD, 2005, pp. 231-234.

[22] S. C. Wang, G. W. Huang, K. M. Chen, A. S. Peng, H. C. Tseng, and T. L. Hsu, “A Practical Method to Extract Extrinsic Parameters for the Silicon MOSFET Small-Signal

[22] S. C. Wang, G. W. Huang, K. M. Chen, A. S. Peng, H. C. Tseng, and T. L. Hsu, “A Practical Method to Extract Extrinsic Parameters for the Silicon MOSFET Small-Signal

相關文件