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Conclusions and Future Work

Conclusions and Future Work

6.1 Conclusions

This research has investigated various aspects in designing practical LDPC coding systems, including encoding, decoding, and code structure. Our work mainly focuses on reducing the processing latency and computational complexity of the system while maintaining good error correcting performance.

First, we propose an encoding algorithm with low latency for dual-diagonal LDPC codes. Our algorithm relaxes data dependency within the encoding process to allow highly parallel operations and better hardware utilization. Implementation results show that the proposed encoder algorithm achieves shorter encoding latency and better throughput to area ratio for dual diagonal codes.

Secondly, we propose a low complexity approach combining an adaptive stopping criterion and a node deactivation mechanism to reduce the number of total node operations required in LDPC decoding. The proposed approach can significantly reduce the number of node operations without error performance degradation. Next, to speedup the decoding convergence, two types of dynamic message scheduling strategies for LDPC decoders are proposed. The first strategy schedules the message updates in a less-greedy way as compared to the conventional dynamic scheduling algorithms. The second strategy applies

a farsighted metric for ordering and selecting the next message to update. The proposed metric estimates the potential of correcting errors by the corresponding message update.

The proposed less-greedy schedule achieves better BLER performance and converges faster than the conventional scheduling algorithms. The proposed farsighted schedule outperforms the less-greedy schedule in terms of both error performance and convergence speed.

Then more low-complexity early stopping criteria are proposed for successful and unsuccessful decoding. For successful decoding, our proposed stopping check equations exclude all parity bits corresponding to degree-2 nodes for the dual-diagonal portion in the matrix. Simulations show the average number of iterations can be reduced by 10% to 15%

at operating point with no performance loss. For unsuccessful decoding, two types of early termination mechanisms are proposed. The first mechanism utilizes the syndrome-check block in the decoder to detect undecodable blocks. This mechanism achieves better iteration reduction and less error performance degradation than comparable approaches.

The second mechanism uses the hard decisions made during consecutive iterations to monitor the decoding status and detect the decoding convergence. This mechanism can achieve significant iteration reduction without compromising error performance.

Finally, we propose a class of structured LDPC codes, H-QC codes, with error performance that matches randomly constructed codes. Compared with QC codes, H-QC codes show no error floors at long code lengths. Two-level H-QC codes are well suited for partially-parallel hardware LDPC decoder implementation. We show that only minor modifications are necessary to adapt QC LDPC decoder architecture to support two-level H-QC codes. The degree of parallelism and code length can be easily adjusted by changing

the H-QC construction parameters. These properties make H-QC codes suitable for long-length LDPC code applications.

6.2 Future Work

First of all, we have presented several encoding and decoding techniques for dual-diagonal codes. Note that other structured codes such as Irregular Repeat Accumulate (IRA) codes [52] defined in DVB-S2 standard [8] or OFDM-based UWB systems [53] are similar to or generalized versions of dual-diagonal codes. We can extend the proposed algorithms to apply to those codes and try to keep our algorithm excellence. Secondly, for dynamic scheduled decoding, the complexity for obtaining the ordering metric is still a burden. Since the proposed low-complexity farsighted schedule has restricted the candidates via the graph connectivity, we can try to schedule message updates with less-complex ordering methods. Finally for hardware-oriented code design, more graph properties can be included in code construction, such as extrinsic message degree (EMD) and approximate cycle EMD (ACE) [54], to achieve better error floor performance.

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