Chapter 3 A Wide Range DLL-based Multiphase Clock Generator with Duty
3.6 Conclusion
A wide range DLL-based multiphase clock generator is proposed. The operating range is from 80 MHz to 500MHz. With the proposed harmonic detection circuit, the proposed multiphase clock generator is free from the harmonic problem. The delay block controller has the dual modes- SAR mode and counter mode. The SAR mode helps to accelerate the lock in speed and the counter mode keeps the proposed work tacking the environmental variations when finishing the SAR search. When the input voltage and frequency are 1.0V and 500MHz, the power consumption is 0.29mW.
With the proposed duty cycle corrector, the clock signal has a 50% duty cycle. The proposed duty cycle can be operated as low as 0.5V. The correction range is from 25%
to 75%. The operation range is 100MHz to 500MHz. With the PVT detection, the output duty cycle error can be reduced up to 17%. When the input voltage and frequency are 0.5V and 167MHz, the power consumption is 26.30 μW.
53
Chapter 4
An Energy-Efficient Level Converter with High Thermal Variation Immunity for Sub-threshold to Super-threshold Operation
A multiple supply voltage scheme is an emerging approach to reduce power dissipation. The scheme requires a level converter as a bridge for different voltage domains. Conventional level converters fail to work in sub-threshold region due to the pull-down devices and the pull-up devices operate in sub-threshold and super-threshold region respectively. By employing diode-connected PMOS transistors, multiple-threshold-voltage CMOS (MTCMOS), and stack leakage reduction techniques, the proposed cross-coupled level converter achieves small propagation delay, low power consumption, and best power-delay-product (PDP) performance.
Also, the reverse short channel effect is utilized to provide our level converter better process/thermal variation immunity. We also propose a dual edge-triggered explicit-pulsed level-converting flip flop (LCFF) concept combining a DCVSPG latch and our level converter. The proposed cross-coupled level converter is designed using TSMC 65nm bulk CMOS technology. It functions correctly across all process corners for a wide input voltage range, from 150mV to 1V. The level converter has a
54
propagation delay of 52ns and a power dissipation of 21nW when the input voltage is 150mV.
In this chapter, we propose a power-delay-product optimized and robust level converter with high thermal variation immunity for sub-threshold to super-threshold operation. This chapter is organized as follows. A introduction is given in Section 4.1.
Diode-connected PMOS transistors, multiple-threshold-voltage CMOS, and stack leakage reduction techniques are discussed. Also, reverse short channel effect, sub-threshold device sizing, and inner inverter device sizing are analyzed in Section 4.2. The simulation results of this work under TSMC 65nm CMOS technology are proposed in Section 4.3. Finally, Section 4.4 concludes this work.
4.1 Introduction
Power dissipation becomes a critical concern in emerging portable applications such as biological systems or wireless electronics. Constrained by a small form factor, the battery lifetime is a critical challenge. Ultra-low voltage design has been proofed to be an effective solution since supply voltage is quadratic function of energy.
However, the side effect of scaling down the supply voltage is the degradation of performance and robustness. Multiple supply voltage techniques have been presented for low power design [4.1]. Some parts of a digital system are employed a nominal supply voltage to meet the performance needs. The other parts are operated in the sub-threshold region to save the power dissipation. Such multiple voltage designs can run different blocks at the different supply voltages to perform dynamic voltage and frequency scaling (DVFS) on different voltage domains. Between the two different voltage domains, it may occur a situation that a lower supply voltage gate drives a higher supply voltage gate. While the high output of a lower supply voltage gate is not
55
strong enough to fully turn off a PMOS gate supplied by a higher supply voltage, this results in a DC leakage path from the voltage source to the ground and increases the power dissipation. In addition, if a higher supply voltage gate is driven by a lower supply voltage gate, it cannot have a full output swing and causes a function error. To solve these problems, a level converter is essentially inserted at the interface between two different voltage domains. Nonetheless, the level converter also consumes power and causes a considerable timing delay. In the multiple supply voltage systems, it is crucial to design a high-speed and energy-efficient level converter.
Fig. 4.1(a) shows a conventional level converter. Two cross-coupled PMOS transistors form a positive feedback loop to make the output full swing. However, the cross-coupled level converter encounters an imbalance driving strength problem so that the positive feedback can’t be triggered. For the signal converting from sub-threshold to super-threshold, some transistors of the level converter are operated in the sub-threshold region and the other transistors perform in the super-threshold operation. A Monte Carlo simulation of the conduction current in 65nm CMOS technology is shown in Fig. 4.1(b). It demonstrates that the driving ability of super-threshold PMOS is much larger than sub-threshold NMOS. Such driving ability difference leads to a level converter failure.
56
Figure 4.1. (a) Convention cross-coupled level converter. (b) Monte Carlo simulation of conduction current
Recently, many level converters [4.2]-[4.10] have been designed to operate in the sub-threshold region. In [4.2], the cross-coupled PMOS transistors are connected by two diode PMOS transistors. They can reduce the pull-up devices driving ability to enable sub-threshold operation. There is a short current problem occurred in [4.2]
resulting large power dissipation, as Fig. 4.2 shown. A level converter with a short current limiting technique was presented in [4.3]. It inserted two NMOS transistors in the positive feedback loop between the latch PMOS transistors and the PMOS diodes, as Fig. 4.3 shown. The two NMOS transistors speed up the transition to avoid a short current path. However, the reliability of two NMOS transistors is susceptible to the
57
variations. In [4.4], it cascaded two conventional cross-coupled level converters to prevent the short current path, as Fig. 4.4 shown. Nevertheless, the cascaded architecture results in a slow propagation speed at higher supply voltage.
Vin
VDDH
Vout
Figure 4.2. A level converter with two diode-connected PMOS transistors [4.2].
Vout
Vin Vin
Figure 4.3. A level converter with built-in short circuit current reduction [4.3]
Vin
VDDH
Vout LVT HVT RVT
Figure 4.4. A level converter with two cascade cross-coupled level converters [4.4].
58
4.2 Proposed Energy-Efficient Level Converter with High Thermal Variation Immunity
The schematic view of the proposed level converter is shown in Fig. 4.5. It is based on the cross-coupled level converter and adapts two diode-connected PMOS transistors in [4.5]. The multiple-threshold-voltage CMOS design is also employed in the proposed level converter. In addition, a stack leakage reduction technique is used to reduce the power consumption. Reverse short channel effect is also exploited to make the proposed level converter more reliable and robust across all the process corners and temperature variations.
Vin
VDDH
Vout
Vout
Voutb
Voutb
LVT HVT RVT
MP1 MP2
MP3 MP4
MN1 MN2
MN3 MN4
MN5 I1 MN6
Figure 4.5. Schematic view of the proposed level converter
4.2.1 Diode-Connected PMOS Transistors
From Fig. 4.1(b), we can find that the conventional level converter has an imbalance driving ability problem when converting a signal from the sub-threshold region to the super-threshold region. For TSMC 65nm CMOS technology, the ratio of pull-down device (NMOS) and pull-up device (PMOS) should be larger than 200X so
59
that the conventional level converter can barely be operated at an input supply voltage of 200mV. The resulting width of NMOS causes a huge area overhead. In Fig. 4.5, the proposed level converter utilizes diode-connected PMOS transistors to reduce the pull-up driving ability [4.5], MP3 and MP4 serve as a current limiter. Two PMOS diodes maintain its initial value during the transition. The initial value is equal to a small diode voltage drop and limits the PMOS strength. As a result, the pull-down devices, MN1 and MN2, can sink the I1 current even when the circuit is operated in the sub-threshold region. Comparing the results in Fig. 4.1(b) and Fig. 4.6, the PMOS conduction current is decreased dramatically and closer to the NMOS conduction current. Thus, they have a comparable driving ability. By connecting two PMOS diodes, the modified cross-coupled level converter overcomes the imbalance conduction current problem when operated at low voltage. Thus, the proposed level converter can convert the signal from sub-threshold region to super-threshold region successfully.
1 1.5 2 2.5 3 3.5 4 0
200 400 600 800 1000
T im e s
conduction current (nA)
σ/μ=0.14 σ/μ=0.48 PMOS at super-threshold
NMOS at sub-threshold
Figure 4.6. Monte Carlo simulation of conduction current of two diode-connected PMOS transistors
60
4.2.2 Multi-threshold-voltage CMOS (MTCMOS)
The MTCMOS design is usually provided in the modern technology.
Low-threshold voltage (LVT) devices take the advantage of the speed but have a severe leakage current problem. High-threshold voltage (HVT) devices have a less leakage current but sacrifice the speed. There is a trade-off between the propagation delay and the power consumption. Therefore, power-delay-product (PDP) should be used as a figure of merit for level converter analysis. To further weaken the PMOS strength, MP1, MP2, MP3, and MP4, use the HTV devices. To enhance the NMOS strength, MN1, MN2, MN3, and MN4, are considered using the LTV devices. If all the NMOS transistors are utilized the LTV devices, the power consumption will be increased very much. In the proposed level converter, only MN3 and MN4 use the LTV devices. This configuration can make a faster speed when output changes from high to low and improve the total propagation delay time. From Fig. 4.7, we can find that the pull up current is shifted to left and becomes more convergent.
1 1.5 2 2.5 3 3.5 4
0 200 400 600 800 1000
T im e s
conduction current (nA)
σ/μ=0.11 σ/μ=0.48 PMOS at super-threshold
NMOS at sub-threshold
Figure 4.7. Monte Carlo simulation of using HVT devices for pull up PMOS transistors
61
4.2.3 Stack Leakage Reduction Technique
The leakage current causes the static power consumption. With the scaling down technology, this problem becomes severely in the LVT logic block. In Fig. 4.8(a), the LVT block is connected by a HVTNMOS transistor [4.11]. When the LVT block is in a sleep mode, the connected HVT transistor is also turned off by a sleep signal to avoid a leakage path to the ground. A sleep mode means the block function is turned off. From the Monte Carlo simulation in Fig. 4.8(b), the leakage current is reduced quietly a lot when using the leakage reduction technique. This technique is adapted in the proposed level converter. MN3 and MN4 are the LTV devices, they are connected by the HTV NMOS transistors, MN5 and MN6, as shown in Fig. 4.5. The signal of Vout and Voutb are feedback to control MN5 and MN6 adaptively. When the input is
“1”, MN3 is in an active mode and MN4 is in a sleep mode. Vout is charged by MP2
and turns on MN5, so the left branch works as usual. Voutb is discharged by the MN1 and turns off MN6. The right branch is in a sleep mode. When the input is “0”, Vout turns off MN5 and Voutb turns on MN6. The left branch is in a sleep mode and the right branch works as usual. In both of the situations, there are no leakage path existing.
62 LVT Block
VDD
Sleep
0.01 0.1 1
0 500 1000
times
Leakage current (nA)
σ/μ=0.03 with leakage reduction
without leakage reduction σ/μ=2.71
(a) (b)
Figure 4.8. (a) Leakage reduction technique [4.11]. (b) Monte Carlo simulation of leakage current with/without leakage reduction technique
4.2.4 Reverse Short Channel Effect [4.13]
The minimum channel length is typically selected for the optimal speed and power performance in the super-threshold operation since the short channel effect is a dominant factor. However, there is a different scenario in the sub-threshold region.
Because of the significantly reduced drain-induced-barrier-lowering (DIBL), the reverse short channel effect becomes a major factor in the sub-threshold operation.
Due to the reverse short channel effect, the threshold voltage decreases monotonically and the conducting current increases exponentially when the channel length is longer.
Thus, the best PMOS channel length of the proposed level converter is not the minimum length. From Fig. 4.9(a), the propagation delay increases with an increase of length. Based on the simulation data, the optimal device sizing is 85nm in this work, as Fig. 4.9(b) shown. While the channel length is longer than the optimal length, the reverse short channel effect is weak.
63
4.2.5 Sub-threshold device sizing
Except for reducing the pull up driving ability, enhancing the pull down driving current is another way to solve the imbalance current problem. The pull down devices are operated in the sub-threshold region so that the sizing technique has a linear impact on the current. To increase the width of the NMOS transistors makes the pull down driving ability stronger. From Fig. 4.10(a), the propagation delay is reduced by
60 80 100 120 140 160 180 200
Figure 4.9. Short channel effect. (a) Delay and power simulation (b) PDP value simulation
64 signal voltage level. Therefore, the inner inverter is also operated in the sub-threshold
150 200 250 300 350
Figure 4.10. Sub-threshold device sizing. (a) Delay and power simulation (b) PDP value simulation
65
region and causes a propagation delay time. As Fig. 4.5 shown, MN2 and MN4 are controlled by the output of the inner inverter. The positive feedback loop has to wait for MN2 and MN4 settling down to be triggered. However, the faster speed brings larger power consumption, as Fig 4.11 shown. Therefore, there is a trade-off between delay and power. From Fig. 4.11(b), we find an optimal point when the width of inner inverter is 400nm.
150 200 250 300 350 400 450 16
150 200 250 300 350 400 450 290
Figure 4.11. Inner inverter sizing. (a) Delay and power simulation. (b) PDP value simulation
66
4.2.7 Proposed level converter performance
Combining the above mentioned techniques, the overall PDP value can be reduced up to 23%, as Fig. 4.12(c) shown. By connecting two PMOS diodes, the conventional cross-coupled level converter can successfully convert the signal from the sub-threshold region to super-threshold region. Using multi-Vth devices improve the propagation delay up to 22%, as Fig. 4.12(a) shown. The leakage reduction technique compensates the LVT logic leakage problem so that the power can be reduced up to 26%, as Fig. 4.12(b). Employing the reverse short channel effect reduce the PDP value approximately up to 17%. Applying these techniques make the proposed level converter more robust and reliable.
67
4.3 Simulation Results
For comparison, we implemented the following three level converters:
conventional cross-coupled type, short current reduction type in [4.3] and two cross-coupled cascaded type in [4.4]. Iso-area analysis is used for the fair comparison.
4.3.1 Minimum input voltage
Comparing with the other three level converters, the proposed level converter has a minimum input voltage below the target voltage 200mV, as Fig. 4.13 shown. The
Figure 4.12. Performance comparison. A: two diode-connected PMOS. B: multi-Vth devices. C: leakage reduction technique. D: reverse short channel effect. E: inner inverter sizing. (a) By implementation B,
delay reduction up to 22% (b) By implement C, power reduction up to 26% (c)By implement D, PDP reduction up to 17%. Finally, combining all implementation, overall PDP reduction up to 23%.
68
minimum input voltage is defined as an input voltage which the level converter can function correctly at five process corners. We set VDDH to 1.0V at room temperature and swept the input voltage from 100mV to 1.0V at five process corners. For the sub-threshold level converter, the NMOS transistor should overpower the corresponding PMOS transistor to make the switch successfully. Therefore, the worst case is slow NMOS-slow PMOS corner. The minimum input voltage of the worst case is 150mV. Typical NMOS-typical PMOS and fast NMOS-fast PMOS are the best cases. The minimum input voltage of the best case is as low as 100mV. From the simulation, the proposed level converter has a wide operation range.
Conventional cross-coupled
[4.3] [4.4] This work 0
0.2 0.4 0.6
M in im u m i n p u t v o lt a g e ( V )
Level converter
Figure 4.13. Minimum input voltage comparison
4.3.2 Propagation delay, Power, and PDP
The propagation delay comparison is drawn in Fig. 4.14(a). Our work is slight slower than the level converter in [4.3] when supply voltage is higher than 0.5V. The level converter in [4.4] provides a slow speed because of a cascaded architecture. For the propagation delay comparison, the proposed level converter shows a better
69
performance when operated in the sub-threshold region. The power consumption comparison is shown in Fig. 4.14(b). Due to the leakage reduction technique, the LVT device leakage problem is compensated. Also, the reverse short channel effect device sizing helps the proposed level converter consumes less power. PDP comparison is
Figure 4.14. Performance comparison between the proposed level converter and the existing level converter. (a) Propagation delay comparison (b) Power comparison (c) PDP compariosn
70
4.3.3 Monte Carlo Simulation
Fig. 4.15 presents 5000-point Monte Carlo simulations for the supply voltage 500mV. Monte Carlo simulation demonstrates how the process variations affect the level converter characteristics. For the sub-threshold region, the Monte Carlo simulation of propagation delay is shown in Fig. 4.15(a). For the near-threshold region, the proposed level converter has the normalized variance value σ/μ is 0.07, which is a relatively small value among the other two level converter. Our work shows the less sensitivity towards the process variations. The proposed level converter is more robustness than the other two level converters in [4.3] and in [4.4].
71
4.3.4 Temperature-induced delay variation
MOSFET mobility and threshold voltage are changed with the temperature.
Consequently, the drain current is related with the temperature. We swept the temperature from 0˚C to 125˚C and measured the temperature variations on the propagation delay. For the simplicity, take the absolute value of the propagation delay
0 20 40 60 80 100 120 140
Figure 4.15. Monte Carlo simulation of propagation delay. (a) supply voltage is 200mV (b) supply voltage is 500mV
72
difference as the temperature-induced variation delay. Comparing with the other two level converters in [4.3] and [4.4], Fig. 4.16 presents that the proposed level converter has less the temperature effects on the propagation delay. The temperature variations on the delay can be reduced up to 99% at the higher supply voltage. Thus, the proposed level converter is more process, voltage, temperature robustness.
0.4 0.5 0.6 0.7
Figure 4.16. Temperature-induced variations on propagation delay.
4.4 Conclusions
A power-delay-product optimized and robust level converter is presented for sub-threshold to super-threshold signal converting. By combining energy-efficient techniques, PDP value of this work is decreased by 23%. Temperature induced converter can be applied to a dual edged-trigged explicit-pulsed level-converting flip flop with a modified DCVSPG latch. It is suitable to be the interface of two different
73
voltage domains in emerging dynamic voltage frequency scaling wireless applications.
3.2 um
4 .4 u m
Figure 4.17 Layout view of the proposed level converter
Table 4.1. Performance Summary and Comparisons
[2] [3] [4] This work
Technology 0.18μm 0.18μm 130nm 65nm
Propagation Delay 10μs@127mV 6.3ns@400mV 35ns@227mV 52ns@150mV
Power Consumption 20μW 7.9μW N.A. 21nW
VDDH 1.8V 1.8V 1.2V 1.0V
Minimum Input Voltage 127mV 400mV 227mV 150mV
Transistor Numbers 10 14 11 12
74
Chapter 5
A PVT Robust Dual-Edged Triggered
Explicit-Pulsed Level Converting Flip-Flop
In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converter may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a level converting flip-flop (LCFF) has been exploited. LCFFs provide a level converting function and a data latching function. A PVT robust dual-edged triggered explicit-pulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate latch (DCVSPG). The clock pulse generator has the symmetric pulse triggering time and holding period helping shorten the D-Q delay. By employed diode-connected PMOS transistors and multiple-threshold devices in the DCVSPG latch, the proposed LCFF can operated from near-threshold region to super-threshold region. In addition, two NMOS transistor are stacked below the diode PMOS transistors to prevent a sneaky leakage current. The proposed dual-edged triggered explicit-pulsed LCFF is designed using TSMC 65nm CMOS technology. It function correctly across all process corners with a wide input voltage range, from 400mV to 1V. The proposed LCFF has a minimum