Different Bias in P1dB Measurement

When applying different voltage on TX port, ANT port and body, the measured P1dB data are different. Table 5.1 shows the result.

Table 5.1 P1dB of different bias.

condition Vctrl Vbody Vtx Vant P1dB

Comparing with condition I and II, the P1dB is improved by bias voltage comparing to condition III and IV. In condition IV、V、VI, the ANT port is also bias positive voltage.

This concept is proposed in [8]-[10]. The TX and ANT node voltage reverse bias the

drain/ source to substrate p-n junction, therefore, improving the power handling capability. Condition VI is the optimized P1dB result.

5.1.2 The Issue of Power Handling Capability

In order to find out the issue of degraded power handling capability, laser cutting is been used. There are three types laser cutting die. First is cutting the shunt circuit of TX path (the node 1 in Fig. 5.1). Second is cutting receiver path (the node 2 in Fig. 5.1) and last is cutting the shunt circuit of TX path and RX path (the node 1 and 2 in Fig. 5.1).

The measured data is in Table 5.2 and table 5.3. In table 5.2, the bias condition is the V of table 5.1. In table 5.3, the bias condition is the VI of table 5.1. In shunt circuit of TX path, the power degradation is about 6 dB. In RX path, the power degradation is about 4 dB. If both RX path and shunt circuit of TX path are cutting, the P1dB can improved to 35~36 dBm. From these results can know the off state of transistor is the key reason degrades the power handling capability.

Table 5.2 Measured P1dB of condition V

Die condition P1dB (dBm)

Complete die 24

Cut position 1 29.85

Cut position 2 27.85

Table 5.3 Measured P1dB of condition VI.

Die condition P1dB (dBm)

Complete die 24.5

Cut position 1 30.85

Cut position 2 28

Cut position 1 & 2 36

Fig. 5.1 Cutting positions of circuit topology.

5.2 The Improvement of Power Handling Capability

5.2.1 The Equivalent Capacitor Cds

From the section 5.1.2, the equivalent capacitors of switch circuit are the issue of degraded insertion loss as well as power handling capability. For this reason, reducing capacitor value is the immediate thought and then the equivalent impedance become large. In equation 5.1, the parallel-plate capacitor:

d

C = ε A

Where ε is permittivity, A is plate area and d is the distance between parallel plates.

From this equation, enlarging distance of the parallel plates is the method of reducing capacitor value. Therefore, Fig. 5.2 shows the conventional and customized transistor layout. The customized transistor layout is enlarging the distance between source and drain, so the capacitor is reduced and then the goal of increased equivalent impedance is reached.

If the equivalent impedance of capacitors becomes higher, it means the effect of closing path is more effective. So the signal will not couple through the off-transistor and then the loss is reduced.

discussed in section 3.3.1. But except for body have parasitic diode, the deep n-well also have. A deep n-well (DNW) is offered as default in the TSMC 0.18μm mixed-signal process for better substrate isolation with an additional p-n junction.

Therefore, the additional DNW bias is also needed. Fig 5.3 shows the cross-sectional view of NMOS. From this figure there are parasitic diodes between DNW and p-type substrate, p-type body and DNW. Due to these parasitic diodes, the power handling capability is degraded. So connecting large resistor to DNW node could improve the power handling capability. If apply positive voltage in DNW node, the improving effect will become better. Because the positive voltage can reverse bias the diodes and large resistor can let current flow smoothly, the power handling capability consequently improved. Therefore, apply large resistor in DNW node is effective in improve power handling capability.

(a)

(b)

Fig. 5.2 Layouts of (a) conventional and (b) customized transistor.

Fig. 5.3 Cross-sectional view of NMOS.

Chapter 6 Conclusion

This paper demonstrates a CMOS T/R switch designed for ultra wideband and higher frequency applications. The LDD MOSFET has been used in this circuit to increase voltage bias on TX node and then improving the power handling capability.

The switch achieves 2.5 dB and 3.5 dB in TX and RX mode under 10.6 GHz, and isolation of 29.8-31.7, 25-31.5 dB, respectively. The measured 1-dB power compression point is 24.5 dBm. The power performance is also analyzed by laser cut.

The newly designed switch will be improved the insertion loss and power capability by smaller parasitic capacitor and control diode voltage method.

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Vita

姓名：陳順芳 性別：男

出生年月日：民國73年8月12日 籍貫：台灣省苗栗縣

住址：苗栗縣竹南鎮新南里23鄰勝利街43號 學歷：國立中央大學電機工程學系

(92年9月~96年6月)

國立交通大學電子研究所固態組 (96年9月~98年6月)

論文題目：

非對稱性 LDD 金氧半元件應用於射頻收發開關之研究

The Study of RF T/R Switch by Asymmetric-LDD MOS Transistor