This chapter describes the digital data path of the transmitter, which is composed of the blocks shown in Figure 8.1. A brief description of the operations performed in this pathway is now given. First, the binary data is convolved with the compensated transmit filter using a ROM and then added to a constant digital word corresponding to the nominal divide value, Nnom; Figure 8.2 displays the bit alignment between these signals. The value of Nnom sets the carrier frequency by virtue of the fact that Foutc = NnomFref. A Σ-∆ modulator then quantizes the resulting 16-bit sequence into a 6-bit sequence which is fed into the input of the divider.
2nd order S-D modulator
16-bit 6-bit
INsd[k]
Carrier Frequency
16-bit DATA[k]
ROM
1-bit 10-bit
N[k]
2.5 MHz
(at 2.5 Mbit/s) 20 MHz
Nnom
( )
20 MHz 20 MHz
Internal to CMOS IC
Pc(ej2pfT)
A B
C
data stream generated by computer in prototype
Figure 8.1: Digital data path to divider input.
To achieve the goal of low power, a pipelining technique discussed in [54, 55] is applied to the Σ-∆ modulator and adder in Figure 8.1. This approach allows the required throughput rate to be achieved with lower circuit speed, thus permitting reduction of power supply voltage. The cost of pipelining is an increase in the circuit area, and capacitance that must be switched during use. However, low power dissi-pation is achieved with supply scaling despite the increased capacitance, as discussed in [68].
117
A9A8A7A6 B15B14B13B12
A5A4A3A2A1A0
B11B10B9B8B7B6B5B4B3B2B1B0
C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1C0 A
+ B
= C
Figure 8.2: Bit alignment between modulation signal and Nnom when added to form INsd[k].
We begin by reviewing the basic topology and properties of the second order, MASH Σ-∆ modulator used in the prototype. The pipelining technique is then pre-sented, and its impact on the overall digital path design is described. Finally, issues related to the depth of pipelining are discussed, and circuit descriptions given.
8.1 Topology
Figure 8.3 shows the second order MASH Σ-∆ topology used in the prototype. The basic building blocks of the structure are first order sections consisting of accumulators whose carry bits are used as output. Each first order stage adds noise according to the relationship
out[k] = in[k] + (D− 1)e[k], (8.1)
where we have invoked the notation Die[k] = e[k− i]. In the presence of a sufficiently active input, e[k] can be considered a white noise source with spectral density
Se(f ) = 1/12. (8.2)
A single first order Σ-∆ stage thus adds quantization noise whose energy is shaped into high frequencies, as seen by examining the spectral density of the output:
Sout(f ) = Sin(f ) + e−j2πfT − 1 2Se(f ). (8.3) The cascade of two stages, as depicted in the figure, leads to second order noise shaping according to the relationship
SOU T(f ) = SIN(f ) + (e−j2πfT − 1)2 2Se(f ). (8.4) This last expression is calculated from the equation:
OU T [k] = out1[k] + (1− D)out2[k] = IN [k] + (1− D)2e2[k], (8.5) where e2[k] is assumed to have the same spectral density as e[k] described above.
8.2. PIPELINING TECHNIQUE 119
1st order
S-D D
carry out[k]
in[k] e[k]
1st order S-D 1st order
S-D
1-D out2[k]
16-bit
6-bit
6-bit 1-bit
10-bit IN[k]
OUT[k]
e1[k]
out1[k]
e2[k]
20 MHz
20 MHz
Figure 8.3: A second order, digital MASH structure.
8.2 Pipelining Technique
A MASH structure of any order has adders and accumulators for its basic building blocks. These components can be pipelined [54, 55] using a technique that will now be described.
The carry chain forms the critical delay path for adders; the carry signal must propagate from the least to most significant bit during each addition operation. This leads to a proportional relationship between the time required for computation and the number of bits in the adder. Pipelining of the carry path at the bit level breaks this relationship by allowing the carry information to travel through only one bit stage per clock cycle regardless of the number of bits in the adder.
Implementation of this approach is accomplished by inserting registers in the carry path, as illustrated in Figure 8.4 for a 3-bit example. The shading in the adder symbol shown in the figure distinguishes the structure from a standard adder (which does not contain registers in its carry path). To achieve time alignment between the input and the delayed carry information, registers are used to skew the input bits. As indicated in the figure, we refer to this operation as “pipe shifting” the input. The adder output is realigned in time by performing an “align shift” of its bits as shown.
The same pipelining approach can be applied to accumulators, as illustrated in Figure 8.5. At first glance, it is somewhat surprising that this technique would work for this structure since feedback is present. However, it is important to note that there is no feedback from higher to lower bits. The passing of carry information therefore takes place in open loop fashion, which allows pipelining to be applied without influencing stability.
A MASH Σ-∆ converter of any order can be pipelined using the techniques thus described. Using the symbols introduced in the previous two figures, Figure 8.6 depicts a pipelined, second order MASH topology. Briefly describing its operation, each first order Σ-∆ is realized as a pipelined accumulator with feedback removed
CinCo A
B S
D D
D D
D
Co D Cin A
B S
D D
D
D Co D
Cin A
B S
A2[k]
A1[k]
A0[k]
B2[k]
B1[k]
B0[k]
S2[k]
S1[k]
S0[k]
ALIGN SHIFT SHIFTPIPE
SHIFTPIPE A[k]
B[k]
S[k]
Figure 8.4: A pipelined adder topology.
D
D Co D Cin A
B S
D D
D
Co D Cin A
B S
D
D
D Co D
Cin A
B S
X2[k]
X1[k]
X0[k]
Y2[k]
Y1[k]
Y0[k]
ALIGN SHIFT D
SHIFTPIPE
X[k] Y[k]
Figure 8.5: A pipelined accumulator topology.
from the most significant bits in its output. The output of the second stage is fed into the filter 1− D, which is implemented with two pipelined adders and a delay element, A. Note that a delay, B, is inserted between these two adders in order to pipeline their sum path, which requires a matching delay, C, in the path above for time alignment. A delay, D, must also be included in the output path of the first Σ-∆ stage to compensate for the time delay incurred through the second stage. The
8.3. DEPTH OF PIPELINING 121
complete pipelined Σ-∆ topology requires pipe shifting of its input data and align shifting of its output data as discussed above. It is useful to note that once a signal is placed in the “pipe shifted domain”, it can be sent through any number of cascaded, pipelined adders and/or accumulators. Therefore, only one pipe shift and align shift need be done in the entire structure.
6-bit ALIGN SHIFT
16-bit 6-bit 1-bit
D D
D
D D
D
10-bit 10-bit
SHIFTPIPE 16-bit
6-bit
Pipelined, 2nd order, MASH S-D Modulator
IN[k]
OUT[k]
A
B C
D
20 MHz
20 MHz
Figure 8.6: A pipelined, second order, digital MASH structure.
Figure 8.7 illustrates the implementation of the overall digital path using pipelin-ing. To achieve flexibility, the compensated digital transmit filter was implemented in software and the resulting digital data stream fed into the custom CMOS IC. Within the IC, all components are pipelined to achieve low power operation. Note that the carrier frequency signal was not pipe shifted since it is constant during modulation.
Pipelined MASH S-D
Carrier Frequency 16-bit
Pc(ej2pfT) data[k]
ROM
1-bit 10-bit
ALIGN SHIFT 6-bit PIPE D
SHIFT 16-bit
Internal to CMOS IC
2.5 MHz 20 MHz 20 MHz 20 MHz
dividerto input
data stream generated by computer in prototype
N[k]
Nnom( )
Figure 8.7: Pipelined digital data path to divider input.
8.3 Depth of Pipelining
Although the pipelining technique has been presented as the placement of registers in the carry path after each of the one-bit adders, this need not be the case. For instance, registers could be placed between every other one-bit adder. In this case, the carry information needs to pass through two stages per cycle rather than one.
Although the delay through the structure is then increased by a factor of two, the area consumed by the many registers required for pipelining is cut in half. In fact, savings in power are potentially obtained in this case if the energy consumption of the registers required for pipelining far outweighs that of the adder cells. The choice of the pipelining level should be made with respect to both area constraints and relative energy consumption within the overall system.
In the context of this work, the choice of pipelining level was made in consideration of the power of other components on the CMOS chip. Specifically, it was found that 2-bit level pipelining of the digital data path dropped its power consumption to a negligible amount in comparison to the high speed divider. Since the 2-bit approach allows an area reduction over the 1-bit approach, it was deemed the better choice for this application. Higher levels than 2-bit were not considered since the further savings in area would be minor, and could lead to higher power dissipation.
8.4 Circuit Implementation
Figure 8.8 and Figure 8.9 illustrate the dynamic TSPC registers and static adder structure used to implement the digital data path on the 0.6 micron CMOS chip.
The adder structure was designed such that its carry logic transistors were small, having roughly the same size as those implementing the sum logic. Generally, this is not the case — carry logic transistors are usually made much larger than their sum counterparts in order to speed up the carry chain. Since the carry chain has been pipelined in our case, there is no need for such large transistors. The resulting decrease in area of the adder cell somewhat alleviates the increase in area accrued by the pipelined registers. As for the registers, a dynamic topology was chosen over a static version to obtain lower area. The TSPC technique simplified the clocking scheme by allowing only one clock line.
Evaluation of the power consumption of each of the above circuits was done using the HSPICE simulation tool; the results with a 1.5 Volt supply are shown in Table 8.1.
The table reveals that the adder circuit has twice the energy consumption per opera-tion as that of the registers. For simplicity in analysis, we will conservatively assume that both types of registers consume the same power as the noninverted register.
Component Energy consumption Static adder .150 fJ/operation Noninverting TSPC register .075 fJ/operation Inverting TSPC register .056 fJ/operation
Table 8.1
Energy consumed by circuit blocks within the digital data path with a 1.5 volt supply
8.4. CIRCUIT IMPLEMENTATION 123
0.6 5.7
0.6 4.8
0.6 1.6
0.6 5.8
0.6 1.6
0.6 1.6
0.6 1.6
0.6
1.6 0.61.6
0.6 1.6 0.6 1.6 0.6 1.6 0.6
1.6 0.61.6
0.6 1.6 0.6
4.8
0.6 4.8 0.6
5.7
0.6 5.7
0.6 5.7
0.6 5.7
0.6 5.7
0.6 5.8 0.6 5.8
A
B
Cin Cout
Sum
A
A
A Cin
B B
B
A B Cin
Cin B
A A
A B
B Cin Cin
Figure 8.8: A static mirror adder circuit.
0.6 2.3
1.6 0.6
3.8 0.6
1.6
0.6 1.6
0.6 1.6
0.6 1.6
0.6 0.6
2.3
0.6 2.3
in out
clk
0.6 2.3
1.6 0.6
2.6 0.6
1.6
0.6 1.6
0.6 1.6
0.6 1.6
0.6 0.6
2.3
0.6 2.3
in out
clk
3.8 0.6
1.6 0.6
(a) (b)
Figure 8.9: Dynamic TSPC register circuits: (a) inverting, (b) non-inverting.
Table 8.2 presents a tabulation of the number of adders and registers required in the digital data path contained in the CMOS IC under pipelined and non-pipelined conditions; the numbers were obtained directly through examination of Figures 8.6 and 8.7. Energy estimates with a 1.5 V supply were computed from Table 8.1 and 8.2 as:
Adder energy: 8.1 fJ/operation, Register energy: 7.9 fJ/operation.
Given that the energy dissipation of CMOS circuits is directly proportional to the amount of capacitance switched, we see that the capacitance added by the pipelining technique is less than a factor of two over the non-pipelined case. However, a speedup of a factor of 8 is gained — the carry path must pass through 2 one-bit adders as
opposed to 16 one-bit adders per clock cycle.
Case Adders Registers
Non-pipelined 54 21
Pipelined (2-bit) 54 105 Table 8.2
Number of adders and registers for the pipelined (2-bit) and non-pipelined case of the digital data path.
Figure 8.10 displays the measured power dissipation of the Σ-∆ modulator for a range of supply voltages. The plot reveals that power dissipation increases as roughly the square of the supply voltage, which is expected since the energy required to charge capacitance C is 12CVdd2 [68].
1 1.5 2 2.5 3 3.5
0 0.5 1 1.5 2 2.5 3
Supply Voltage (V)
Power Dissipation (mW)
Power Dissipation of Σ−∆ vs. Supply Voltage
Figure 8.10: Measured power dissipation of Σ-∆ vs. supply voltage.
8.5 Summary
This chapter presented implementation details of the Σ-∆ modulator and surrounding circuits in the digital data path used in the prototype. It was shown that a well known pipelining technique for adders and accumulators can be applied to the MASH Σ-∆
structure to achieve low power operation of this component.