4. SD Memory Card Functional Description
4.14 Erase Timeout Calculation
This chapter provides the guideline for long erase and a method to calculate erase timeout value.
4.14.1 Erase Unit
The Speed Class Specification defines a new management unit of AU (Allocation Unit). Erase timeout calculation is defined as the basis of AU. SD memory card supports block erase but it takes more time to erase blocks, which are part of AU (partial erase AU). In this case, the host should add 250 ms to the result of timeout calculated on AU basis. When the start and end blocks are in the same partially erase AU, 500ms should be added.
4.14.2 Case Analysis of Erase Time Characteristics
Figure 4-10 shows an example of erase characteristics, number of AU erased versus erase time. Erase time is derived from erasing specified numbers of AUs by one erase command. Assuming that Erase is performed on AU basis and its erase characteristics can be approximated to a linear line. The line A illustrated in Figure 4-10 is an example characteristic.
The red line indicates the erase timeout value the host should use. The timeout value can be determined by line A. If the erase timeout is less than 1 second the host should use 1 second as timeout. If the timeout is bigger than 1 second the host should use the value determined by Line A.
Register parameters NERASE, TERASE and TOFFSET define the shape of the line. TERASE indicates timeout for erasing NERASE AUs from TOFFSET. TERASE and NERASE determine the slope of the line. TOFFSET adjusts the line by moving in parallel on the upper side. The card manufacturer shall determine these parameters so that the line is always greater than the erase time of any AUs.
Figure 4-10: Example Erase Characteristics (Case 1 TOFFSET=0)
0 1 2
Number of AU Erased Erase Timeout [Sec]
NERASE 1
2 3
Line A
TOFFSET
3 TERASE
The line B illustrated in Figure 4-11 shows another example of erase characteristics. The red line indicates the erase timeout value that the host should use. Since the time-out is bigger than 1 second, the red line and line B are equivalent.
Figure 4-11: Example Erase Characteristics (Case 2 TOFFSET=2)
4.14.3 Method for Erase Large Areas
The calculated erase timeout for multiple AUs might be too large compared with the actual erase time.
The calculation of erase timeout is not accurate because calculated timeout includes a margin. A margin per AU accumulates and the result of calculating the timeout for large number of AUs will include large margins. Such calculations would be meaningless because the range of margin might be in order of minutes. Therefore, a small number of AUs should be erased at one time. This enables the host to calculate smaller timeout with fewer errors.
Application Note:
When a large area is erased, the host should divide it into small areas at the AU boundary and continuously erase the small areas using a small area erase timeout. It may take a long time to erase a large area, so the host should inform the user about the erase progress, otherwise the user might abort the execution of the erase.
4.14.4 Calculation of Erase Timeout Value Using the Parameter Registers
Erase Timeout of X AU can be calculated by Equation (6).
Erase Time-out of X AU OFFSET
ERASE ERASE
T N X
T ⋅ +
=
……….…(1)Erase timeout is determined by following steps:
(1) Calculate Equation (6).
(2) If the result of (1) is less than 1 second, the timeout is set to 1 second.
(3) 250 ms should be added to the result of (2) for each partial erase AU. When the start and end blocks are in partially erase AUs, add 500 ms to the result of (2).
0 1 2
Number of AU Erased Erase Timeout [Sec]
NERASE 1
2 3
Line B TOFFSET
3 TERASE
5. Card Registers
Six registers are defined within the card interface: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands (see Chapter 4.7). The OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters.
In order to enable future extension, the card shall return 0 in the reserved bits of the registers.
5.1 OCR register
The 32-bit operation conditions register stores the VDD voltage profile of the card. Additionally, this register includes status information bits. One status bit is set if the card power up procedure has been finished. This register includes another status bit indicating the card capacity status after set power up status bit. The OCR register shall be implemented by the cards.
The 32-bit operation conditions register stores the VDD voltage profile of the card. Bit 7 of OCR is newly defined for Dual Voltage Card and set to 0 in default. If a Dual Voltage Card does not receive CMD8, OCR bit 7 in the response indicates 0, and the Dual Voltage Card which received CMD8, sets this bit to 1.
Additionally, this register includes 2 more status information bits.
Bit 31 - Card power up status bit, this status bit is set if the card power up procedure has been finished.
Bit 30 - Card capacity status bit, this status bit is set to 1 if card is High Capacity SD Memory Card. 0 indicates that the card is Standard Capacity SD Memory Card. The Card Capacity status bit is valid after the card power up procedure is completed and the card power up status bit is set to 1. The Host shall read this status bit to identify a Standard or High Capacity SD Memory Card.
The OCR register shall be implemented by the cards.
1) This bit is valid only when the card power up status bit is set.
2) This bit is set to LOW if the card has not finished the power up routine.
Table 5-1: OCR Register Definition
The supported voltage range is coded as shown in Table 5-1. A voltage range is not supported if the corresponding bit value is set to LOW. As long as the card is busy, the corresponding bit (31) is set to LOW.
OCR bit position OCR Fields Definition 0-3 reserved
4 reserved 5 reserved 6 reserved
7 Reserved for Low Voltage Range 8 reserved
9 reserved 10 reserved 11 reserved 12 reserved 13 reserved 14 reserved 15 2.7-2.8 16 2.8-2.9 17 2.9-3.0 18 3.0-3.1 19 3.1-3.2 20 3.2-3.3 21 3.3-3.4 22 3.4-3.5 23 3.5-3.6 24-29 reserved
30 Card Capacity Status (CCS)1 31 Card power up status bit (busy)2
VDD Voltage Window