Chapter 2 Low Frequency Noise Theory and Measurement Method

2.4 Low Frequency Noise Data Analysis Method

As mentioned previously, an extensive noise characterization indicates that low frequency noise (LFN) in nMOSFETs follows the number fluctuation model whereas that in pMOSFET is in better agreement with mobility fluctuation model. For MOSFETs, the measured LFN is generally expressed as normalized PSD (power spectral density) of drain current noise, denoted as SID/IDS2 to identify which model is the dominant one in the devices under test.

According to the normalized PSD derived for number fluctuation model for subthreshold, linear, and saturation regions in (2.1), (2.3), and (2.5), respectively, the SID/IDS2 is proportional to 1/IDS2 and increases linearly with oxide trap density Nt. On the other hand for the normalized PSD governed by mobility fluctuation model, expressed in (2.12) and (2.13) as a function of IDS and VGT, respectively, the SID/IDS2 is proportional to 1/IDS or 1/ VGT and independent of the oxide trap density Nt. The bias dependence suggests that increasing gate


overdrive VGT can suppress LFN. Sometimes, the experimental present VGS dependence stronger than what predicted by model. McWhorter’s carrier trapping model may provide one of mechanisms responsible for the stronger VGS dependence. The oxide trap density Nt is known to be a function of the potential energy across the band gap of semiconductor substrate.

When VGS is varied, Fermi level of the channel moves accordingly. If the number of particular traps that cause flicker noise drastically changes along with the VGS, the noise amplitude could be a stronger function of the bias. Another factor that we should take into account is the fact that carrier mobility is also a function of VGT. Regarding device scaling effect, both models reveal dependence of device dimensions in terms of 1/WLCox2, which means the channel length and width scaling will lead to increase of SID/IDS2 but the oxide thickness TOX scaling can help reduce LFN in terms of SID/IDS2

. Note that W, L, Cox, eff, H, and VGT appear as key parameters in LFN models and how to accurately extract or determine the mentioned parameters becomes critical for LFN data analysis and diagnosis. In LFN models, W and L represent effective channel width and effective channel length, rather than drawn dimensions on layout or physical dimensions from optical measurement. The accurate extraction of effective channel dimensions brings additional challenges for miniaturized MOSFETs with short channel and narrow width to sub-100 nm regimes in 90nm technology and below. STI top corner rounding (TCR) effect on effective channel width will be described in chapter 3. As for Cox, it represents the gate capacitance density per unit area, under strong inversion condition in which Cox is contributed from three major capacitances in series – gate oxide capacitance, gate depletion capacitance, and inversion channel capacitance. Again, an accurate extraction of Cox becomes difficult in miniaturized MOSFETs, due to several complicated factors like deviations in effective channel length and width, gate depletion effect, inversion channel quantization effect, and more importantly the parasitic capacitances from pads, interconnection lines, and substrate. A large device with channel length and width large


enough to minimize or even eliminate the deviation of effective channel dimensions is adopted to solve this problem. Furthermore, a dedicated open deembedding to the bottom metal, i.e. M1 is necessary to approach an accurate extraction of Cox.

The accuracy or deviation of mentioned basic device parameters will have direct impact on the determination of eff and H. Furthermore, both eff and H are a function of scattering mechanisms and biases. The bias dependence ofeff and H comes from electrical field effect on carriers transport and their scattering through the conduction channel. Note that the gate bias dependence manifests normal field effect and is expressed in terms of gate overdrive VGT=VGS -VT in which VT variations from processes, geometries, profiles, and biases can be taken into account. As shown in Fig. 2.7, the measured LFN in terms of SID/IDS2 decrease with increasing |VGT| for both NMOS and PMOS. Fig. 2.8 (a) and (b) illustrate SID/IDS2 versus VGT for NMOS and PMOS, respectively and reveal the difference of VGT dependence between NMOS and PMOS. The results can be explained by (2.3) and (2.5) for NMOS governed by number fluctuation, and (2.13) for PMOS dominated by mobility fluctuation.

Frequency dependence is one more key factor for LFN analysis and modeling. Assuming an ideal condition that trap density Nt is a constant, the frequency dependence of flicker noise will follow 1/f. However, in most of real cases, the exponent  in frequency dependence may deviate from 1 due to the fact that the trap density Nt is not uniform in depth. For the case when the trap density near the gate oxide/channel interface is higher than that in the interior of the gate oxide,  tends to be smaller than 1. For the opposite case,  may become larger than 1.

Referring to Fig. 2.7, the frequency dependence of PMOS (Fig.2.7(b)) follows 1/f very consistently but that of NMOS (Fig. 2.7(a)) reveals certain deviation from 1/f , with the exponent  < 1.

It has been a conventional belief from analog circuit design using N+ poly gate technology that PMOS has the advantage of lower flicker noise (LFN) than NMOS. It may be a truth for


buried channel PMOS, attributed to deeper channel and less surface scattering. However, the advancement of CMOS process has driven phase-out of N+ poly gate technology and deployment of dual gate technology, i.e. N+ /P+ poly gate for N/P MOSFET, since 0.25m technology node and beyond. The dual gate technology can realize surface channel for both NMOS and PMOS and help push VT scaling for low voltage operation. In this way, the advantage of PMOS over NMOS, in terms of flicker noise can no longer be maintained. Fig.

2.9 makes a comparison of measured LFN (SID/IDS2) between NMOS and PMOS under the same bias, i.e. |VGT|=0.3V and |VDS|=0.05V. As can be seen clearly that SID/IDS2 of PMOS is higher than NMOS by around one order at very low frequency (<10 Hz) and the difference decreases at higher frequency. The results suggest that conventional design using PMOS in VCO for low phase noise is no longer valid. A detailed analysis of LFN to investigate the mechanisms responsible for NMOS and PMOS and the optimization design for suppressing LFN become an important task.

NMOS and PMOS fabricated in 90nm low leakage process.


versus frequency, measured from (a) NMOS and (b) PMOS under |VGT|=0.3V and |VDS|=0.05V. NMOS and PMOS were fabricated in 90nm low leakage CMOS process.


Chapter 3

Analysis of Layout Effect on STI Stress and Device Parameters

3.1 STI stress Mechanics in RF MOSFET

Shallow trench isolation (STI) emerged to replace LOCOS as the standard isolation technology in CMOS process at 0.25 m node and below [24,25]. The technology transition proves itself the success that STI enables continuous scaling of active and isolation regions to far beyond 0.25m node, and realize higher integration level for IC design. Also, STI brings the advantages like reduced sidewall capacitance for AC performance and improved surface planarity for high integration [26]. In spite of the mentioned advantages, STI indeed introduces some other impacts, such as mechanical stress from refilled trench or known as Length of Oxide Definition (LOD) stress-effect [27,28]. The STI stress may have a significant influence on MOSFETs’ electrical characteristics, such as threshold voltage (VT), carrier effective mobility (eff), transconductance (Gm), gate speed, cut-off frequency (fT), and low frequency noise, etc. The mentioned impacts always increase with devices scaling and becomes the key factors of consideration in MOSFETs layout for integrated circuit design, particularly for RF and analog circuits of our focus in this thesis.

The STI module implemented in standard CMOS processes from 0.25m to 65nm nodes generally introduce compressive stress, either along or transverse to the channel length, i.e. the current flow direction. The stress along the channel length is defined as longitudinal stress //, and that transverse to the channel length is denoted as transverse stress. The reverse type of stress, namely tensile stress will introduce its influence in the opposite direction with that of compressive stress. The impact from STI stress on device characteristics is strongly dependent on the device types and orientations. Table 3.1 summarizes the stress favorable for mobility enhancement and reveals fundamental differences between NMOS and PMOS. For NMOS, tensile stress, either // or  can


improve eff. As for PMOS, compressive stress in // or tensile stress in  is the right one for eff enhancement [29]. The results indicate that compressive stress in transverse direction, i.e.  along the channel width always leads to mobility degradation in both NMOS and PMOS. It means that channel width scaling will result in Gm degradation due to eff

degradation under the condition that STI stress is the only one factor influencing eff. However, the experimental from a comprehensive coverage of narrow device layouts reveals an interesting result that an increase of effective channel width, namely W from STI top corner rounding (TCR) emerges as an anti-factor, which will trade off with eff degradation from STI stress in determining Gm. The details will be described in sections 3.4 and 3.5.


Compressive  //

Tens ile

x y


Compressive  //

Tens ile

x y

Figure 3.1 Schematic views of stress types and orientations

Table 3.1 Stress favorable for mobility enhancement in NMOS and PMOS along longitudinal and transverse directions [29]







Tensile Compressive




Tensile Tensile

Stress favorable for mobility enhancement


3.2 MOSFET Layouts for STI stress Modulation

(Multi-finger, Multi-OD, and Doughnut Structures)

In this work, MOSFETs with various layouts were fabricated in 90nm low leakage CMOS process with nitrided oxide of target physical thickness at 2.2nm. The gate length drawn on the layout is 90nm, i.e. Ldrawn=90nm and the total channel width Wtot are specified at 32 m or 64 m. To investigate STI transverse stress effect, two new layouts derived from multi-finger MOSFET, namely narrow-OD and multi-OD MOSFETs with extremely narrow widths were designed and implemented. Note that OD means oxide diffusion, which is equivalent to active area, generally denoted as AA.

Fig. 3.2 displays narrow-OD MOSFET layouts in which gate finger numbers (NF) and finger width (WF) are varied simultaneously to keep WF×NF=Wtot. In this work, three splits of WF×NF, namely W2N16 (WF×NF=2m×16), W1N32 (WF×NF=1m×32), and W05N62 (WF× NF=0.5m×64) corresponding to Wtot=32m were fabricated, as shown in Fig. 3.2(a)~(c). The multi-OD MOSFETs shown in Fig.3.3 represent multiple OD fingers with simultaneously varied OD finger width (WOD) and OD finger number (NOD) under a specified finger width, which is WF=WOD×NOD. As shown in Fig. 3.3(a)~(c), three splits of layout, namely OD1 (WOD × NOD=2m×1), OD8 (WOD × NOD=0.25m×8) and OD16 (WOD×NOD=0.125m×16) are designed corresponding to WF=2m and NF is fixed at 16. Note that the poly-gate edge to OD edge distance along the direction of channel length is fixed at 0.5m for both narrow-OD and multi-OD MOSFETs.


(a) W2N16 (b) W1N32 (c) W05N64


Fig.3.2 Schematics of narrow-OD MOSFETs with three layouts (a) W2N16 (WF×NF=2m×16) (b) W1N32 (WF×NF=1m×32) (c) W05N62 (WF×NF=0.5m×64) corresponding to Wtot=32m

2um 0.25um


2um 0.25um


(a) OD1 (b) OD8 (c) OD16

Fig.3.3 Schematics of multi-OD MOSFETs with three layouts (a) OD1 (WOD × NOD=2m×1) (b) OD8 (WOD × NOD=0.25m×8) (c) OD16 (WOD×NOD=0.125m×16)


Besides the multi-finger MOSFETs, a new MOSFET layout, namely doughnut (donut) is proposed to create devices free from STI transverse stress , along the channel width. As shown in Fig. 3.4, donut MOSFETs are constructed as 4-side polygons in which the corners contribute very little to the channel current [30]. In this thesis, donut devices with two layout dimensions were implemented. In Fig. 3.4(a), D1S1 represents donut MOSFET in which the space from poly gate to STI edge follows the minimum rule, i.e. 0.3m, to maximize the compressive stress from STI along the channel (i.e., longitudinal stress //). Meanwhile, D10S10 shown in Fig. 3.4(b) denotes donut MOSFET with 10 times larger space between poly gate and STI edge, i.e. 3m, intentionally to relax // from STI.

In the following section, an extensive characterization has been performed on both NMOS and PMOS devices to explore the STI stress effect on channel current (IDS), transconductance (Gm) and effective mobility (eff).






Fig.3.4 A brief layout of donut MOSFET with two major layers, such as active region (OD) and poly gate (PO) (a) D1S1 (poly gate to STI edge distance =0.3m (min. rule) (b) D10S10 (poly gate to STI edge distance =3m=10x min. rule), 4-side polygons length is 16 m x4.

3.3 Layout Effect on DC Characteristic

Regarding layout dependent STI stress effect on electrical characteristics of MOFSETs, DC characteristics such as I-V, VT, and Gm are the most fundamental ones to be verified.


Besides the mentioned DC characteristics, effective mobility µeff is the most important parameter to be extracted for investigating STI effect on carrier transport. At first, I-V characterization was performed using HP4156B Semiconductor Parameter Analyzer. For the extraction of µeff, I-V characteristics in linear region and C-V characteristics from high frequency S-parameter measurement have been carried out. Note that an accurate extraction of intrinsic gate capacitance is indispensable for accurate determination of inversion carriers density Qinv, which is required for µeff extraction.

In the following, the effective mobility µeff is extracted from linear I-V under very low drain bias VDS (|VDS|=0.05V in this work) and Qinv determined by intrinsic gate capacitance from S-parameters through an appropriate deembedding. In this work, S-parameters were measured by Agilent network analyzer E8364B for high frequency characterization up to 40 GHz and AC parameters extraction. Open de-embedding was performed on the measured two-port or four-port S-parameters to remove the parasitic capacitances from the pads as well as interconnection lines and short de-embedding was done to eliminate the parasitic resistances and inductances originated from the metal interconnection lines.

where, Leff and Weff are the effective channel length and width of the intrinsic channel region;

VDS0 is the internal drain voltage, which is applied to the intrinsic channel excluding the parasitic drain and source resistances, given by

 

0 - ( )


V V I R R (3.2) Assume that IDS (RD+RS) << VDS at VDS= 0.05V to simplify the problem and easily derive µeff as follows (an example for NMOS, and an opposite sign for all biases for PMOS)

DS 1

29 note that (3.4) is valid under strong inversion condition, i.e.

  


Cox(inv) is the intrinsic gate capacitance density per unit area, under strong inversion condition, which can be calculated by intrinsic Y-parameters (Im(Y11)) from S-parameters after an open deembedding to the bottom metal, i.e. M1

,int ,int

For a long-channel and wide width MOSFET

, 1 validate the equivalence of drawn dimension and physical dimension, i.e.

eff , g


Once we have obtained accurate values of the effective mobility µeff, we will be at a position for analyzing the possible mechanisms responsible for the mobility enhancement or degradation in MOSFETs. However, the Cgg(DUT) extracted after an open deembedding contains not only inversion channel but also fringing capacitances from gate sidewall and finger ends, which cannot be removed even after an open deembedding to M1 (openM1).

These gate related fringing capacitances are not scalable with the scaling of device dimensions, such as gate length and width. As a result, the fringing capacitances occupy a significant rate in Cgg(DUT) and may dominate that from intrinsic channel region in very short


and/or very narrow MOSFETs. Under this condition, the inversion carrier calculated directly by Cgg(DUT) will be overestimated and then the extracted µeff is underestimated. The increase of Weff from STI TCR, namely W and an accurate extraction of W from I-V and C-V methods will be described in sections 3.4 and 3.6. Through an appropriate correction on Weff, which is indispensable for very narrow MOSFETs, the µeff can be accurately extracted for narrow-OD and multi-OD MOSFETs to clarify STI stress effect or STI TCR induced W effect. The methods developed in this thesis can facilitate a rigorous investigation on the mechanisms responsible for mobility enhancement or degradation in miniaturized MOSFETs.

The STI stresses introduced in MOSFETs with standard and narrow-OD layouts (Fig. 3.2) are illustrated in Fig. 3.5 to assist an analysis and understanding of layout effect on STI stress and the electrical characteristics. Note that STI stress is classified as longitudinal stress, denoted as //, which is in parallel with the channel length, and transverse stress, namely , which is transverse to the channel length. In this work, the longitudinal stress // is considered to be similar for all of devices with various layouts, due to fixed gate length and poly gate edge to OD edge distance [31]. Referring to Table 3.1, the stress favorable for electron mobility in NMOS is tensile stress in both longitudinal direction (//) and transverse direction (). However, the stress favorable for hole mobility in PMOS becomes compressive stress in longitudinal orientation (//) but keeps tensile stress in transverse direction () [29].





(a) (b)


Fig.3.5 Schematics of STI stresses along the longitudinal and transverse directions, defined as

// and  in MOSFETs with different layouts (a) standard multi-finger MOSFET (b) narrow-OD MOSFET

It has been known that STI process generally leads to VT lowering with channel width scaling and it is the so called inverse narrow width effect (INWE) [32]. As shown in Fig. 3.6, the VT vs. WOD for narrow-OD NMOS present an obvious INWE. Note that INWE is determined by collective effects from doping profile, 2D charge sharing effect, trench corner field crowding, STI stress, and STI TCR (W), etc. Considering VT variations from the mentioned effects, VGT =VGS-VT is used for electrical characterization and analysis. Fig. 3.7 presents the drain current (IDS) and transconductance (Gm) under varying VGT, measured from narrow-OD NMOS with two splits, such as W1N32 (1m×32) and W05N64 (0.5m×16) and the standard one W2N16 for a comparison. The results indicate that the smaller WOD (=WF) leads to lower Gm and also the maximum Gm (Gm,max). It is found that Gm,max of W1N32 (WOD=WF=1m) is degraded by around 2% but that of W05N64 (WOD=WF=0.5m) is degraded by as large as 8%, compared with the standard NMOS, i.e. W2N16 (WOD=WF=2m). The monotonic degradation of Gm with WOD scaling in narrow-OD devices suggests that the increase of STI compressive  is the dominant factor responsible for eff degradation and the resulted Gm degradation.

0.5 1.0 1.5 2.0

0.50 0.52 0.54 0.56 0.58

Narrow-OD NMOS VDS=50mV, VBS=0V

V T (V)


Fig.3.6 Linear VT versus WOD for narrow-OD NMOS with various layouts like W2N16

32 characteristics. Again, STI stress is classified as longitudinal stress, denoted as //, which is in parallel with the channel length, and transverse stress, namely , which is transverse to the channel length.

Fig.3.8 Schematics of STI stresses along the longitudinal and transverse directions, defined as


// and  in MOSFETs with different layouts (a) standard multi-finger MOSFET (b) multi-OD MOSFET with multiple OD finger and multiple gate finger.

For multi-OD NMOS, the VT vs. WOD shown in Fig. 3.9 indicates a strong INWE with VT fall-off to 0.42V for OD16 with the minimal WOD to 0.125m. Again, INWE is determined by combined effects from doping profile, 2D charge sharing effect, corner field crowding, STI stress, and STI TCR (W), etc. Note that the WOD dependence of VT for narrow-OD and multi-OD NMOS actually follow a universal curve in VT vs. WOD. Again, Fig. 3.10 presents the IDS and Gm under varying VGT measured from multi-OD NMOS with two splits, such as OD8 (NOD=8, WOD =0.25m) and OD16 (NOD=16, WOD =0.125m) and their comparison with the standard one, i.e OD1 (NOD=1, WOD =2m). The results indicate that the Gm,max of OD8 is degraded by around 20% as compared to OD1 but the continuous scaling of WOD to 0.125m in OD16 leads to an increase of Gm compared to OD8 and the Gm,max degradation compared to OD1 is shrunk to 11%. The result looks very interesting and cannot be explained by STI compressive stress alone.

0.1 1

0.40 0.45 0.50 0.55 0.60

OD16 (0.125m) OD8 (0.25m)

OD1 (2m) Multi-OD NMOS

VDS=50mV, VBS=0V

V T (V)


Fig.3.9 Linear VT versus WOD for multi-OD NMOS with various layout dimensions : OD1 (NOD=1, WOD=2m), OD8 (NOD=8, WOD=0.25m), and OD16 (NOD=16, WOD=0.125m). Bias condition : VDS=50mV and VBS=0V.


As for donut MOSFET with the layouts shown in Fig. 3.4, the STI stresses introduced in this donut device is illustrated in Fig. 3.11 (b). Through a comparison with that of standard multi-finger MOSFET in Fig. 3.11(a), the major difference is that donut layout can keep the MOSFET free from STI transverse stress , along the channel width and eliminate the impact from  on mobility. Another difference is that the channel current in donut MOSFETs

As for donut MOSFET with the layouts shown in Fig. 3.4, the STI stresses introduced in this donut device is illustrated in Fig. 3.11 (b). Through a comparison with that of standard multi-finger MOSFET in Fig. 3.11(a), the major difference is that donut layout can keep the MOSFET free from STI transverse stress , along the channel width and eliminate the impact from  on mobility. Another difference is that the channel current in donut MOSFETs

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