Conclusions and Future Works
8.2 Future Works
The large power consumption in the ADC’s prototype which was not optimized is the major drawback which needs to be improved. The capacitors and the biasing currents of the pipeline stages should be scaled further from the first stage to the last stage according to the resolution requirements of the dedicated pipeline stage under the scaling. The minimum capacitor size can be determined according to the thermal noise requirement.
The minumum power dissipation will be set by the minimum size of capacitor of each pipeline stage [61].
The performance of high-resolution time-interleaved ADCs is often significantly de-graded by timing mismatch errors. Low-complexity techniques for estimating unknown time skew parameters and for correcting the output signal from these estimates should be developed.
Methodologies for improving the SNR should be investigated when the SNR perfor-mance is an issue, especially implemented in the low-voltage progressive technology.
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Vita
Zwei-Mei Lee was born in Tau-Yuan, Taiwan, in 1976. She received the B.S.E.E.
degree from National Central University, Chung-Li, Taiwan, in 1998, and the M.S.E.E. degree from National Chiao-Tung University, Hsin-Chu, in 2000. She worked toward the Ph.D. degree in electronic engineering at National Chiao-Tung University. From 1999 to 2000, she was a full-time teaching assistant in electronic engineering at National Central University.
Her research interests are high-performance data converters and VLSI designs.
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