Intrinsic Device and Parasitic RLC Parameters Extraction and Analysis

在文檔中 射頻金氧半場效電晶體元件佈局對高頻特性與低頻雜訊之影響以應用於射頻與類比電路 (頁 98-0)

Chapter 5 RF MOSFET Layout Effect on High Frequency Characteristics

5.2 Two-port 3T MOSFET with Multi-finger, Multi-OD, and Doughnut Structures

5.2.1 Intrinsic Device and Parasitic RLC Parameters Extraction and Analysis

The intrinsic gate resistance obtained by Y-method of standard and doughnut were extracted at VDS= 1.2V and VGS= 1V are plotted in Fig. 5.2 From the extracted Rg at various frequencies, we can find easily it is frequency independent and does not appear non-quasi-static (NQS) effect because of sufficient high frequency and short channel.

0 5 10 15 20 25 30 35 40 45

0 50 100 150 200 250 300

350 90nm W2N32 NMOS

VDS=1.2V, VGS=1V Std

D1S1 D10S10

Rg (Ohm)

Frequency (Ghz)

Fig. 5.2 The extracted Rg of standard and doughnut devices as a function of frequency with

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VDS= 1.2V, VGS= 1V

Fig. 5.3 and Fig. 5.4 shows the extracted Rg for NMOS and PMOS with standard and doughnut devices at saturation region. We can see Rg shows very weak gate bias dependence for short channel devices. Based on above results, we can see there is no different between Y-method and Z-method extracting results, and thus we can confirm the exact value of poly gate resistance for different test patterns.

0.8 0.9 1.0 1.1 1.2

Fig. 5.3 Comparison of (a) Z-method and (b) Y-method Rg extraction for NMOS standard and doughnut devices

Fig. 5.4 Comparison of (a) Z method and (b) Y method Rg extraction for PMOS standard and doughnut device

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Table. 5.1, table. 5.2, and table. 5.3 is the parameter values which are for the gate resistance optimization of Z-method. The calculated Ag and B are mainly from the parameter gds, Cgg, Cgd, Cgs, gm, and Cds. The used devices are standard multi-finger W2N32, D1S1, and D10S10, including N type and P type MOSFETs.

Table. 5.1 The optimized parameters (Ag and B) for Z method Rg extraction of standard W2N32 device

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (S) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz 0.8 3.38E-03 7.68E-14 2.49E-14 5.19E-14 4.26E-02 1.89E-14 ####### ####### 7.07 0.9 4.06E-03 7.87E-14 2.51E-14 5.36E-14 4.68E-02 1.79E-14 ####### ####### 5.74 1 4.63E-03 8.00E-14 2.53E-14 5.47E-14 4.87E-02 1.72E-14 ####### ####### 4.85 1.1 5.15E-03 8.10E-14 2.56E-14 5.54E-14 4.92E-02 1.67E-14 ####### ####### 4.17 1.2 5.65E-03 8.17E-14 2.59E-14 5.58E-14 4.89E-02 1.63E-14 ####### ####### 3.59 Average 5.08 NMOS standard W2N32 bias dependent with vary Vgs (Vds=1.2V)

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (S) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz -0.8 3.84E-03 7.16E-14 2.39E-14 4.78E-14 1.60E-02 2.77E-14 4.42E+22 6.34E+23 5.91 -0.9 4.37E-03 7.28E-14 2.43E-14 4.86E-14 1.84E-02 2.78E-14 5.70E+22 7.07E+23 5.88 -1 4.88E-03 7.39E-14 2.47E-14 4.92E-14 2.01E-02 2.81E-14 6.78E+22 7.40E+23 5.65 -1.1 5.45E-03 7.47E-14 2.52E-14 4.95E-14 2.13E-02 2.81E-14 7.96E+22 7.40E+23 5.19 -1.2 5.96E-03 7.56E-14 2.58E-14 4.98E-14 2.21E-02 2.81E-14 8.96E+22 7.20E+23 4.71 Average 5.47 PMOS standard W2N32 bias dependent with vary Vgs (Vds= -1.2V)

Table. 5.2 The optimized parameters (Ag and B) for Z method Rg extraction of doughnut D1S1 device

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (S) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz 0.8 3.11E-03 7.73E-14 2.15E-14 5.57E-14 4.26E-02 2.58E-14 1.31E+23 1.96E+24 10.06 0.9 3.75E-03 7.93E-14 2.17E-14 5.76E-14 4.68E-02 2.48E-14 1.67E+23 1.98E+24 8.62

1 4.31E-03 8.05E-14 2.19E-14 5.85E-14 4.87E-02 2.42E-14 1.92E+23 1.95E+24 7.65 1.1 4.81E-03 8.15E-14 2.22E-14 5.93E-14 4.92E-02 2.36E-14 2.10E+23 1.85E+24 6.79 1.2 5.30E-03 8.22E-14 2.26E-14 5.96E-14 4.89E-02 2.33E-14 2.23E+23 1.75E+24 6.11 Average 7.85 NMOS doughnut D1S1 bias dependent with vary Vgs (Vds=1.2V)

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Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (S) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz -0.8 3.85E-03 7.06E-14 2.34E-14 4.72E-14 1.69E-02 2.67E-14 4.98E+22 7.06E+23 6.25 -0.9 4.27E-03 7.22E-14 2.38E-14 4.84E-14 1.97E-02 2.69E-14 6.31E+22 8.04E+23 6.37 -1 4.66E-03 7.34E-14 2.43E-14 4.92E-14 2.16E-02 2.72E-14 7.37E+22 8.53E+23 6.23 -1.1 5.05E-03 7.44E-14 2.48E-14 4.96E-14 2.30E-02 2.74E-14 8.38E+22 8.81E+23 6 -1.2 5.44E-03 7.51E-14 2.53E-14 4.98E-14 2.39E-02 2.75E-14 9.28E+22 8.84E+23 5.67

Average 6.1 PMOS doughnut D1S1 bias dependent with vary Vgs (Vds= -1.2V)

Table. 5.3 The optimized parameters (Ag and B) for Z method Rg extraction of doughnut D10S10 device

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (A/V) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz 0.8 2.83E-03 7.82E-14 2.49E-14 5.33E-14 4.75E-02 3.33E-14 1.28E+23 2.31E+24 12.09 0.9 3.50E-03 7.99E-14 2.51E-14 5.48E-14 5.12E-02 3.27E-14 1.54E+23 2.34E+24 10.78 1 4.07E-03 8.10E-14 2.54E-14 5.56E-14 5.27E-02 3.21E-14 1.73E+23 2.31E+24 9.8 1.1 4.58E-03 8.18E-14 2.57E-14 5.61E-14 5.29E-02 3.14E-14 1.87E+23 2.24E+24 8.97 1.2 5.08E-03 8.25E-14 2.60E-14 5.65E-14 5.23E-02 3.07E-14 1.98E+23 2.14E+24 8.21 Average 9.97 NMOS doughnut D10S10 bias dependent with vary Vgs (Vds=1.2V)

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm

(A/V) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz -0.8 2.98E-03 7.12E-14 2.32E-14 4.80E-14 1.69E-02 3.22E-14 3.15E+22 8.02E+23 8.48 -0.9 3.65E-03 7.26E-14 2.36E-14 4.90E-14 1.94E-02 3.11E-14 4.48E+22 8.59E+23 7.96 -1 4.28E-03 7.36E-14 2.41E-14 4.95E-14 2.13E-02 3.01E-14 5.91E+22 8.91E+23 7.29 -1.1 4.90E-03 7.46E-14 2.47E-14 4.99E-14 2.26E-02 2.93E-14 7.30E+22 8.83E+23 6.49 -1.2 5.52E-03 7.54E-14 2.53E-14 5.01E-14 2.34E-02 2.87E-14 8.63E+22 8.49E+23 5.68 Average 7.18 PMOS doughnut D10S10 bias dependent with vary Vgs (Vds= -1.2V)

Narrow-OD Rg with Z-method and Y-method were extracted and plotted as a function gate bias, as shown in Fig. 5.5 that were obtained by the two methods are compared. Similar values were obtained for W2N16, which has the minimum finger number here. But for the W1N32 and W05N64, a slight difference between Z-method and Y-method. The lowering of Rg by Y-method attribute to the term in the denominator of 2

11 11

Re(Y )/Im(Y ) , this capacitive components become higher due to the poly gate to metal coupling introduced by poly gate to metal coupling capacitance, which is not clean enough for open metal3 de-embedding result.

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And this can be improved by applying metal1 de-embedding but will be at a significantly cost of chip area

Fig. 5.5 Comparison of (a) Z method and (b) Y method Rg extraction for NMOS narrow-OD device

As discussed before, the Rg lowering effect is fine and acceptable for narrow-OD devices with Y-parameter. But for multi-OD with even larger extrinsic parasitic capacitance, the Rg is dramatically different between there two method. Multi-OD Rg with Z-method and Y-method were extracted and plotted as a function gate bias, as shown in Fig. 5.6 that were obtained by the two methods are compared. Similar values were obtained for OD1 and OD8, which has nearly the same poly width here. But for OD16, a significant difference between Z-method and Y-method occurs and a totally different trends. The Y-method Rg of OD16 even lower than OD1. Same as narrow-OD devices, the lowering of Rg by Y-method attribute to the term in the denominator of 2

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the comparison result that the Z-parameter is suitable and more accurate than Y-parameter in most of the conditions and test patterns.

0.8 1.0 1.2

Fig. 5.6 Comparison of (a) Z method and (b) Y method Rg extraction for NMOS multi-OD device

5.2.2 High Frequency Performance Analysis (fT, fMAX, and NFmin)

A model for the high frequency figures-of-merit can be derived based on the small signal equivalent circuit includes gate resistance (Rg), gate-source (Cgs), gate-drain (Cgd), gate-body (Cgb) capacitances, transconductance (Gm), body resistance (Rbb), and junction capacitance (Cdsb). Previous studies [67] have ignored the presence of Cgb, but it will affect the fT and unilateral gain significantly, even with a small value that arises from fringing capacitance.

The cut-off frequency fT and Maximum oscillation frequency fMAX are the most important figures of merit for the frequency characteristics of RF transistors. They are often used to emphasize the superiority of newly developed semiconductors or technologies. The value of fMAX can be determined by the unilateral power gain Ugain as defined by [68].

2

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Where K is Kurokawa’s stability factor[] defined as

where We can also expressed in the Y-parameter

   

Therefore, fMAX is the Maximum frequency at which the transistor still provides a power gain. An ideal oscillator would still be expected to operate at this frequency, hence the name Maximum oscillation frequency. Like the short circuit current gain H21, Ugain drops with a slope of -20dB/dec.

fMAX does not have to necessarily larger than fT. Generally, transistors have useful power gains up to fMAX, that above they cannot be used as power amplifiers any more. However, the importance of fT and fMAX depends on the specific application. Thus, there is no general answer whether fMAX should be prioritized over fT. Both figures should be as high as possible, and manufactures often strive for fT~fMAX in order to enter many different application for their transistors.

The impact from layout dependent STI stress on high frequency performance is crucial for RF MOSFETs and circuits design. Fig. illustrates the cutoff frequency fT measured from NMOS with multi-OD layouts. (Noted that fT is extracted from extrapolation of |H21| to unity gain).

The impact from layout dependent STI stress on high frequency performance is of special concern for RF MOSFETs and circuits design. Fig. 5.7 illustrates the cutoff frequency fT measured from NMOS with multi-OD layouts. (Note that fT is extracted from extrapolation of short circuit current gain |H21| to unity gain). H21 basically characterizes the ratio between the

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small-signal drain and gate current |ID/IG|. The cut-off frequency is normally extracted for various operating points.

It is found that OD1 gains the highest fT while the OD16 reveals itself the worst one. An analytical model for calculating fT, it is predicted that fT is proportional to Gm and the enhancement of Gm can boost fT under fixed gate capacitances (Cgg and Cgd). Fig.5.13 (b) present Cgg measured from multi-OD layouts. The results indicate that OD16 gets larger Cgg and smaller Gm as compared to OD1. Thus, layout dependence of fT just follows those of both Cgg and Gm.

Regarding other RF performance parameters, such as maximum oscillation frequency, fMAX and noise figure, NFmin (not shown), the OD16 MOSFETs suffer significant degradation due to inherently larger gate resistances.

0.2 0.4 0.6 0.8 1.0 1.2

Fig. 5.7 (a) The cut-off frequency fT versus VGT measured for multi-OD devices(b) Cgg versus VGS extracted from Y-parameters for multi-OD devices

The second important RF figure of merit is the Maximum oscillation frequency fMAX, which is related to the frequency at which the device power gain equals unity. The high frequency Ugain and fMAX, on the other hand, are independent of Cgb, but are influenced by the pole formed by Cdb. Since fMAX are relatively insensitive to the change in body resistance, it makes sense that the power characteristics are also insensitive to body resistance. But the

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impact of body resistance on unilateral gain is an important consideration for designers. The unilateral power gain, on the other hand, can depend on the body resistance. We used experimental data to verify the relationship between fT and fMAX.

2 ( ) 2

Fig. 5.8 (a) Ugain and (b) fMAX extraction for multi-OD NMOS

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Fig. 5.9 (a) Ugain and (b) fMAX extraction for narrow-OD NMOS Standard and Doughnut device comparison

The impact from layout dependent STI stress on high frequency performance is of special concern for RF MOSFETs and circuits design. Fig. 5.10 (a) and (b) illustrate the cutoff frequency fT measured from NMOS and PMOS with donut and standard layouts. Note that fT is extracted from the extrapolation of |H21| to unity gain. For NMOS in Fig. 5.10 (a), D10S10 gains 5% improvement in the Maximum fT compared to the standard and D1S1. The benefit from donut layout becomes particularly larger for PMOS. As shown in Fig. 5.10 (b), D1S1 presents the best performance with the highest fT and realizes 28% increase in the Maximum fT than the standard device.

Fig. 5.10 The cut-off frequency fT vs. Vgs measured for standard and donut devices (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.

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Fig. 5.11 Cgg vs. Vgs extracted from Y-parameters for standard and donut devices (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.

Regarding other RF performance parameters, such as maximum oscillation frequency, fMAX and noise figure, NFmin, the donut MOSFETs suffer significant degradation due to inherently larger gate resistances than the standard one with multiple gate fingers. The experimental suggests an innovative donut device layout is required to cover all of the RF and analog performance. Normally, noise parameters are measured using a relatively complicated system that measured both noise and S-parameters of the device under test (DUT) and these measurements are very time consuming.

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An analytical method to extract the HF noise parameters of the MOSFET directly has been recently presented in [69]. Direct measurement of the noise parameters requires considerable amount of time since. The noise performance of any noisy two-port network can be represented by:

Where Fmin is the minimum noise factor (the minimum noise factor in dB is called minimum noise figure), which is defined as the signal-to-noise ratio at the input port divided by the signal-to-noise ratio at the output port of the noisy two-port. Rn is the equivalent noise resistance, Ys ( = Gs+ jBs) is the source admittance and Ysopt (= Gsopt+ jBsopt) is the optimum source admittance which result in the Fmin. The best noise figure in a circuit is achieved when the device is presented with optimum source impedance. The optimum input network to achieve this objective does not in general result in an excellent return loss match. Balanced amplifiers and isolators are sometimes used to achieve both the optimum noise figure and a good match.

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Fig. 5.12 Comparison of NFmin measurement result of standard and doughnut devices of NMOS (left) and PMOS (right).

Fig. 5.13 Comparison of Rn measurement result of standard and doughnut devices of NMOS (left) and PMOS (right).

Fig. shows the measured values of all four noise parameters of the device versus frequency at Vgs= 1V and Vds= 1.2V. It is observed that Rn does not vary much with frequency, but the doughnut devices have markedly difference Rn between standard multi-finger devices, which can be seen that the gate resistance have a great impact on noise resistance. The Rn of doughnut is D1S1 about 7 times larger than standard and we can verify it from the following relation formula:

91 is observed that Rn shows no difference among three devices, NFmin is the worst for W05N64 but not that critical for a normal condition. It is believed that the multi-finger type transistors in 90nm technology are well-controlled at HF noise behavior.

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Fig. 5.15 Comparison of noise parameters measurement result of standard and narrow-OD devices, (a) NFmin (b) Rn

Fig. 5.16 Comparison of noise parameters Re(Ysopt) and Im(Ysopt) measurement result of standard and narrow-OD devices

The difference of RF noise parameters from layout variation in narrow-OD NMOS is not obvious, whereas the multi-OD devices have a totally different performance with respect to the narrow-OD ones, as shown in Fig. 5.17. The OD16 with 0.125um OD width has the worst NFmin, but the noise resistance of OD16 is not the largest one. The OD8 has a totally different slope of NFmin versus frequency compared to OD1 and OD16, and the noise resistance of OD8 is the largest one. For the frequency under 10Ghz, the NFmin of OD8 is higher than OD1,

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when the frequency higher than 10Ghz, the NFmin of OD1 exceed the OD8. As a summury, OD16 with middle Rn but the worst parasitics effect (mainly from Cgs) make it NFmin worse than OD1 and OD8.

Fig. 5.17 Comparison of noise parameters measurement result of standard and multi OD devices, (a) NFmin (b) Rn (c) Re(Ysopt) and Im(Ysopt)

5.3 Four-port 4T MOSFET with various Body Contact Layouts

Accurate extraction and modeling of the body network is of utmost importance in RF regime and application to CMOS RF circuit design [70-72]. However, in the conventional 2-port RF test structure used for extraction of elements of the body model, the source terminal is invariably shorted to body. Body network shunts the source junction making extraction of its capacitance difficult.

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The four-port RF MOSFET test structure related to body pattern and device characterization were implemented in this section to alleviate these problems and help in accurately extracting the body networks. We proposed eight structures which include each type of body contact shape.

Due to the analytical expressions for body parameter modeling based on device geometry, we proposed each kind of layout with different body pickup. The conventional ring-shaped body contacts, we called it standard briefly. We usually approximate it to body coupling in vertical and horizontal directions, and it was the most common used structure in many works.

The other structures include only side body contacts such as parallel and perpendicular, which means the body contacts are parallel or perpendicular to the gate fingers, and then the body coupling only in one side and less area of body contacts.

We also proposed some body shapes which are not in symmetry such as L-shape contacts and U-shape contacts which may reveal some interesting outcome of body network parameters compared with the above different types layout.

The third kind layout, we split the body contacts into multi-ring and the total width (Wtotal), finger number (Nf), and channel length (Lg) are the same as standard type(ring-shape) in this work. The detailed description and classification were shown in the following table.

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Table. 5.4 The layout view and classification of each kind body contacts

Structure Layout Description

Standard The ring-shape

Body and N-well contact.

2-rings Body contact split into 2

group and ring-shape

N-well contact.

4-rings Body contact split into 4

group and ring-shape

N-well contact.

8-rings Body contact split into 8

group and ring-shape

N-well contact.

U shape U-shape body and N-well

contact.

L shape L-shape body and

N-well contact.

Parallel Body and N-well contact

parallel to poly-gate

fingers.

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Perpendicular Body and N-well contact

perpendicular

to poly-gate fingers.

5.3.1 Four-port De-embedding Method

The 4-port here has the same analytical de-embedding method for 2-port. The following equation is the matrix de-embedding method for 4-port devices:

_

meas o meas open

YYY (5.26)

_

short o short open

YYY (5.27)

1 1 1

_ _ (( ) ( ) )

dut meas o short o meas open short open

ZZZYY YY (5.28)

Thus, according to the above, the procedures of the two step de-embedding technique can be given as follows. First, we obtain the s-parameters (Smeas, Sopen, and Sshort) for DUT, open and short test structures and convert them to Y parameters (Ymeas, Yopen, and Yshort). Then perform the first step de-embedding by removing the parallel parasitics from both YDUT and Yshort according to the following equations

_

meas o meas open

YYY (5.29)

_

short o short open

YYY (5.30)

The last step of de-embedding is to perform the second de-embedding by removing the series parasitics Zshort_o, converting from Yshort_o, from Zmeas_o, converting from Ymeas_o according to the following equation

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_ _

DUT meas o short o

ZZZ (5.31) 5.3.2 Intrinsic Device and Parasitic RLC Parameters Extraction and

Analysis – Body Contact Layout Effect and Bias dependence

As shown in the table, A 2*32um device with standard body layout is selected as a may cause the Cjd and Cjs lowering. The Fig. shows the source and drain junction capacitance Cjs and Cjd of standard, U shape, and L shape body contact layout. It is easily found that for the Cjs and Cjd without applied Rbb calibration, the capacitance at frequency higher than 500 Mhz dramatically drops because of the term 2(CjdCjs)2Rbb2 get higher. The phenomenon

Fig. 5.18 Cjs extraction versus frequency (a) without Rbb calibration and (b) after Rbb

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Fig. 5.19 Cjd extraction versus frequency (a) without Rbb calibration and (b) after Rbb calibration

Table. 5.5 Cjs extraction versus Vgb extraction

Vbs(V) Cjs(standard) Cjs(2-rings) Cjs(4-rings) Cjs(8-rings)

-0.6 2.67E-14 2.88E-14 3.32E-14 4.21E-14

0 3.50E-14 3.80E-14 4.34E-14 5.48E-14

0.6 9.50E-14 1.05E-13 1.24E-13 1.63E-13

Table. 5.6 The increment of Cjs with the body ring number increased

-0.6 7.87 16.5 33.3

0 8.57 15.4 32.57

0.6 10.5 20 41.05

Equation (Cjs_R2- Cjs_std)/ Cjs_std (Cjs_R4- Cjs_R2)/ Cjs_std (Cjs_R8- Cjs_R4)/ Cjs_std

Vbs(V) Capacitance of 4-rings

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Fig. 5.20 Cgs and Cgd extraction versus frequency of ring type body contact layout

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6

Fig. 5.21 Cjs extraction versus frequency of ring type body contact layout

Fig. shows the measured Csdb and Cbsd as a function of body bias Vbs for 1 ring and 8-Rings body contact layout devices. For a zero gate bias, the measured capacitance decreases with increasing junction reverse bias (Vbs< 0) due to the increase of the depletion widths of the individual junction components. It can also be seen that at Vgb= 0V (Vgs= Vbs= 0), corresponding to a depleted surface in the transistor channel. As the channel goes into accumulation (Vgb< 0V), the inner sidewall of source and drain junction comes into existence and the measured capacitance increases due to reduction of the depletion width of the

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sidewall junction with increasing degree of accumulation.

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 multi-ring body contact structures (2-Rings, 4-Rings, and 8-Rings). It’s due to the more body contact we split, the more source side transmission line distance that may impact the total capacitance of source side capacitances as shown in Fig. 5.22.

These are mainly inter connect coupling capacitances introduced by both metal-to-metal and metal-to-contact interconnect.

The body resistance shows weak bias dependence, but strongly dependence on device geometry such as number of fingers and length of body contacts. In these case, 1/ Rbb scales with body contact length which is due to the length of resistive path.

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Table. 5.7 Body resistance and deep-N-well capacitance with different body shapes Body layout Rbb ( Ohm) Cdwn (fF)

Parallel 1415.48 105.6

L shape 691.86 132.8

U shape 600.97 140.9

Perpendicular 409.15 151.8 standard 384.21 155.4

2-Rings 310.25 166.6

4-Rings 212.87 187.7

8Rings 181.27 231.2

The extracted body resistance and capacitance values from Fig. can be viewed in Table.

The body resistance and capacitance values have been obtained after applying a slight optimization so that the best match for the simulated and measured Y-parameters can be achieved. The body resistance and capacitance values have been obtained after applying a slight optimization so that the best match for the simulated and measured Y-parameters can be achieved.

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Chapter 6 Conclusions

6.1 Summary

The potential impact from layout dependent STI stress on LFN and high frequency performance has been investigated on multi-finger MOSFETs with various layouts, such as narrow-OD and multi-OD. The monotonic decrease of Gm with finger width (WF) scaling in narrow-OD NMOS proves eff degradation from the compressive STI stress along transverse direction (). However, the multi-OD NMOS reveal an abnormal Gm increase for extremely narrow OD width to WOD=0.125m. The observed results suggest that STI stress is not the only mechanism governing the electrical property in miniaturized devices. STI TCR induced

W is identified as another key factor, which may overcome STI stress effect in determining channel current and Gm. Semi-empirical formulas have been derived to successfully predict WOD scaling effect on eff and Gm. Taking this method, W can be precisely extracted based on a simultaneous best fitting to eff and Gm and the resulted increase of effective width (Weff) is dramatically large to around 34% for OD16 with WOD=0.125m. The larger Weff becomes the major contributor to reducing LFN and overcome Nit effect in narrow-OD and multi-OD devices with sufficiently small WOD. The reduction of LFN with OD width scaling is the other evidence reflecting STI TCR induced W effect.

W is identified as another key factor, which may overcome STI stress effect in determining channel current and Gm. Semi-empirical formulas have been derived to successfully predict WOD scaling effect on eff and Gm. Taking this method, W can be precisely extracted based on a simultaneous best fitting to eff and Gm and the resulted increase of effective width (Weff) is dramatically large to around 34% for OD16 with WOD=0.125m. The larger Weff becomes the major contributor to reducing LFN and overcome Nit effect in narrow-OD and multi-OD devices with sufficiently small WOD. The reduction of LFN with OD width scaling is the other evidence reflecting STI TCR induced W effect.

在文檔中 射頻金氧半場效電晶體元件佈局對高頻特性與低頻雜訊之影響以應用於射頻與類比電路 (頁 98-0)