Chapter 2 Noise Theory and Noise Measurement Technique
3.2 Lossy Substrate Model Development For Various Pad Structures
Before we study lossy substrate effect on high frequency noise and the excess noises, which were introduced through pad and TML, the open pad equivalent circuit model should be developed first. Fig. 3.2. depicts the equivalent circuit schematics of the enhanced lossy substrate model to incorporate various pad structures. This new RLC network was created to accurately capture the frequency response with varying pad structures associated with the lossy substrate. The primary enhancement to the original model is a modification on the substrate RLC network in conjunction with TML by adopting a Cox representing the TML to substrate coupling capacitance. The resulted enhanced model is composed of two substrate RLC networks in series with Cpad and Cox to simulate substrate loss through the pads and TML from silicon substrate, respectively. These capacitances are mainly governed by the signal pad or TML area and metal stack underneath. In this work, these two capacitances are physical parameters calculated based on layout and BEOL process parameters (metal thickness, IMD thickness and dielectric constants) rather than from extraction. Csi and Lsi in series with Rsi
make this RLC network different from the conventional substrate network by a simple shunt RC. Capacitances Cp and Csi account for the capacitive coupling while substrate resistance Rsi
and inductance Lsi were proposed to model the semi-conducting nature of silicon substrate under high frequency operation. Coupling capacitance Cc connecting the two-ports is required to model S12 and S21 of the open pads and it should be removed from the pad model when a device is attached through the two-ports to simulate S-parameters and noise parameters of a full structure before de-embedding. Regarding the resistance (Rtml) and inductance (Ltml) associated with transmission line, they can be extracted from Z-parameters of a short pad after modified open de-embedding. A complete extraction flow assisted by equivalent circuit analysis can be referred to our original work [4-5]. Fig. 3.3. illustrates the schematic block diagram derived by circuit analysis theory to extract the circuit elements (Rsi, Csi, Lsi, Cp,
values for further optimization. Parameters optimization was done by Agilent IC-CAP and Agilent Advance Design System (ADS) to get the best fit to S- and Y-parameters. The table 3.1 lists full set of model parameters through optimization for lossy, normal, and small pads respectively. We could observed something interesting from the parameters of lossy substrate model for various pad structures. The category of lossy pad reveals apparently larger capacitances for all three elements(Cpad, Cp1, Csi1) and lower resistance (Rsi1) and inductance (Lsi1) in the first RLC network under pad and larger Csi2 and lower Rsi2, Lsi2 under the second RLC network under TML. As shown in Fig. 3.4. The large capacitances indicated the much coupled effect from the lossy substrate, and the lower resistances and inductances implied that the low resistivity Si substrate effect. Note that Cox is kept at similar value for all three kinds of pad due to the same metal layout and topology for TML from the pads to intrinsic device.
On the other hand, Cpad presents significant difference among the three pad structures in which the scaling factors of around 3.9~4 for lossy versus normal and 0.82~0.85 for small versus normal just approach the theoretical values of 4.04 and 0.75 calculated by layout and process parameters. The accuracy of optimized lossy substrate model was verified and justified by good match with measured S11 and S22 (mag. and phase ) for lossy, normal, and small pads together in Fig. 3.5. Good prediction was achieved for Y-parameters simultaneously (real and imagine part of Y11 and Y22 ) as shown in Fig. 3.6. We could observed something interesting that the lossy pad reveals remarkably smaller magnitudes and more negative phase for both S11 and S22,extraordinary shift in magnitude and phase away from 1.0 and 0° under increasing frequency. We have been known that the purely capacitive plot on Smith chart was trended to along the side of smith chart and kept the constant R circle (kept the same magnitudes), which started form the point of Γ=1 on smith chart. The lossy pad revealed remarkably smaller magnitudes indicated there were not only capacitances but also some parasitic components like resistances and inductances in lossy substrate model to characterize this lossy effect, and the more negative phase indicated the larger capacitances. We could observed these effects
obviously from Y-parameters which larger Im(Y11) indicated larger capacitances in the lossy pad. The difference between normal and small pads is much smaller. As a result, the enhanced lossy substrate model can accurately simulate the pad structure effects in terms of layout and metal topologies with predictable scaling factors.
M8 M8
M1
M7~M2 M7~M2
M8
G S G
Rtml, Ltml
Cpad
DUT
Cox
Substrate
r
Rsi Csi Lsi Cp
(a)
M8 M8
M1
M7~M2 M7~M2
M8
G S G
DUT
Rtml, Ltml
Cpad
Substrate
Cox M2 M7~M3
r
Rsi Csi Lsi Cp
(b)
Fig .3.1. 3D schematics of GSG pads (a) lossy pad scheme : S-pads with stacked metals from M2 to M8 (b) normal pad:S pads with top metal (M8) only
Gate Cc
r
r
r
L
tmlR
tmlRsi1 Csi1 Csi2
Lsi1 Cp1
Cpad
Rsi2
Lsi2 Cp2
Cox
Cp2
Drain
Csi1
r r
r
L
tmlR
tmlRsi1 Csi2
Lsi1 Cox Cpad
Cp1 Rsi2
Lsi2
Fig. 3.2. The equivalent circuit schematics of enhanced lossy substrate open pad model
Gate
r r
Rsi,2 Csi,2 Lsi,2 Rsi,1
Csi,1
Lsi,1 Cp,1
Cpad Rtml
Cp,2
Drain
r r
r
Ltml Rtml
Cpad
Port 1
RQ2 CQ2
RQ1 CQ1
Port 2
Yc Yb
Ya
Port 1 Port 2
Cox Cox
r
Ltml
Rsi,1 Csi,1
Lsi,1 Cp,1
Rsi,2 Csi,2 Lsi,2 Cp,2
Cc
Cc
Open pad
Fig. 3.3 (a) Equivalent circuit model derivation by circuit analysis
High frequency to extract CP, Rsi, Lsi Use Ya to extract Cc
Pad model extraction flow
a 21 12
Fig. 3.3 (b) Pad model parameter extraction flow
Table 3.1
Pad model parameters for various pad structures
Gate Pad RLC model parameters
Pad layout Cpad (fF) Cp1 (fF) CSi1 (fF) LSi1 (pH) RSi1 (Ω) Ltml (pH) Rtml (Ω)
Lossy 77.87 74.97 200 170.7 159.9
Normal 20 28.55 32.68 425.3 511.7 50 0.2
Small 13.89 24.43 33.4 425.3 511.7
Pad layout Cox (fF) Cp2 (fF) CSi2 (fF) LSi2 (pH) RSi2 (Ω) Cc (fF)
Lossy 10.78 1.629 45.98 515.4 328.8
Normal 9.932 2.553 9.316 874.3 638.3 1.103
Small 9.913 2.635 8.741 874.3 638.3
Drain Pad RLC model parameters
Pad layout Cpad (fF) Cp1 (fF) CSi1 (fF) LSi1 (pH) RSi1 (Ω) Ltml (pH) Rtml (Ω)
Lossy 80.99 62 200 83.72 164.3
Normal 20.17 24.05 30 671.3 511.7 50 0.2
Small 12.84 19.72 30 671.3 511.7
Pad layout Cox (fF) Cp2 (fF) CSi2 (fF) LSi2 (pH) RSi2 (Ω)
Lossy 11.07 2 54.15 590.6 270.9
Normal 10.21 2.887 11.73 1059 540.3
Small 9.932 2.635 10.29 1059 540.3
0
Lossy Normal Small Lossy Normal Small 0
200
Fig. 3.4. Pad model parameters scalability for various pad structure
0 10 20 30 40
Fig. 3.5. Comparison of open pad S-parameters between measurement and lossy substrate model for three pad schemes, lossy normal, and small (a) mag(S11) (b) phase(S11) (c) mag(S22)
0 10 20 30 40 0.000
0.001 0.002 0.003 0.004
lossy pad normal pad small Line : model Re(Y11)
lossy pad normal pad small Line : model lossy pad
normal pad small Line : model
0 10 20 30 40
0.000 0.005 0.010 0.015
Im(Y 11)
(c) (d)
(a) (b)
0 10 20 30 40
0.000 0.001 0.002 0.003 0.004
Re(Y22)
Freq (GHz)
0 10 20 30 40
0.000 0.005 0.010 0.015
Im(Y22)
Freq (GHz) lossy pad
normal pad small Line : model
Fig. 3.6. Comparison of open pad Y-parameters for three pad structures (a) re(Y11) (b) imag(Y11) (c) re(Y22) (d) imag(Y22)
Chapter 4
RF MOSFET Intrinsic I-V and C-V Model Calibration
4.1 I-V and C-V Modeling Theory Valid for Sub-100nm MOSFETs
It is very important and required pre-works to create an accurate current-voltage (I-V) and capacitance-voltage (C-V) model for RF MOSFET model development. A complete model of I-V characteristic over a wide bias range is important for nowadays circuit design, especially for analog and RF circuit design, where a variety of bias conditions will be used.
Also with the rapidly increases demand for ultra-low power circuit design in recent year, an accurate model near subthreshold region is also necessary. An accurate capacitance model is also required to predict the devices or circuit speed and AC performance. In conclusion, correct I-V and C-V models are essentials to provide us trustworthy DC and AC characteristics for further study of high frequency performance.
In our research, Bsim3v3 model [13] is used which releases by foundry, TSMC for 0.13um MS/RF CMOS general purpose 1P8M 1.2V technology. In this thesis, there are three dimension of devices which keep width with 4um and length with 0.13um by various finger numbers of NF=18, 36, 72, were adopted for I-V , C-V and S-parameters model calibration and extended to high frequency noise model development. Multi-finger structure was employed to reduced gate resistance and the induced excess noise, and then further to investigate the impact on high frequency and noise performance as well as model scalability to fit various device geometries. The model calibration work was started by modifying the model parameters in Bsim3v3 model. Before this work, DC I-V and two port S-parameters were measured by Agilent vector network analyzer up to 40GHz. Y- and H- parameters can be derived from S-parameters for extraction of gate capacitances (Cgg, Cgs, Cgd) and current gain
cut-off frequency fT. The ultimate goal is to build a accurate model by Bsim3v3 model calibration which can be correspond to the measured results on I-V, C-V, S-parameters, and noise performance. Before starting the model parameters calibration and optimization, we must be known some process related model parameters are specified and fixed at their known values, such as some important geometry or process parameters, Lint (channel length offset), Wint (channel width offset), Tox (oxide thickness), Nch (channel doping concentration), Xj
(junction depth) and so forth. For sub-100nm MOSFET, the following important mechanisms are considered in Bsim3v3 model (1) short channel and narrow width effects on threshold voltage, (2) mobility reduction due to vertical field, (3) velocity saturation, (4) drain-induced barrier lowering (DIBL), and (5) Substrate current induced body effect (SCBE). It is assumed that most of the I-V and C-V parameters were fairly modeled in the original model and only minor modification is needed to improve the model accuracy.
4.2 DC I-V Model Development
For RF MOSFET, 3–terminal test structure is usually implemented with common source configuration in which source and body terminals are tied together and grounded. To measure its high frequency characteristic (both S parameter and NFmin), two sets of probing pad with G-S-G structures are implemented and connected to the gate and drain terminals. The parasitic resistances associated with MOSFET’s terminals such as Rg_ext, Rd_ext, Rs_ext, and Rb_ext contributed from the interconnection lines and probing pads will affect I-V characteristic of DUT. In I-V model development, these parasitic resistances can not be moved out. Extraction of these parasitic resistances should be done and added to the original intrinsic MOSFET model (BSIM3). These parasitic resistances such as Rd_ext and Rs_ext will cause the measured drain current degradation. Rd_ext at drain terminal will affect the rising slope between linear and saturation region, and Rs_ext at source terminal will affect the drain current at saturation region and also cause the transconductance (gm) degradation. Rg_ext at
gate terminal is minor affect on drain current because the current at gate terminal is assumed to very small, and without voltage dropped across the Rg_ext at gate terminal. Therefore, modeling these parasitic resistances accurately is very important. The mentioned parasitic resistances can be extracted from the dummy short pads which is designed to de-embed the resistive and inductive parasitics of the interconnect lines and probe pads, etc. In this study, simulation was done by using Agilent IC-CAP for model verification and calibration. Based on the original model card, default simulation results of Id-Vg and Id-Vd curves were obtained.
Through comparison between simulation and measurement in terms of Id-Vg and gm-Vg curves in both linear and saturation regions, significant deviation was identified for the threshold voltage (Vth), drain current (Id), gate subthreshold swing (S), etc. As for comparison of Id-Vd
curves, channel length modulation (CLM) and drain induced barrier lowering (DIBL) effects were revealed. In BSIM3v3 model, there are many parameters associated with the threshold voltage model. Since source and body of the DUT are tied together and connected to ground, body bias effect on threshold voltage is not available. Narrow width effect on Vth was neglected for sufficient large width of 4μm. Short channel effect related parameters such as Dvt0 and Dvt1 were included to account for charge sharing induced threshold voltage lowering. Mobility model parameter U0 is the zero-filed mobility for Id-Vg simulation in linear region under small drain bias (Vd = 0.1 or 0.05V). Ua, Ub and Uc are fitting parameters used to model the mobility degradation subject to normal field under gate bias. Saturation velocity Vsat determines the saturation current level. Eta0 and Dsub control the amount of threshold voltage variation caused by DIBL and Id-Vg under Vd= Vdd is the fitting target.
Parameters A1 and A2 stands for first and secondary non-saturation effect which occurs in the expression of Vdsat also help to improve Id-Vg and gm-Vg modeling. Subthreshold current fitting can be improved by Voff and Nfactor after the previous terms are well modeled. As for Id-Vd modeling, Pclm, Pdiblc1, Pdiblc2 can be used to properly modify the linear and
first order derivative and even second order derivative also deserve the effort to be well modeled since gm or gds at a certain given bias (application bias point) may affect the device performance such as fT, fmax as well as circuit simulation result.
Fig. 4.1 ~ Fig. 4.4 present the DC I-V modeling results. Good agreement between measured and simulated results under varying biases and various NF shows the integrity of the intrinsic BSIM model. Due to the same metal routing of the interconnect lines for various pad structures (same parasitic resistances and inductances ), and the DC I-V characteristic have no concern with the pad capacitances. So the DC I-V measured results for various pad structures were almost identical when used the same device geometries. Therefore, the DC I-V modeling results which present in Fig. 4.1~4.4 are without the pad definition. Actually, the DC I-V modeling results were not exactly fitting the measured one, because it is difficult to exactly modeling I-V and S-parameters simultaneously especially on S22. So we met a trade off between the exactly fitting on I-V model but poorly accurate on intrinsic S-parameters and doesn’t purely exact fitting but looks ok on I-V model and almost exactly fitting on intrinsic S-parameters, and we have chose the latter one.
4.3 Intrinsic C-V Model Development
In this section, intrinsic gate capacitance model of multi-finger RF MOSFET is presented.
For submicron MOSFET, the thinner oxide thickness is necessary which can reduce SCE (short channel effect), gate swing, but suffer the penalty of gate leakage and gate capacitances.
Since the details are not our focus. The physical oxide thickness of RF013G NMOS technology is 2.8nm. For this thin oxide thickness, the BSIM3 capacitance model flag capMod=3 was set as default model to consider the finite charge thickness determined by quantum effect, which becomes more important for thinner Tox CMOS technologies.
Capacitances in MOSFET is generally divided into three parts, intrinsic, extrinsic, and extrinsic parasitic. In Bsim3v3 model, intrinsic and extrinsic capacitances model were been
included, but extrinsic parasitic capacitance neither. We will explain this later. The intrinsic is associated with the region between the metallurgical source and drain junction. The extrinsic capacitances model considered in BSIM3 are fringing capacitance and overlap capacitance, both consist of bias dependent and bias independent part. In this thesis, only the bias independent outer fringing capacitances are added between the gate and source as well as the gate and drain (parameter CF). The overlap capacitances are composed of two parts: (1) bias independent component which models the overlap capacitances between the gate and the heavily doped (non-LDD) source/drain (parameter Cgso, Cgdo); (2) bias dependent between gate and the gate and the lightly doped (LDD) source/drain (parameter Cgsl, Cgdl). Finally, the extrinsic parasitic capacitances are due to the metal routing (M1~M3) parasitic capacitances which can not be de-embedding. Because the open dummy pad we used in this thesis was deembedding to M3, and couldn’t clearly de-embedding the metal routing capacitances below M3. So these parasitic capacitances (Cgs_ext, Cgd_ext, Cds_ext) should be added to the original intrinsic MOSFET model. Fig. 4.5. demonstrates a detailed classification of capacitances in MOSFETs.
Capacitances of RF MOSFET with GSG probing structure are conventionally extracted from the intrinsic Y parameter (Yint) at low frequency. Before the extracting process, parasitic capacitances due to probing pad and interconnection metal should be de-embedded from the measured data. Traditionally, the removal of these parasitics is done through open de-embedding mentioned early. In fact, short de-embedding should also be carried out to get rid of the series impedances. This is essential for accurate capacitance extraction. A broadly accepted de-embedding technique is open/short two step de-embedding for two-port three terminal device (source/bulk tied together) [22]. Due to the fact, a conventional open pad leaving only the GSG pad can not de-embedding all the coupling capacitances. Thus remand the metal connecting between DUT and GSG pad. However, the coupling capacitances
between two port is mainly dominated not only GSG pad but also the interconnection line which may influences the accuracy of capacitances extraction on real device. Therefore, a modified open/short de-embedding approach was used to improve these influence. A modified structure is to remove the DUT cell simply, thus leave the connecting metal between DUT cell and signal metal pad. This modification enables us to extract the capacitances of the DUT cell that is sometimes what a circuit designer need in some cases. Appendix B presents this modified de-embedding. The new de-embedding method is especially efficient when an open pad is designed with all the interconnection metal left.
After the open/short de-embedding, intrinsic gate capacitances can be extracted from the formulas given by [23]:
gg int,11
C = Im(Y )/ω (4-1)
gd int,12
C = - Im(Y )/ω (4-2)
gs int,11 int,12
C = Im(Y +Y )/ω (4-3)
ds int,22 int,12
C =Im(Y +Y )/ω (4-4)
Intrinsic gate-to-back capacitance Cgb is negligible due to its small value in triode and saturation regions. This is because the inversion layer in the channel shields between gate and bulk. In the modeling process, extrinsic components Cgs_ext and Cgd_ext were used to model the remanded parasitic capacitance (M1~M3) and model parameters, Cgso, Cgdo, Cgsl, Cgdl, Voffcv were used to complete the result. With little modification on these model parameters, C-V characteristics ca be modeled well. First, adjust Cgso and Cgdo to a value so that simulation result is close to the measured one. Then, use Voffcv to better fit measured near subthreshold region. Cgsl and Cgdl are employed to modulate the gate bias trend of Cgs and Cgd individually.
Finalized model parameters are shown in Table 4.1. Fig. 4.6. present the modeling result of gate capacitances for multi finger (NF=18, 36, 72) NMOS devices.
Table 4.1
Model parameters for gate capacitances modeling
T13RF-95A
WF=4um NF Cgs_ext(fF) Cgd_ext(fF) Cgs0(F/m) Cgd0(F/m) Cgsl(F/m)Cgdl(F/m) CF(F/m) Voffcv
18 5.37 1.99 360p 386p 70p 70p 0 -0.053
36 9.27 3.69 360p 386p 70p 70p 0 -0.053
72 17.07 7.10 360p 386p 70p 70p 0 -0.053
Modified values
0.0 0.2 0.4 0.6 0.8 1.0 1.
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Fig. 4.5.Category diagram of gate capacitances in MOSFETs
0.4 0.6 0.8 1.0 1.2
Chapter 5
Lossy Substrate Model to Predict Pad Structure Effect on RF Noise-Broadband Accuracy & Scalability
In this chapter, the enhanced lossy substrate model was further verified by integrating with the intrinsic devices for full circuit (pad+intrinsic) simulation to identify the impact on high frequency and noise characteristics. The particularly interesting and useful application is an accurate and simple noise extraction method to ensure noise simulation accuracy for nanoscale devices. Before starting the full circuit model calibration. The lossy substrate model must be developed firstly by open pad measurement (chapter 3). Then the model calibration was done on the intrinsic device’s I-V and C-V models(chapter 4). Afterward, 4 terminal parasitic R and L (Rg, Rs, Rd, Rbulk, Lg, Ld, Ls) were correctly extracted and deployed in intrinsic MOSFET. Consequently, good match in terms of gm, Cgg, Cgd, Cgs (Y-parameters), and fT (H-parameters) over wide range of biases or currents was realized for 100nm NMOS of various finger numbers (NF=18, 36, 72). The full circuit model accuracy can be verified in terms S-parameters up to 40GHz and noise parameters up to 18GHz.
5.1 Equivalent Circuit Model Verification
Fig. 5.1. illustrates the device characterization and modeling flow. An equivalent full circuit include the pad model and intrinsic MOSFET model were shown in Fig. 5.2. The RLC networks represents the lossy pad, lossy substrate ,and transmission line are linked with the intrinsic MOSFET. The dash block in the full circuit schematic was the equivalent circuit of intrinsic MOSFET which given by foundry. A core BSIM3 MOSFET model was calibrated in terms of I-V and C-V characteristics. Due to that BSIM3 MOSFET model didn’t include the high frequency characteristic components like gate resistances and substrate network.
Therefore, in order to modeling the intrinsic MOSFET accurately up to 40GHz, some
parasitic components must be added to core BSIM3 model. The parasitic components such as gate resistance, substrate network, Cds ,and Rds were the important and necessary elements for high frequency characterization (S-,Y-parameters). In the intrinsic MOSFET model, two junction diodes were implemented to represent the drain-to-body and source-to-body p-n junctions. Cds and Rds were adopted to model the source to drain proximity capacitance and the associate resistance apparent at high frequency, they play an important role in accurate
parasitic components must be added to core BSIM3 model. The parasitic components such as gate resistance, substrate network, Cds ,and Rds were the important and necessary elements for high frequency characterization (S-,Y-parameters). In the intrinsic MOSFET model, two junction diodes were implemented to represent the drain-to-body and source-to-body p-n junctions. Cds and Rds were adopted to model the source to drain proximity capacitance and the associate resistance apparent at high frequency, they play an important role in accurate