Chapter 6 Conclusion
6.2 Future Work
6.2.1 Low Noise Measurement and Modeling
The established lossy substrate model and lossy substrate de-embedding method have been extensively verified and justified by nanoscale devices adopting various pad structures.
Further research works to be done will cover two major subjects : one is on-chip noise shielding methods to measure truly intrinsic device noise without resort to de-embedding and another one is a broadband and fully scalable lossy substrate model for nanoscale RF MOSFET noise extraction and simulation with broad freedom in pad and interconnect layouts.
We will also extend our effort to several interesting and challenging topics like short channel effect on channel noise, substrate network effect, noise model valid in subthreshold region, and dynamic body biasing effect for low noise, low power and high speed design through 4T and 4-port device implementation. The ultimate goal for us to realize through future project supported by 90nm low power CMOS process is to assure on-Si-chip noise simulation accuracy and to facilitate low noise, low power and broadband RF circuit design.
6.2.2 Ultra-low power RF CMOS design
The advancement of CMOS technology to nanoscale era can offer miniaturized devices of higher speed at even lower voltage. It is really a very attractive solution for low power and low cost RF integrated circuit (IC) development. However, the tradeoff among various RF performance parameters such as bandwidth, linearity, gain, power, and noise becomes an important reality to be considered. For cable-free body monitoring with μW biomedical acquisition devices, a sub-mW wireless transceiver is required for long-term observation.
However the power consumption is a critical issue, and how to reduce the active and standby leakage power in the circuit is a big challenge. Therefore, the demand for ultra-low power circuit design increases rapidly.
To meet the stringent requirements for ultra-low power design, new device and/or circuit techniques become increasingly important to corporate with technology scaling to realize leakage reduction and maintain performance simultaneously. A future work with interest in new device configuration with new bias schemes for ultra-low power design will be one of research topics worthy of continuous effort.
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Appendix A
[24]The Y-Factor Method and Noise Figure Correction
In noise figure measurement, total output noise power measured is
o a i a
N = N + GN = N +kTBG (A-1) where No and Ni represent the noise levels available at the output and input respectively, G is the gain of the DUT, B is the bandwidth, k is Boltzmann’s constant, and T is the absolute temperature.
To determine Na, output noise power corresponding to two source temperatures are needed. Two output noise power and two source temperatures determine the slope kBG and intercept Na. A diode based noise source in the on-state (hot) generates noise when it is reverse biased into avalanche breakdown. Thus the equivalent noise temperature will be higher than its “off-state” (cold). Temperature difference is expressed by excess noise ratio (ENR)
ENRdB
h c 10
dB
0
ENR = 10 log(T -T ) , ENR = 10
T (A-2)
Y-factor is defined as the output noise ratio
1 2
Y=N
N (A-3) Derivation is shown as follows:
dB
1 a c 2 a h
ENR
h c
10
0
a h
2
1 a c
N =N +kT BG , N =N +kT BG ENR = 10 =T -T
T N +kT BG Y=N =
N N +kT BG
(A-4)
In practice, Tc is assumed to be 290K when it is calibrated. This leads to
a h 0
0 0
0
a 0
(Y-1)N = kBG(T -YT )
= kBG(T ENR+T -Y T ) = kT BG(ENR+1-Y) N = kT BG(ENR-1)
Y-1
⋅ ⋅ 0
⇒
(A-5)
From the derived Na, the total noise factor measured can be calculated.
0 0
a i
tot
i 0
kT BG(ENR-1)+GkT B
N +GN Y-1 ENR
F ≡ GN = GkT B = Y-1 (A-6) Because only the noise factor of the DUT is interested, removal of the noise contributed from the second stage is essential. Based on the noise factor analysis of multi-stage system, total noise factor of a two-stage system is
2
tot 1
1
F = F +F -1
G (A-7) where F1, F2 and G1 are noise factor of 1st stage, 2nd stage and gain of 1st stage respectively.
Noise factor of the instrument (F2) can be characterized while doing system calibration and gain of the DUT (G) will be obtained while measuring S-parameters before noise measurement. Therefore corrected noise factor is obtained
2
1 tot
1
F = F F -1
− G (A-8) then is used to construct the noise equation.
Appendix B
Modified Open-Short De-embedding
Open and short pads were conventionally used to de-embed parallel parasitic admittance and series parasitic impedance respectively. The de-embedding procedure is shown as follows:
m_de_o m o
Y = Y -Y
Y
1
(B-1)
s_de_o s o
Y = Y - (B-2)
1 1 1
int m_de_o s_de_o m o s o
Z = (Y )− −(Y )− =(Y -Y )− −(Y -Y )− (B-3)
1
int int
Y = (Z )− (B-4)
where
Y = measured Y parameter of DUT m
Y = measured Y parameter of open pad o
Y = measured Y parameter of short pad s
Y = intrinsic Y parameter after open/short de-embedding int
Equivalent circuits of test structure with DUT, open pad and short pad are given in Fig.
B.1~Fig. B.3. According to these equivalent circuits, following expression holds
p1 p3 p3
o
p3 p2 p
Y +Y -Y
Y = -Y Y +Y
⎛ ⎞
⎜⎝ 3⎠⎟ (B-5)
s1 s3 s3 -1
s_de_o s_de_o s o
s3 s2 s3
Z +Z Z
Z = (Y ) = Y -Y =
Z Z +Z
⎛⎜
⎝ ⎠
⎞⎟
⎞⎟
(B-6)
In this de-embedding process, based on Fig. B.3, short pad does not see a parasitic admittance Yp3 because all the interconnection metals are shorted at the same potential.
De-embedding procedure (B-2) may introduce an over-de-embedding error because Yp3 was deducted from Ys in which Yp3 does not exist. Therefore step (B-2) was modified as given below and keeps the rest of the steps the same.
11 12
s_de_o s
22 21
Y +Y 0
Y Y
-0 Y +Y
= ⎛⎜
⎝ ⎠ (B-7)
Y
p3DUT
Y
p1Z
s1Y
p2Z
s2Port 1 Port 2
Z
s3Fig. B.1 Equivalent circuit of test structure with DUT
Y
p3Y
p1Z
s1Y
p2Z
s2Port 1 Port 2
Z
s3Fig. B.2 Equivalent circuit of open pad
Y
p1Z
s1Y
p2Z
s2Port 1 Port 2
Z
s3Fig. B.3 Equivalent circuit of short pad
Vita
蔡依修 Yi-Hsiu Tsai
Birthday： 1982/10/18
Birthplace：Tainan County, Taiwan Education：
2001/09 ~ 2005/06 B.S. Degree in Department of Communucations Engineering, Yuan Ze University
2005/09 ~ 2007/07 M.S. Degree in Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University
Publication：
[1] Guo, J.C.; Tsai, Y.H., "A Scable Lossy Substrate Model for Nanoscale RF MOSFET Noise Extraction and Simulation Adapted to Various Pad Structures," Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE , vol., no.pp. 299- 302, JUNE 3-5 2007