Output Stages

The output stage is consist of four power transistor switches controlled by four control signals CT1, CT2, CT3 and CT4 as shown in Fig. 26. The control signal CT1 controls the control circuit 1 and the output stage of the negative voltage –VDD. The control signals CT2, CT3 and CT4 control the control circuit 2, 3 and 4 and the output stages of the positive voltage 10V, 20V and the ground 0V respectively. The output stages of each output voltages are different because of the difference of the voltages between the output node and the

generated voltages. The output stages are going to be unfolded later in this chapter.

Fig. 40 Output stage of the negative charge pump

Fig. 40 is the circuit schematic of the output stage which outputs the negative voltage from the negative cross-coupled charge pump to the output terminal. CT1 is the control signal as a square wave swings between input voltage V_DD and the ground. It transforms to a square wave swings between the ground the negative voltage –VDD by the level shifter circuit in the output stage to control the output power transistor. We name the output stage which is shown in Fig. 40 as output stage 1. The simulation result of the output stage 1 is shown in Fig. 41.

The input is control signal CT1 and the output is the delivered output VOUT.

Fig. 41 Simulation of the output stage 1

As shown in Fig. 41, the input control signal CT1 controls the delivering of the negative voltage –V_DD to the output node. When CT1 is high, the voltage at node V3 will be pulled high from the negative voltage –VDD to the ground, it will turn on the power transistor MO1

and pull the output voltage to the negative voltage –V_DD as shown in the figure.

2V^DD

CT2

2V^DD

VDD

V^DD V^OUT

M^O2

V¹ V²

Fig. 42 Output stage of the input voltage VDD

Fig. 42 is the output stage for the input voltage VDD transferring. The control signal CT2 is a square wave swings between the input voltage V_DD and the ground. It passes a level shifter and transform to a square wave at node V2 swings between the highest voltage 2VDD

and the ground. By doing so, the power transistor M_O2 can be turned off correctly when the output node is at the highest voltage 2VDD. A pair of PMOS transistor is connected to the bulk of the power transistor M_O2 to bias the bulk to the highest voltage of the transistor. Fig. 43 shows the simulation results of the above output stage. The output voltage can be pulled from both high to low and low to high as shown in the figure.

Fig. 43 Simulation of the output stage 2

Fig. 44 is the output stage which delivers the highest voltage 2V_DD to the output terminal.

The structure is much similar as the output stage shown in Fig. 42.

2V^DD

CT3

2V^DD

V^DD

2V^DD V^OUT

M^O2

V¹ V²

Fig. 44 Output stage of the positive charge pump

The control signal CT3 is a square wave swings between the input voltage VDD and the ground. It passes a level shifter and transform to a square wave at node V2 swings between the highest voltage 2VDD and the ground. By doing so, the power transistor MO2 can be turned off correctly when the output node is at the highest voltage 2V_DD. The simulation is shown in Fig. 45. The voltage is delivered to the output terminal while CT3 and V2 are low. The output terminal can be pulled to the highest voltage 2V_DD by the output stage no matter the original voltage of the output terminal is a positive or even a negative voltage.

Fig. 45 Simulation of the output stage 3

The last output stage is the output stage which delivers the ground level to the output terminal as shown in Fig. 46. The above-mentioned output stages all need only one power transistor to deliver the voltage. But when it comes to the output stage here, only one power transistor to switch and deliver the ground level to the output terminal will lead to the unwanted leakage current when the transistor supposed to be turned off. Because the original voltage of the output terminal might be higher or lower than the ground level, the output power transistor must be redesign to fit the requirement. If the output power transistor is a PMOS transistor, it can deliver the ground level to the output terminal when it is at negative voltage lower than the ground. And a positive voltage at the output terminal will force the PMOS transistor to leakage a reverse current from output to the ground at the turning off period. Similarly, if the output power transistor is a NMOS transistor, a negative at the output

terminal will force the NMOS transistor to leakage a reverse current from the ground to the output terminal at the turning off period.

V^OUT the other above mentioned output stages. It uses two output power transistors to deliver the output voltage level. A PMOS transistor MO2 delivers the charge while the output terminal is at a negative voltage lower than the ground and a NMOS transistor MO1 delivers the charge while the output terminal is at a positive voltage higher than the ground. Two diode-connected PMOS transistors with bulk biasing circuits MD1 and MD2 are introduced to prevent the corresponding output power transistors from conducted in the turning off period. The control signal CT4 will transform to a square wave at node V1 which swings from the ground to the negative voltage –VDD to correctly control the output power transistor MO2. And another output power transistor M_O1 is controlled by CT4 directly.

The simulation result of the output stage 4 is shown in Fig. 47. CT4 is the input control signal. V2 is the reversion of the control signal CT4. V1 is the signal generated by level shifting the control signal C4. As we can see, the output voltage can be pulled to the ground level no matter the original output voltage is higher or lower than the ground. And the output can remain its original voltage when the output stage is turned off without leakage current.

Fig. 47 Simulation of the output stage 4