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Post-Simulation results of multiband frequency synthesizer

Chapter 3 A 3-to-10-GHz Direct Frequency Synthesizer with 12 selective

3.6 Post-Simulation results of multiband frequency synthesizer

The synthesizer is fabricated in the 0.18μm CMOS process, and the chip consumes an area of 0.9 × 1.1mm, as shown in Fig. 3.6.1. The post-simulated core circuit consumes 60.76mW and the buffer consumes 52.93mW from a 1.8-V supply. Fig. 3.6.2 shows the simulated tuning characteristics of the QVCO, and the tuning ranges are 2515MHz by turning on/off the switch Vbank at TT corner, 2248 MHz at FF corner, and 2393 MHz at SS corner.

The simulated phase noises of QVCO at TT, FF, and SS corner are less than -92.5dBc/Hz at

300-KHz offset and -107.5dBc/Hz at 1-MHz offset, when Vbank is turned on or off, as shown in Fig. 3.6.3.

Fig. 3.6.1 The layout of the multiband frequency synthesizer

Fig. 3.6.2 Tuning ranges of the QVCO (TT, FF, and SS corner)

(a) (b)

(c)

Fig. 3.6.3 Simulated phase noise at Vbank on/off (a) TT (b) FF (c) SS corner

Fig. 3.6.4 shows the simulated output spectrums of twelve LO bands in the frequency synthesizer after Fast Fourier Transformation (FFT) of the output transient. The worst case of spurs is at 6072 MHz (Band 6), and the distance from main tone to spurs is about 2 GHz. The difference to main tone is about 35dBc. Fig. 3.6.5 shows signal transient analysis of 9240 MHz (Band 12), 6600 MHz (Band 7), and 4488 MHz (Band 3) that are produced by QVCO, 1st divider, and mixer individually.

(a) 3960 MHz (Band 2) (b) 4488 MHz (Band 3)

(c) 5016 MHz (Band 4) (d) 6072 MHz (Band 6)

(e) 6600 MHz (Band 7) (f) 7128 MHz (Band 8)

(g) 7656 MHz (Band 9) (h) 8184 MHz (Band 10)

(i) 8712 MHz (Band 11) (j) 9240 MHz (Band 12)

(k) 9768 MHz (Band 13) (l) 10296 MHz (Band 14) Fig. 3.6.4 The FFT simulation results of twelve bands

(a)

(b)

(c)

Fig. 3.6.5 Signal transient analysis at (a) 9240 MHz (Band 12) (b) 6600 MHz (Band 7) (c) 4488 MHz (Band 3)

Fig. 3.6.6 Simulated output frequency synthesizer in the time domain by controlling the switches

Table 3.6.1 Summary of wide tuning range QVCO TT corner FF corner SS corner

Fig. 3.6.6 shows simulated output frequency synthesizer in the time domain. The simulated LO frequency switches from 1954 to 10296 MHz by controlling S1-S4, Vctrl and Vbank about 1ns, which is well within the 9-ns channel switch time specified in the MB-OFDM

proposal. Table 3.6.1 summarizes the pose-simulation performance of wide tuning range QVCO. Table 3.6.2 shows the output power of twelve bands individually, settling time and total power consumption. Table 3.6.3 shows the comparisons of this work and correlated papers. It can be seen that the multiband synthesizer presented in this chapter achieves more LO bands and less area fabricated in 0.18-μm CMOS process. This circuit provides a solution to generate a full coverage of the fourteen bands with minor modification, holding great promise for future WPAN systems.

Table 3.6.2 selective-band switches in the frequency synthesizer

Band(MHz) Switch Vbank(V) Vctrl(V) Output swing(Vpp) Output power

10296 0 1.8 0.4408 -3.13dBm

Settling time ~1ns

Power (mW) 60.76

Switched Buffer Power(mW) 52.93

Table 3.6.3 The comparisons of this work and the correlated researches This work

(Post-simulation) [22] [23] [34]

Frequency 3.96~10.296GHz 3.432~7.92GHz 3.432~7.92GHz 3.432~4.488GHz

No. of Bands 12 7 7 3

Phase Noise (@1-MHz offset)

-107.5dBc/Hz

(QVCO) -110dBc/Hz -103dBc/Hz -104dBc/Hz

Settling Time 1ns 3ns 1ns 1ns

Power Diss. 113.69mW 46mW 48mW 27mW

Supply Voltage 1.8V 2.7V 2.2V 2.7V

Chip Area 0.9mm x 1.1mm 2.0mm x 2.0mm 1.3mm x 1.1 mm 1.0mm x 1.1mm Technology 0.18-μm CMOS 0.18-μm SiGe 0.18-μm CMOS 0.25-μm SiGe

Chapter 4

Conclusions and future works

4.1 Conclusions

This thesis analyzes the design method of low-voltage, low-power, UWB LNA, and this circuit is demonstrated with wideband performance from 2.5 to 8.5 GHz at only 1V power supply. Besides, a direct frequency synthesizer structure for UWB is designed with low phase noise performance. The circuit consists of a binary 8448MHz voltage controlled oscillator (VCO) and 2-stage frequency dividers, and three LO bands (8448MHz, 4224MHz and 2112MHz) are produced individually. Finally, a fast-hopping frequency synthesizer that generates twelve LO bands from 3 to 10 GHz is designed. The prototype is completed by combining a wideband QVCO, 2-stage dividers, switched buffer and only one quadrature SSB mixer. The three ICs have been fabricated using CMOS 0.18um process. In this thesis we have presented the design concepts, simulation results, experimental results, discussions and comparisons for the correlated researches. All of the circuits were simulated by Eldo-RF and ADS. The inductors and long transmission lines are simulated by Sonnet. The UWB LNA and frequency synthesizer for low phase noise are measured in CIC.

The low-voltage, low-power, UWB LNA topology is studied and analyzed in three respects, including input matching, noise figure, and power gain. These characteristics are analyzed in terms of circuit elements. Some simulations are also demonstrated to prove the analysis equations. It achieves wideband performances. The measured power gain is 10dB from 2.5 to 8.5 GHz. The input return loss is less than -7.07dB from 3.1GHz to 10.6GHz. The minimum noise figure is 3.46dB at 5.46 GHz, and noise figure is less than 5.6dB from 3 to 9 GHz. The measured P1dB are -8.5dBm at 3 GHz, -9.5dBm at 6 GHz, and -8.5dBm at 9 GHz.

The measured results show the LNA achieves wideband performance at 1V supply voltage, and the power consumption is only 7.25mW.

The MB-OFDM UWB has greater flexibility in coexisting with other international wireless systems and future government regulator, and could avoid transmitting in already occupied bands. The receiver of such a system should have high linearity and a wideband local oscillator (LO) capable of frequency hopping in less than 9ns. So, a direct frequency synthesizer structure with quadrature phases for UWB systems is presented. At first, an initial direct frequency synthesizer structure for UWB is designed with low phase noise performance.

The circuit consists of a binary 8448MHz VCO and 2-stage frequency dividers, and three LO bands (8448MHz, 4224MHz and 2112MHz) are produced individually. The switched buffer as multiplexer with symmetrical independent architecture is used to select output frequency and lowers the phase noise. Fabricated in 0.18-μm CMOS technology, in three LO bands, this work achieves the phase noise of less than -121dBc/Hz@1MHz offset and the frequency tuning range of 10% while consuming 52.2mW from a 1.8-V supply.

Furthermore, a fast-hopping frequency synthesizer that generates more LO signals of twelve bands from 3 to 10 GHz is designed. The prototype is completed by combining a wideband QVCO from 7.93 to 10.3 GHz, 2-stage dividers, switched buffer and only one quadrature SSB mixer. Fabricated in 0.18-μm CMOS technology, this work achieves QVCO’s simulated phase noise less than -107dBc/Hz at 1 MHz offset, and the simulated output powers of twelve bands have better than 35 dB sideband rejection while consuming 81.1mW of the core circuit and 32.6mW of the buffer from a 1.8-V supply. The simulated switching time for hopping frequency is about 1ns.

4.2 Future works

4.2.1 UWB receiver

In the design of UWB LNA and multiband frequency synthesizer, there are several directions for future study. First, for higher frequency applications, more accurate RF CMOS component models such as large size MIM capacitors and the inductance spiral inductors with higher Q-value should be built up for exactly matching network design in the future. All parasitic effects including parasitic capacitance, resistance and inductance must be considered more carefully. A more accurate and efficient EDA tool for extracting parasitic effects are quietly important. The UWB LNA may be improved as gain-controllable one for higher dynamic linearity application and lower noise figure to depress the average noise figure of the receiver.

Besides, the multiband frequency synthesizer with 12 selective LO bands is presented. By combining PLL architecture, the frequency synthesizer can offer more stable LO frequency, but the settling time increases because of the PLL structure, as shown in Fig. 4.2.1. For example, the fractional-N divider has fast setting time performance than integer-N divider.

High reference clock speeds up to lock frequency but induces more in-band noise. The more charge current in the charge pump accelerates the variation change of Vctrl signal, but induces more power consumption. Therefore, it must be trade-off to achieve the whole PLL structure for multiband frequency synthesizer.

Fig. 4.2.1 A basic PLL structure

As for the MB-OFDM UWB receiver, it can be achieved by combining the UWB LNA, the multiband synthesizer, and an additional UWB mixer. The fully integrated UWB transceiver, including receiver front-end, power amplifier, up-mixer, quadrature VCO, multi-modulus frequency synthesizer, and IF Gm-C filters may be realized for future system-on-chip (SOC) design.

4.2.2 Cognitive communications

Wideband communication is a trend of the future communication. Based on MB-OFDM UWB technique, Cognitive radio is viewed as a novel approach for improving the utilization of a precious natural resource: the radio electromagnetic spectrum, the use of which by transmitters and receivers is licensed by governments. But, Federal Communications Commission (FCC) has pointed out that, in many bands, spectrum access is a more significant problem than physical scarcity of spectrum, in large part due to legacy command-and-control regulation that limits the ability of potential spectrum users to obtain such access [35]. Less than 20% of the licensed spectrum is in use at any given time.

The cognitive radio, built on a software-defined radio, is defined as an intelligent wireless communication system that is aware of its environment and uses the methodology of understanding-by-building to learn from the environment and adapt to statistical variations in the input stimuli. The underutilization of the electromagnetic spectrum leads us to think in terms of spectrum holes. A spectrum hole is a band of frequencies assigned to a primary user, but, at a particular time and specific geographic location, the band is not being utilized by that user [36]. Spectrum utilization can be improved significantly by making it possible for a secondary user (who is not being serviced) to access a spectrum hole unoccupied by the primary user at the right location and the time in question.

As time evolves and spectrum holes come and go, the bandwidth-carrier frequency

picture in Fig. 4.2.2 for the case of seven carrier frequencies, and the way in which the spectrum manager allocates the requisite channel bandwidths for three instant time, depending on the availability of spectrum holes.

Fig. 4.2.2 Illustrating the notion of dynamic spectrum-sharing for OFDM based on seven channels

The front-end of the transceiver used in the cognitive communication is designed with wideband LNA, wideband mixer, wideband PA, and multiband frequency synthesizer, as shown in Fig 4.2.3. When the spectrum sensor detects an unused spectrum hole, baseband processor offer control signals to adjust multiband frequency synthesizer. Therefore, the carrier frequency can be shifted to the spectrum hole for secondary users. When the spectrum sensor detects that a primary user will use the spectrum covering the spectrum hole. The carrier frequency of the secondary users will be shifted to another spectrum hole or stop transmission. In the cognitive communication, UWB LNA and the frequency synthesizer with wider tuning range are needed. Unlike the MB-OFDM UWB specifications, the number of LO bands produced by frequency synthesizer must be extended to more possible spectrum holes to tens of GHz.

Therefore, it is widely recognized that the use of a MIMO antenna architecture can provide for a spectacular increase in the spectral efficiency of wireless communications [37].With

improved spectrum utilization as one of the primary objectives of cognitive radio, it seems logical to explore building the MIMO antenna architecture into the design of cognitive radio.

The end-result is a cognitive MIMO radio that offers the ultimate in flexibility, which is exemplified by four degrees of freedom: carrier frequency, channel bandwidth, transmits power, and multiplexing gain for future communications.

Fig. 4.2.3 The transceiver architecture of the cognitive communication

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Publication Remarks

International conference papers:

1. Bo-Yang Chang and Christina F. Jou, “Design of a 3.1-10.6GHz Low-Voltage, Low-Power CMOS Low-Noise Amplifier for Ultra-wideband Receivers”, IEEE Asia-Pacific Microwave Conference (APMC 2005), December 4-7, 2005, Suzhou, China.

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