Proposed Energy-Efficient Level Converter with High Thermal

The schematic view of the proposed level converter is shown in Fig. 4.5. It is based on the cross-coupled level converter and adapts two diode-connected PMOS transistors in [4.5]. The multiple-threshold-voltage CMOS design is also employed in the proposed level converter. In addition, a stack leakage reduction technique is used to reduce the power consumption. Reverse short channel effect is also exploited to make the proposed level converter more reliable and robust across all the process corners and temperature variations.

Vin

VDDH

Vout

Vout

Voutb

Voutb

LVT HVT RVT

MP1 MP₂

MP₃ MP4

MN₁ MN2

MN3 MN4

MN₅ I₁ MN6

Figure 4.5. Schematic view of the proposed level converter

4.2.1 Diode-Connected PMOS Transistors

From Fig. 4.1(b), we can find that the conventional level converter has an imbalance driving ability problem when converting a signal from the sub-threshold region to the super-threshold region. For TSMC 65nm CMOS technology, the ratio of pull-down device (NMOS) and pull-up device (PMOS) should be larger than 200X so

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that the conventional level converter can barely be operated at an input supply voltage of 200mV. The resulting width of NMOS causes a huge area overhead. In Fig. 4.5, the proposed level converter utilizes diode-connected PMOS transistors to reduce the pull-up driving ability [4.5], MP3 and MP4 serve as a current limiter. Two PMOS diodes maintain its initial value during the transition. The initial value is equal to a small diode voltage drop and limits the PMOS strength. As a result, the pull-down devices, MN₁ and MN₂, can sink the I₁ current even when the circuit is operated in the sub-threshold region. Comparing the results in Fig. 4.1(b) and Fig. 4.6, the PMOS conduction current is decreased dramatically and closer to the NMOS conduction current. Thus, they have a comparable driving ability. By connecting two PMOS diodes, the modified cross-coupled level converter overcomes the imbalance conduction current problem when operated at low voltage. Thus, the proposed level converter can convert the signal from sub-threshold region to super-threshold region successfully.

1 1.5 2 2.5 3 3.5 4 0

200 400 600 800 1000

T im e s

conduction current (nA)

σ/μ=0.14 σ/μ=0.48 PMOS at super-threshold

NMOS at sub-threshold

Figure 4.6. Monte Carlo simulation of conduction current of two diode-connected PMOS transistors

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4.2.2 Multi-threshold-voltage CMOS (MTCMOS)

The MTCMOS design is usually provided in the modern technology.

Low-threshold voltage (LVT) devices take the advantage of the speed but have a severe leakage current problem. High-threshold voltage (HVT) devices have a less leakage current but sacrifice the speed. There is a trade-off between the propagation delay and the power consumption. Therefore, power-delay-product (PDP) should be used as a figure of merit for level converter analysis. To further weaken the PMOS strength, MP1, MP2, MP3, and MP4, use the HTV devices. To enhance the NMOS strength, MN₁, MN₂, MN₃, and MN₄, are considered using the LTV devices. If all the NMOS transistors are utilized the LTV devices, the power consumption will be increased very much. In the proposed level converter, only MN₃ and MN₄ use the LTV devices. This configuration can make a faster speed when output changes from high to low and improve the total propagation delay time. From Fig. 4.7, we can find that the pull up current is shifted to left and becomes more convergent.

1 1.5 2 2.5 3 3.5 4

0 200 400 600 800 1000

T im e s

conduction current (nA)

σ/μ=0.11 σ/μ=0.48 PMOS at super-threshold

NMOS at sub-threshold

Figure 4.7. Monte Carlo simulation of using HVT devices for pull up PMOS transistors

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4.2.3 Stack Leakage Reduction Technique

The leakage current causes the static power consumption. With the scaling down technology, this problem becomes severely in the LVT logic block. In Fig. 4.8(a), the LVT block is connected by a HVTNMOS transistor [4.11]. When the LVT block is in a sleep mode, the connected HVT transistor is also turned off by a sleep signal to avoid a leakage path to the ground. A sleep mode means the block function is turned off. From the Monte Carlo simulation in Fig. 4.8(b), the leakage current is reduced quietly a lot when using the leakage reduction technique. This technique is adapted in the proposed level converter. MN₃ and MN₄ are the LTV devices, they are connected by the HTV NMOS transistors, MN5 and MN6, as shown in Fig. 4.5. The signal of Vout and Voutb are feedback to control MN₅ and MN₆ adaptively. When the input is

“1”, MN3 is in an active mode and MN4 is in a sleep mode. Vout is charged by MP2

and turns on MN₅, so the left branch works as usual. Voutb is discharged by the MN₁ and turns off MN6. The right branch is in a sleep mode. When the input is “0”, Vout turns off MN₅ and Voutb turns on MN₆. The left branch is in a sleep mode and the right branch works as usual. In both of the situations, there are no leakage path existing.

62 LVT Block

VDD

Sleep

0.01 0.1 1

0 500 1000

times

Leakage current (nA)

σ/μ=0.03 with leakage reduction

without leakage reduction σ/μ=2.71

(a) (b)

Figure 4.8. (a) Leakage reduction technique [4.11]. (b) Monte Carlo simulation of leakage current with/without leakage reduction technique

4.2.4 Reverse Short Channel Effect [4.13]

The minimum channel length is typically selected for the optimal speed and power performance in the super-threshold operation since the short channel effect is a dominant factor. However, there is a different scenario in the sub-threshold region.

Because of the significantly reduced drain-induced-barrier-lowering (DIBL), the reverse short channel effect becomes a major factor in the sub-threshold operation.

Due to the reverse short channel effect, the threshold voltage decreases monotonically and the conducting current increases exponentially when the channel length is longer.

Thus, the best PMOS channel length of the proposed level converter is not the minimum length. From Fig. 4.9(a), the propagation delay increases with an increase of length. Based on the simulation data, the optimal device sizing is 85nm in this work, as Fig. 4.9(b) shown. While the channel length is longer than the optimal length, the reverse short channel effect is weak.

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4.2.5 Sub-threshold device sizing

Except for reducing the pull up driving ability, enhancing the pull down driving current is another way to solve the imbalance current problem. The pull down devices are operated in the sub-threshold region so that the sizing technique has a linear impact on the current. To increase the width of the NMOS transistors makes the pull down driving ability stronger. From Fig. 4.10(a), the propagation delay is reduced by

60 80 100 120 140 160 180 200

Figure 4.9. Short channel effect. (a) Delay and power simulation (b) PDP value simulation

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150 200 250 300 350

Figure 4.10. Sub-threshold device sizing. (a) Delay and power simulation (b) PDP value simulation

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region and causes a propagation delay time. As Fig. 4.5 shown, MN₂ and MN₄ are controlled by the output of the inner inverter. The positive feedback loop has to wait for MN₂ and MN₄ settling down to be triggered. However, the faster speed brings larger power consumption, as Fig 4.11 shown. Therefore, there is a trade-off between delay and power. From Fig. 4.11(b), we find an optimal point when the width of inner inverter is 400nm.

150 200 250 300 350 400 450 16

150 200 250 300 350 400 450 290

Figure 4.11. Inner inverter sizing. (a) Delay and power simulation. (b) PDP value simulation

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4.2.7 Proposed level converter performance

Combining the above mentioned techniques, the overall PDP value can be reduced up to 23%, as Fig. 4.12(c) shown. By connecting two PMOS diodes, the conventional cross-coupled level converter can successfully convert the signal from the sub-threshold region to super-threshold region. Using multi-V_th devices improve the propagation delay up to 22%, as Fig. 4.12(a) shown. The leakage reduction technique compensates the LVT logic leakage problem so that the power can be reduced up to 26%, as Fig. 4.12(b). Employing the reverse short channel effect reduce the PDP value approximately up to 17%. Applying these techniques make the proposed level converter more robust and reliable.

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