Summary

The SOI neutral-body coupling effect should be considered for the characterization and modeling of SOI MOSFETs, although the thick buried oxide can block the complicated substrate network. An equivalent circuit including the neutral-body parasitics has been proposed, and a new set of model equations capturing the frequency dependence of extrinsic resistances and output characteristics has been derived accordingly. After taking into account the impact of quasi-neutral body, we have completed a physically accurate RF small-signal characterization and modeling for SOI MOSFETs.

The neutral-body parasitics predict and explain the existence of anomalous S₂₂ and S21 behaviors, and they can influence the RF output characteristics of SOI MOSFETs.

References

[1] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, “Substrate crosstalk reduction using SOI technology,” IEEE Trans. Electron Devices, vol. 44, pp. 2252–2261, Dec.

1997.

[2] E. Zencir, N. S. Dogan, and E. Arvas, “Modeling and performance of spiral inductors in SOI CMOS technology,” IEEE Canadian Conference on Electrical and Computer Engineering, May 2002, pp. 408-411.

[3] J. Kim, J.-O Plouchart, and N. Zamdmer, “Design and manufacturability aspect of SOI CMOS RFICs,” in Proc. Custom Integrated Circuit Conf., Oct. 2004, pp. 541-548.

[4] T. Douseki, T. Tsukahara, Y. Yoshida, F. Utsunomiya, and N. Hama, “A batteryless wireless system with MTCMOS/SOI circuit technology,” in Proc. Custom Integrated Circuit Conf., Sept. 2003, pp. 163-168.

[5] J. P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker-Janvier, and J. P. Colinge, “Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling,” IEEE Trans. Electron Devices, vol. 45, pp.

1017–1025, May 1998.

[6] D. Lederer, D. Flandre, and J.-P. Raskin, “Frequency degradation of SOI MOS device output conductance,” Semicond. Sci. Technol., vol. 20, pp. 469–472, 2005.

[7] D. Lederer, O. Rozeau, and J.-P. Raskin, “Wideband characterization of body-accessed PD SOI MOSFETs with multiport measurements,” in Proc. IEEE Int. SOI Conf., 2005,

18

Wireless Components Lett., vol. 17, no. 5, pp. 364–366, May 2007.

[10] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, “RF extrinsic resistance extraction considering neutral-body effect for partially-depleted SOI MOSFETs,” in Proc. VLSI-TSA, Hsinchu, Taiwan, Apr. 2006, pp. 1-2.

[11] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, “Radio-frequency silicon-on-insulator modeling considering the neutral-body effect,” Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2087-2091, April 2008.

[12] C. L. Chen et al., “High-frequency characterization of sub-0.25-μm fully depleted silicon-on-insulator MOSFETS,” IEEE Electron Device Lett., vol. 21, pp. 497–499, Oct.

2000.

[13] J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge, “Direct extraction method of SOI MOSFET transistors parameters,” in Proc. IEEE Int. Conf. Microelectron. Test Structures, vol. 9, pp. 191-194, Mar. 1996.

[14] J.-P. Raskin, G. Dambrine, and R. Gillon, “Direct extraction of the series equivalent circuit parameters for the small-signal model of SOI MOSFET’s,” IEEE Microwave Guided Wave Lett., vol. 7, no. 12, pp. 408-410, Dec. 1997.

[15] A. Bracale, V. Ferlet-Cavrois, N. Fel, D. Pasquet, J. L. Gautier, J. L. Pelloie, and J. du Port de Poncharra, “A new approach for SOI devices small-signal parameters extraction,” in Analog and Integrated Circuits and Signal Processing. Norwell, MA:

Kluwer, 2000, pp. 157-169.

[16] D. Lovelace, J. Costa, and N. Camilleri, “Extracting small-signal model parameters of silicon MOSFET transistors,” in Proc. IEEE MTT-S Dig., 1994, pp. 865–868.

[17] W. Liu et al, “R.F.MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model,” in Proc. Int. Electron Devices Meeting, Dec. 1997, pp. 309–312.

[18] R. T. Chang et al., “Modeling and optimization of substrate resistance for RF-CMOS,”

IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 421–426, Mar. 2004.

[19] S. Lee, “Response to Comments on ‘A direct extraction technique for a small-signal MOSFET equivalent circuit with substrate parameters’,” Microwave Opt. Technol. Lett., vol. 43, pp. 268-269, 2004.

[20] R. Howes and W. Redman-White, “A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFETs,” IEEE J. Solid-State Circuits, vol. 27, pp. 1186–1192, Oct. 1992.

20

Table 2-1 Extracted model parameters for the extrinsic resistances. The values of

G F

F N N

W

L/ / / for FET1, FET2 and FET3 are 0.12μm/2.4μm/16/3, 0.12μm/1.8μm/2/18, and 0.12μm/3.6μm/11/4, respectively.

W ( μm )

A (10²¹F^1s^1)

B (10²⁰s^2)

s

Rd_

( )

s

Rg_

(  )

d

Rg_

( ) Rs

( ) Rd

( ) Rg

( )

FET1 115.2 4.9 7.2 1.4 1.45 2.15 0.1 1.5 1.4

FET2 64.8 6.4 6.4 2.9 1.35 2.8 0.1 3 1.3

FET3 158.4 3.5 7.4 0.9 1.55 2 0.1 1 1.5

Table 2-2 Extracted model parameters for the intrinsic modeling. (V_GS = 1.2V )

) V

DS(

V C_gs(fF) C_gd(fF) g_m(mS) C_ds(fF) R_ds() R_b() C_j,sb(pF) C_j,db(pF) g_mb(mS)

0.8 109 56 96 14 119 63 61 50 32

1 109 53 96 24 156 73 64 58 25

1.2 109 51 96 29 167 88 74 20 53

22

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0 10 20 30 40 50 60 70

V

_GS

= 0.4 V V

_GS

= 0.8 V V

_GS

= 1.2 V

I

D

(mA)

V

_DS

(V)

Figure 2-1 I_D versus V_DS curves for the RF SOI MOSFETs showing their properties of being partially depleted. (L/W_F/N_F /N_G = 0.12μm/2.4μm/16/3)

Figure 2-2 Traditional equivalent circuit for the bulk MOSFET under the zero condition.

24

0 5 10 15 20

-10 -5 0 5 10 15 20 25 30 35 40

Curves for resistance extraction ()

Frequency (GHz)

Re(Z₁₂) for bulk MOSFET Re(Z

22-Z

12) for bulk MOSFET Re(Z₁₁-Z₁₂) for bulk MOSFET Re(Z₁₂) for SOI MOSFET Re(Z

22-Z

12) for SOI MOSFET Re(Z₁₁-Z₁₂) for SOI MOSFET

Re(Z₁₂) for SOI MOSFET with substrate RF ground Re(Z

22-Z

12) for SOI MOSFET with substrate RF ground Re(Z₁₁-Z₁₂) for SOI MOSFET with substrate RF ground

Figure 2-3 Resistance curves for the bulk and PD SOI MOSFETs. (L/W_F /N_F /N_G = μm/16/3

4 . 2 / μm 12 .

0 )

Figure 2-4 (a) Cross-sectional view of the SOI MOSFET under the zero condition, and (b) its corresponding equivalent circuit.

(a)

(b)

26

Re( Z

12

) and Re( Z

22

-Z

12

) (  )

Frequency (GHz)

Figure 2-5 Model-data comparison for the extraction of extrinsic resistances.

(L/W_F /N_F/N_G = 0.18μm/2.4μm/16/3)

0 5 10 15 20 -10

-8 -6 -4 -2 0 2 4 6 8 10

0 2 4 6 8 10 12 14 16 18 20 L_f/W_f/NF/NG = 0.12m/2.4m/16/3 L_f/W_f/NF/NG = 0.12m/1.8m/2/18 Lf/W

f/NF/NG = 0.12m/3.6m/11/4

Re(Z₂₂-Z₁₂) Re(Z₁₁-Z₁₂)

Re(Z

11

-Z

12

) or Re(12) (



)

Frequency (GHz)

Re(Z₁₂)

Re(Z

22

-Z

12

) (



)

Figure 2-6 Modeling results for extrinsic resistance extraction considering the neutral-body effect. (symbols: measured data; lines: models)

28

0 1 2 3 4 5 6

-8 -7 -6 -5 -4 -3 -2 -10123 4 5 6 7 8 9

100 2 4 6

-2 -1 0 1 2

L_f/W_f/NF/NG = 0.12um/2.4um/16/3 L_f/W_f/NF/NG = 0.12um/1.8um/2/18 L_f/W_f/NF/NG = 0.12um/3.6um/11/4 Re(Z11-Z

12)

Re(Z 11-Z 12) or Re(Z 22-Z 12) ()

Re(Z12) () Re(Z₂₂-Z₁₂)

Re(Z11 -Z12 ) () Re(Z₂₂-Z₁₂) ()

Figure 2-7 Correlation between Re



Z₂₂ Z₁₂



, Re Z

 

₁₂ , and Re



Z₁₁Z₁₂



. (symbols:

measured data; lines: models)

Figure 2-8 Intrinsic small-signal model considering the neutral-body effect for the SOI MOSFET.

30

0 1 2 3 4 5 6 7 8 9 10

0 20 40 60 80 100 120

20 40 60 80 100 120 140

C gs and C gd (fF)

Frequency (GHz) C_gd

C_gs

gm (mS) gm

Figure 2-9 Modeling results of C_gs, C_gd and g_m. (symbols for measured data, lines for models, and L/W_F /N_F /N_G = 0.12μm/3.6μm/16/2)

0 1 2 3 4 5 15

20 25

V_DS = 1.2 V, V_GS = 1.2 V V_DS = 1 V, V_GS = 1.2 V G out (mS)

Frequency (GHz) V_DS = 0.8 V, V_GS = 1.2 V

0 1 2 3 4 5

0 50 100 300 400 500

V_DS = 0.8 V, V_GS = 1.2 V VDS = 1 V, V

GS = 1.2 V VDS = 1.2 V, V

GS = 1.2 V

C out (fF)

Frequency (GHz)

Figure 2-10 Modeling results of (a) G_out, and (b) C_out. (symbols for measured data, lines for models, and L/W /N /N = 0.12μm/3.6μm/16/2)

(a)

(b)

32

measurement

simulation without NBE simulation with NBE

A

simulation without NBE simulation with NBE

A

simulation without NBE simulation with NBE

S21

simulation without NBE simulation with NBE

S21

34

simulation without NBE simulation with NBE measurement

simulation without NBE simulation with NBE

|S 22|

simulation without NBE simulation with NBE

|S 21|

simulation without NBE simulation with NBE

S21 , ()

Bias A

Bias B Bias A

Figure 2-13 Modeling results of (a) S₂₂ and S₂₂, and (b) S₂₁ and S₂₁ with and without considering the neutral-body effect (NBE). The bias conditions for Bias A and B are

V

0.8 0.9 1.0 1.1 1.2

36

0.8 0.9 1.0 1.1 1.2 0.0

0.5 1.0 1.5 2.0 2.5 3.0

V_GS = 1 V V_GS = 1.2 V



V_DS (V) V_GS = 0.8 V

Figure 2-15  versus V_DS for different V_GS. (L/W_F /N_F /N_G = 0.12μm/3.6μm/16/2)

Chapter 3

RF Noise Characterization for Bulk and SOI MOSFETs

3.1 Introduction

The noise performance of RF MOSFETs is critical to RF applications, especially to the design of low noise amplifiers, resulting in a need for the accurate noise modeling [1].

Besides, it is well known that both the small-signal circuit parameters and noise sources play important roles in RF noise modeling. There have been many studies on the RF noise characterization and modeling for both bulk and SOI MOSFETs [1]-[9], and the temperature dependence of their small-signal performances has also been widely discussed [10]-[12].

However, the study on the temperature dependence of their RF noise sources and noise parameters was deficient. Therefore, for the purpose of temperature modeling and understanding the underlying physics, the temperature dependence of RF noise behaviors demands investigation.

Pascht et al. have presented the temperature noise model by exploiting the circuit simulator [2]. However, only the noise source for the bulk MOSFET has been discussed, and its temperature dependence was not clear. In this chapter, we will experimentally study the temperature dependence of the power spectrum densities (PSDs) of the intrinsic noise sources

38

are fixed to 3.6 μm , 16 and 2, respectively. For SOI MOSFETs, the thicknesses for gate oxide, SOI layer and buried oxide are 1.4 nm, 40 nm, and 200 nm, respectively.

The noise parameters of the device under different temperatures were measured using ATN NP5B noise parameter measurement system. The pads and series parasitics were de-embedded to obtain the intrinsic noise parameters. Then, the intrinsic noise current sources can be extracted by following the approach presented in [3], which is based on the noise matrix manipulation derived from the two-port noise theorem.

3.3 RF Noise Characterization for Bulk MOSFETs

3.3.1 RF Noise Characteristics for Medium-Long Devices

In this sub-section, we will first discuss the RF noise behaviors for the medium-long device (L0.36μm ) [13].

The van der Ziel’s model widely adopted to characterize the PSDs for the drain-induced gate noise (S_ig), channel noise (S_id), their correlation noise (Sigd*) can be expressed as follows [7][14].

0

to 3-3, respectively.

In these figures, one can find that S_ig and Sigd* would become larger for higher ambient temperature. For S , however, it tends to decrease with increasing temperature. To _id explain these different trends, Table 3-1 lists the extracted C , ₀ g and their normalizations _d0 with respect to their cases at 40℃. Besides, the extracted model parameters  ,  and  for different temperatures are also shown in Fig. 3-4. It is also worth noting that the van der Ziel’s model was originally derived for long channel devices, and the model parameters should be _sat 16135 ,_sat 2 3 ,and_sat 19 in the saturation region. It is no surprise that for the short channel device as in our study, the parameters could deviate from these theoretical values [3]-[5].

The small variations for  ,  and  shown in Fig. 3-4 reveal that they are less temperature-dependent, and may not be the main contribution to the temperature dependence of these three PSDs. In addition, C in Table 3-1 is shown to be insensitive to temperature. ₀ Therefore, for a given operating frequency, the following approximations can be achieved.

0 d

ig g

S  T (3-4)

0 d

id Tg

S  (3-5)

T

S_igd*  (3-6)

Equation (3-6) directly captures the positive temperature coefficient observed for Sigd*.

On the other hand, as temperature increases, the channel mobility would decline [10],

40

Finally, the extracted values for the model parameters and the correlation coefficient for various gate and drain biases are shown in Figs. 3-5 (a)~(d). It suggests that in the wide temperature range between 40℃ and 200℃,  ,  , and c / j have a larger temperature dependence at higher V , while _GS  has a larger temperature dependence only for a lower V . GS

3.3.2 RF Noise Characteristics for Deep-Submicron Devices

We now turn to investigate the RF noise behaviors for deep-submicron MOSFETs. Since compared to the channel noise, both the drain-induced gate noise and the correlation noise between them have been shown to play an insignificant role in determining the high- frequency noise behaviors for devices down-scaled into/beyond deep-submicron regime [15], we will limit our studies on the channel noise source only.

Figure 3-6 shows the temperature dependence of noise factor  for devices with different channel lengths. One can see that the temperature dependence is weak even for

μm 12 .

0

L device biased at high V . This indicates that _GS g ’s temperature dependence is _d0 still the major factor determining the temperature dependence of channel noise S as _id suggested by Equ. (3-5). For L0.12μm device, since g does not decrease with _d0 temperature as much as that for both L0.24μm and L0.36μm devices (shown in Fig.

3-7), instead of decreasing with temperature, the channel noise relatively remains constant over the whole temperature range as shown in Fig. 3-8.

The minimum noise figure (NF_min) and the equivalent noise resistance (R ) are two _n important figures of merit (FOM) used to judge the noise performance of a device, and can be respectively written as [15][16]:

 

Note that in the above derivation, we have neglected the contribution from S_ig and S_igd.

From Equs. (3-8) and (3-9), we can see that except S_id, the trans-conductance g_m would play an important role in determining both intrinsic NF_min and R_n. The temperature dependence of g_m for devices with different channel lengths is shown in Fig. 3-9. It suggests that g_m decreases with temperature at a rate larger than that for S_id . Therefore, according to Equs. (3-8) and (3-9), both NF_min and R_n would tend to degrade and become larger with increasing temperature as shown in Figs. 3-10 (a) and (b), respectively.

3.4 RF Noise Characterization for SOI MOSFETs

Figure 3-11 shows the noise factor  for both the bulk and SOI devices. It shows that, in the medium-long channel devices (L0.36μm),  seems to remain the same for both SOI and bulk devices. However, the SOI devices would have an increasing  as the channel length shrinks. Two mechanisms may contribute to this phenomenon: floating body effect (FBE) and self-heating effect (SHE) [20]. Due to the floating body structure of the SOI nMOSFET, there is a potential barrier between the source and the body region. Therefore, the holes generated by impact ionization [19] at high drain bias condition can be easily trapped in

42

[19] at lower V_GS (V_dd 2), FBE would have a larger impact on the excess noise at lower VGS.

On the other hand, as V_GS increases, the DC power and therefore the temperature of the SOI MOSFET increases due to the so-called self-heating effect [18][19]. This effect is caused by poor thermal conductivity of the buried oxide, which is about two orders of magnitude less than that of the silicon [18][19], and the lattice temperature would play an important role in determining the SOI MOSFET noise characteristics [8]. Besides, the noise arising from the neutral-body resistance should be enhanced by the elevated lattice temperature and its contribution to the channel noise S_id may have to be considered. However, since the effective mobility and hence channel conductance should be decreased accordingly, the excess noise caused by SHE would partly counterbalanced by the reduction of channel conductance.

This captures the slight increase of  at high V_GS (see Equ. (3-2)). It is worth noting that since the SHE may reduce the body potential by inducing more diode leakage [20], the excess noise caused by FBE at high V_GS could be further alleviated.

Figure 3-12 shows the temperature dependence of  for both SOI and bulk devices.

Since the FBE can be eliminated at high temperature [17], the channel suffering less FBE would have decreasing  with increasing temperature. This is especially obvious at low VGS, where FBE dominates the excess channel noise behavior. For bulk devices, since they suffer neither FBE nor SHE, they have the similar  over the whole temperature region.

Finally, we compare NF_min and R_n for the SOI and bulk devices for a given DC power consumption. Figure 3-13(a) and (b) respectively show the comparison of S_id and g_m versus current for a given drain voltage (V_DS 1.0V). Because SOI device has larger S_id and lower g_m than the bulk counterparts in our experiments, referring to Equs. (3-8) and (3-9), it is expected that it would has worse NF_min and R_n as shown in Fig. 3-14(a) and (b), respectively. It is worth noting that the extrinsic parameters, such as gate capacitance and terminal resistances would not significantly contribute to the deviations, since both devices

have been checked to have similar C_gg (see Fig. 3-13(c)) and terminal resistances (shown in Table 3-2) for each temperature.

It should be noted that we have neglected the neutral-body effect on the RF characterization in this section. This is because the previous chapter has demonstrated the insignificant neutral-body effect on the RF small-signal characteristics of SOI MOSFETs except the output admittance. Besides, the body trans-conductance and drain leakage current have been presented to have significant effect mostly on the low frequency noise behavior due to its low-pass nature [21]. Note that at the very high frequency, the neutral-body resistance Rb would be equivalently parallel to the channel resistance and can contribute to the output noise current associated with the drain terminal. However, its thermal noise contribution is at the level of about 4k_BT R_b 1.6610^22A² Hz (for R_b 100Ω), and can be neglected compared with the extracted S_id (see Fig. 3-13(a)).

3.5 Summary

We have investigated the temperature dependence of S_ig , S_id and S_igd* for the

medium-long RF MOSFET. S_ig and S_igd* are found to have positive correlation with ambient temperature, while S_id has negative one due to much lower channel conductance at higher temperature. For L0.12μmdevice, however, since g_d0 does not decrease with temperature as much as that for both L0.24μm and L0.36μm devices, S_id relatively

44

contribution to S_id may not be significant.

Finally, since the trans-conductance decreases with temperature in a rate higher than that for S_id, both NF_min and R_n would increase accordingly. Our experiment also shows that the SOI device has worse NF_min and R_n due to the larger S_id and lower g_m than the bulk counterpart.

References

[1] A. J. Scholten, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, A. T. A. Zegers-van Duijnhoven, and V. C. Venezia, “Noise modeling for RF CMOS circuit simulation,”

IEEE Trans. Electron Devices, vol. 50, pp. 618–632, Mar. 2003.

[2] A. Pascht, M. Grozing, D. Wiegner, and M. Berroth, ‘Small-signal and temperature noise model for MOSFETs’, IEEE Trans. Microw. Theory Tech., vol. 50, no. 8, pp. 1927–1934, Aug. 2002.

[3] C.-H. Chen, M. J. Deen, Y. Cheng, and M. Matloubian, “Extraction of the induced gate noise, channel noise, and their correlation in submicron MOSFETs from RF noise measurements,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2884-2892, Dec.

2001.

[4] K. Han, H. Shin, and K. Lee, "Analytical drain thermal noise current model valid for deep submicron MOSFET's," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 261~269, Feb. 2004.

[5] K. Han, J. Gil, S.-S. Song, J. Han, H. Shin, C.-K Kim, and K. Lee, "Complete high frequency thermal noise modeling of short-channel MOSFETs and design of 5.2 GHz low noise amplifier," IEEE J. Solid-State Circuits, vol. 40, no. 3, pp.726~269, Mar. 2005.

[6] M. J. Deen, C.-H. Chen, S. Asgaran, G. A. Rezvani, J. Tao, and Y. Kiyota,

“High-frequency noise of modern MOSFETs: Compact modeling and measurement issues”, IEEE Trans. Electron Devices, vol. 53, no. 9, pp.2062-2081, Sep. 2006.

46

and bulk-silicon MOSFETs for RF applications, ” IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 872-880, Sep. 2008.

[10] S. M. Nam, B. J. Lee, S. H. Hong, C. G. Yu, J. T. Park and H. K. Yu, "Experimental investigation of temperature dependent RF performances of RF-CMOS devices," in Proc.

6th Int. Conf. VLSI CAD (ICVC’99), 1999, pp. 174–177.

[11] Y. S. Lin, “Temperature dependence of the power gain and scattering parameters s11 and s22 of an RF nMOSFET with advanced RF-CMOS technology,” Microw. Opt. Technol.

Lett., vol. 44, no. 2, pp.180–185, Jan.20, 2005.

[12] M. Emam, D. Vanhoenacker-Janvier, K. Anil, J. Ida and J.-P. Raskin, “High temperature RF behavior of SOI MOSFETs for low-power low-voltage applications,” in Proc. IEEE Int. SOI Conf., 2008, pp. 139–140.

[13] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, ‘Temperature dependence of high frequency noise behaviors for RF MOSFETs,” IEEE Microw.

Wireless Comp. Lett., vol. 18, pp. 530-532, Aug. 2008.

[14] A. van der Ziel, Noise in Solid State Devices and Circuits, Now York: Wiley, 1986.

[15] S.-C. Wang, P. Su,K.-M. Chen, K.-H. Liao, B.-Y. Chen, S.-Y. Huang, C.-C. Hung, and G.-W. Huang, “Comprehensive noise characterization and modeling for 65-nm MOSFETs for millimeter-wave applications,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 4, pp. 740–746, Apr. 2010.

[16] J. Jeon, I. Song, I. M. Kang, Y. Yun, B.-G. Paark, J. D. Lee, and H.Shin, “A new noise parameter model of short-channel MOSFETs,” in IEEE Radio Freq. Integr. Circuits Symp., Jun. 2007, pp. 639–642.

[17] S. C. Lin and J. B. Kuo, “ Temperature-dependent kink effect model for partially-depleted SOI NMOS devices,＂ IEEE Trans. Electron Devices, vol. 46, pp.

254–258, Jan. 1999.

[18] L. Su, J. Chung, D. Antoniadis, K. Goodson, and M. Flik, “Measurement and modeling of self-heating in SOI NMOSFETs,” IEEE Trans. Electron Devices, vol. 41, p. 69, Jan.

1994.

[19] P. Su, K.-I. Goto, T. Sugii, and C. Hu, “Enhanced substrate current in SOI MOSFETs,”

IEEE Electron Device Lett., vol. 23, no. 5, pp. 282–284, May 2002.

[20] P. Su, S. K. H. Fung, S. Tang, F. Assaderaghi, and C. Hu, “BSIMSPD: A partial-depletion SOI MOSFET model for deep-submicron CMOS designs,” in Proc. IEEE Custom Integr.

Circuits Conf., 2000, pp. 197–200.

[21] W. Jin, P. C. H. Chan, S. K. H. Fung, and P. K. Ko, “Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFETs,” IEEE Trans.

Electron Devices, vol. 46, pp. 1180–1185, June 1999.

48

Table 3-1 Extracted g_d0, C₀ and their normalizations with respect to cases at -40℃ for the bulk MOSFET. (L0.36 μm )

 

^K

T T

 

K g_d0(mS) g_d0 C₀(fF) C ₀

40

T  ℃ 233 ^1 112.4 1 520 1

0

T ℃ 273 1.17 96 0.85 517 0.99

100

T ℃ 373 1.60 66 0.59 508 0.98

200

T ℃ 473 2.03 51 0.45 506 0.97

Table 3-2 Extracted R_s, R_d, and R_g for both the SOI and bulk devices. (L0.12 μm )

SOI BULK

()

Rs R_d() R_g() R_s() R_d() R_g()

 23

T ℃ 0.1 1.7 1.9 0.1 1.5 2.0

100

T ℃ 0.1 1.8 2.2 0.1 1.8 2.2

200

T ℃ 0.1 2.2 2.3 0.1 2.0 2.5

50

0 1 2 3 4 5 6 7 8 9 10 11 12

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

T = -40C T = 0C T = 100C T = 200C

S

ig

(10

-22

A

2

/Hz)

Frequency (GHz)

Figure 3-1 Induced gate noise (S_ig) versus frequency for the bulk MOSFET under different temperatures. (L0.36 μm , and V_GS V_DS 1.2V)

0 1 2 3 4 5 6 7 8 9 10 11 12 1.0

1.2 1.4 1.6 1.8 2.0

T = -40C T = 0C T = 100C T = 200C

S

id

(10

-21

A

2

/Hz )

Frequency (GHz)

Figure 3-2 Channel noise (S_id) versus frequency for the bulk MOSFET under different temperatures. (L0.36 μm , and V_GS V_DS 1.2V)

52

0 1 2 3 4 5 6 7 8 9 10 11 12

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

T = -40C T = 0C T = 100C T = 200C

S

igd*

(1 0

-22

A

2

/Hz )

Frequency (GHz)

Figure 3-3 Correlation noise (Sigd*) versus frequency for bulk MOSFET under different temperatures. (L0.36 μm , and V_GS V_DS 1.2V)

-50 0 50 100 150 200 0.0

0.2 0.4 0.6 0.8 1.0



,



,



, and c

Temperature (



C)





,



,



, and c c/j





Temperature (



C)

Figure 3-4 Model parameters  ,  ,  and correlation coefficient c versus temperature for the bulk MOSFET. (L0.36μm , and V_GS V_DS 1.2V)

54 for different temperature and gate bias conditions for the bulk MOSFET. (L0.36μm )

(a) (b)

(c) (d)

-50 0 50 100150200

Noise Factor, 

VDS = 1.0V

-50 0 50 100150200 0.5

Temperature (C)

-50 0 50 100150200 0.5

Figure 3-6 Temperature dependence of  for bulk devices with different channel lengths.

56 -50 0 50 100150200 0

-50 0 50 100150200 0

Temperature (C)

-50 0 50 100150200 0

Figure 3-7 Temperature dependence of g_d0 for bulk devices with different channel lengths.

-50 0 50 100150200 -50 0 50 100150200

0.8

Temperature (C)

-50 0 50 100150200 0.5

Figure 3-8 Temperature dependence of S_id for bulk devices with different channel lengths.

58 -50 0 50 100150200

0

Trans-conductance, g m (mS)

-50 0 50 100150200 0

Temperature (C)

-50 0 50 100150200 0

Figure 3-9 Temperature dependence of g_m for bulk devices with different channel lengths.

-50 0 50 100 150 200

NF min@8GHz (dB)

-50 0 50 100 150 200

Temperature (C)

-50 0 50 100 150 200

-50 0 50 100150200 0

-50 0 50 100150200 0

Temperature (C)

-50 0 50 100150200 0

60

Noise Factor, 

Figure 3-11 Noise factor  for both SOI (symbols) and bulk (lines) devices with different channel lengths.

0 20 40 60 80 100 120 140 160 180 200 0

1 2 3 4 5

VDS = 1.0V

L=0.12m V_GS = 0.8V

V_GS = 1.0V V_GS = 1.2V

Noi s e Fac tor, 

Temperature (  C)

Figure 3-12 Temperature dependence of noise factor  for both SOI (symbols) and bulk (lines) devices.

62

S id (10-21 A2 /Hz)

S id (10-21 A2 /Hz)

在文檔中 先進金氧半場效電晶體考慮溫度相依之高頻小訊號及雜訊特性分析 (頁 33-0)