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The Proposed Method for Fine Symbol Timing Synchronization

Chapter 4 Synchronization Techniques for MIMO OFDM Systems

4.3 Symbol Timing Synchronization

4.3.2 Fine Symbol Timing Synchronization

4.3.2.2 The Proposed Method for Fine Symbol Timing Synchronization

The CFDFS method with IFFT should introduce serious round-off errors, this phenomenon can be analyzed further in the future. For the reason, without resorting to frequency-domain operations we propose the direct time-domain fine symbol timing synchronization (DTDFS) method based on circular convolution to estimate the channel impulse response.

*

Since the estimation error is less than +/- 5 samples after the coarse symbol timing estimation, we can reduce the computation complexity by directly calculating time-domain circular convolution outputs in the range of the +/- 5 points as shown by Equation (4.24) and adjust the fine symbol timing. This simplified method is defined as simplified direct time-domain fine symbol timing synchronization (STDFS) method.

( )

m r

( )

m x

( )

m m N N N

hˆn = nn* − =1,2,..,5 & −4, −3,.., (4.24) Table 4.1 shows the computation complexity of the three methods, we can find that the computation complexity of the proposed STDFS method is almost the same as the conventional IFFT method or even less, when the number of subcarriers is large and

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the range for adjustment is small. Furthermore, the proposed method based on simplified circular convolution uses the received signal for computation directly. For the reason, the proposed SFDFS method should reduce the round-off errors in practice.

Table 4.1 The computational complexity comparison of fine symbol timing estimation.

Methods No. of multiplications No. of additions CFDFS [25, 26] (Radix-2) N×log2 N+N 2N×log2 N

Proposed DTDFS N 2 N

(

N−1

)

Proposed STDFS L×N L

(

N −1

)

N: FFT length L: the range for fine search and adjustment

4.4 Sampling Clock Offset Synchronization

4.4.1 Sampling Clock Offset Estimation

4.4.1.1 Conventional Methods for Sampling Clock Offset Estimation [27,28]

Sampling clock offset results in a slow shift of sampling instants, and rotating the phase of data carried by subcarriers. For analyzing the sample clock offset, we define the normalized sampling clock offset as β in (4.25). The n-th received symbol with clock offset β can be expressed as (4.26)

s s s

T T T

= '

β (4.25)

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where Ts and Ts` are the transmitter sampling period and the receiver sampling period respectively. where N is the number of subcarriers, and Ng is the length of guard interval.

The method for sampling clock synchronization adopted here for acquisition uses the phase difference between two consecutive training symbols [27] as shown in Equation (4.28).

)

In the equation, by conjugating the (n-1)-th symbol and multiply it with the n-th symbol, the channel phase will be eliminated and the phase difference can be calculated. With the information of the phase difference, the sampling clock offset can be estimated using the information with various feasible ways. (4.29), (4.30), and (4.31) show three possible estimation schemes.

Method 1 [27]: carryingk pilot tones

k k k right averagek Z Y left averagek Z Y

=

42

) 1(

) (

2 Yright Yleft

C Ng N

N × ∠ −∠

= +

β) π (4.30)

Method 1 directly averages the overall phase-difference cases between any two pilot subcarriers and estimate the clock offset. Method 2 first separates the pilot carriers in two groups, then finds the difference of their averaged phase values, and finally estimates the clock offset.

4.4.1.2 The Proposed Method for Sampling Clock Offset Estimation

Method 1 treats the all phase-difference cases between any two pilot subcarriers equally and estimate the sampling clock offset by averaging all the offset estimate samples. In Equation (4.29), we can find the phase differences of various pilot pairs are divided by different constants. Since the constant is the distance the pilot carriers, the ability of eliminating noise effect increases with the distance between the pilot carriers.

Owing to that the ability of eliminating noise effect increases with the distance between the pilot carriers, we propose the method (4.31) by only using the most separated pilot carriers to estimate the sampling clock offset and simultaneously reduce the computational complexity.

Proposed Method :

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⎥⎦

⎢ ⎤

⎡ ∠ − + − ∠ − +

+

= − (( ) ( ))

) )(

(

2 max min Zn,kmax n,kmax n 1,kmax Zn,kmin n,kmin n 1,kmin Ng

N k k

N φ φ φ φ

β) π

(4.31) When the number of receiver antennas is more than one, each receiver antenna performs the sampling clock offset estimation independently first. Since all the reception data streams use the same sampling clock oscillator, one can average all the estimated clock offset samples and obtain a low-noise clock offset estimation, then finally performs the clock offset compensation for all the reception data streams with the same clock offset.

4.4.2 Sampling Clock Offset Compensation

As soon as the sampling clock offset has been estimated, there are various feasible schemes to compensate the offset, such as adjusting the sampling frequency of ADC in the continuous-time domain, or rotating the FFT outputs in frequency domain, or correcting the timing by using a resampling interpolator in discrete-time domain.

The VCXO (Voltage-controlled crystal oscillator) is used to control the sampling frequency of ADC. However, a VCXO usually has higher cost and higher noise jitter than a XO (Crystal oscillator). For these reasons, the scheme is not suitable for 802.11n.

When the sampling clock offset compensation is performed by rotating the FFT outputs in frequency domain, no over-sampling is needed and the timing error correction can be done by a single complex multiplication. However, this method works well only when a small frequency offset is guaranteed. Accurate and expensive

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XOs are required at both transmitter and receiver sides. Furthermore, the cost of updating the rotor coefficients is quite high. If a look-up table is used for coefficient updating, it will require a large memory.

Various interpolators [29,30,31,32,33] have been proposed to usually perform the compensation by time-domain resampling and applied to the compensation structure, shown in Figure 4.6. With a free-running oscillator, timing correction can be done by some discrete-time signal processing techniques on sample sequence. A simple interpolator may be a finite impulse response filter (FIR) that produces a fractional delay. The interpolator coefficients are time-varying, because they depend on the timing error to correct. Due to the time-varying filtering, the FFT output data suffers a time-varying phase rotation and attenuation. Such distortion introduces additional noises, especially on high frequency subcarriers that are close to the Nyquist frequency.

The noise can be reduced by over-sampling the received signal or by using a high-order interpolator. However, due to the high sampling rate and high computation complexity, those schemes might not be suitable for very high-rate systems.

ADC FFT

Phase Error Detector

to next stage Interpolator

Timing

&

Carrier Frequency Synchronization

Figure 4.6 Structure of discrete-time resampling timing correction.

In the following subsections, we will find suitable interpolators with low complexity and high performance.

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4.4.2.1 Designs of Digital Resampling [43]

Figure 4.7 shows an ideal fractional delay (FD) block, which can be viewed as a digital version of a continuous- time delay line. Therefore, the impulse response of an LSE (least square error) fractional delay filter is a shifted and sampled sinc function.

) ( sin )

(n c n D

h = − (4.32)

where n is the sample index and D is the delay with a fractional part d = D-floor(D) and an integral part floor(D).

S(n) h(n) S(n-D)

Figure 4.7 The discrete- time delay block.

- 4 - 3 - 2 - 1 0 1 2 3 4

- 0 .4 - 0 .2 0 0 . 2 0 . 4 0 . 6 0 . 8 1

S a m p le I n d e x (n )

Impulse response h(n)

(a)

46

- 4 - 3 - 2 - 1 0 1 2 3 4

- 0 .2 0 0 . 2 0 . 4 0 . 6 0 . 8

S a m p le I n d e x ( n )

Impulse Response h(n)

(b)

Figure 4.8 The impulse response of the sinc interpolator with the delay (a) d=0.0, (b) d=0.3

Figure 4.8 shows the LSE sinc impulse response when d=0 and d=0.3. Since the impulse response of sinc fraction delay filter is infinite-length, it should be truncated for practical applications. Since its impulse response is not absolutely summable and suffers from the well-known Gibbs phenomenum, the sinc FD filter is impractical with poor performance.

To design an efficient FD filter, finite-length, truncated and properly windowed sinc functions with small Gibbs phenomenon are desired. Signal interpolation is conceptually equal to a resampling operation on reconstructed signals in continuous-time domain. In order to obtain the reconstructed continuous-time signals, least-square interpolation, equirriple interpolation, windowed-sinc interpolation and polynomial-based interpolation are frequently used. In this work, we use various interpolators to perform the compensations, and assess theier performances when applied to IEE802.11n standard.

Since a resampling interpolator’s coefficients are time-varying, the introduced

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time-varying phase rotation and attenuation are difficult to be equalized. Before simulating these interpolators, let’s check the frequency responses of some popular interpolators [43].

Figure 4.9 (a) (b) (c) (d) shows the responses of 4-tap fractional-delay FIR filters, which are obtained from several major windowed sinc functions. Figure 4.10 (a), (b), (c) , and (d) shows the responses of various 4-tap fractional-delay FIR filters, which are designed by general least-squares approximation, equirriple approximation, Lagrange interpolation and Cubic B-spline interpolation, respectively. Since the received data will be demodulated and decoded in frequency domain, frequency responses of those interpolators are important. Due to time-varying coefficients, a fractional delay FIR has different frequency responses with respect to the fractional part d of input delay D.

The magnitude response error and phase delay error will introduce additional noise. Therefore, an interpolator with small phase error and small magnitude response error is desired. In Figure 4.9 and 4.10, we can find that the magnitude distortion of the Cubic B-spline interpolation is serious at the high frequency band especially. For the reason, the performance of the Cubic B-spline interpolation is poor in its application to IEEE 802.11n. We will simulate these interpolation designs in the next chapter and find suitable designs for IEEE 802.11n.

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NORMALI ZED FREQUENCY

MAGNITUDE

NORMALI ZED FREQUENCY

PHASE DELAY

NORMALI ZED FREQUENCY

MAGNITUDE

NORMALI ZED FREQUENCY

PHASE DELAY

NORMALI ZED FREQUENCY

MAGNITUDE

Windowed Sinc [Kaiser] L=4beta=3.3 wp= 1

0 0.2 0. 4 0.6 0.8 1

NORMALI ZED FREQUENCY

PHASE DELAY

NORMALI ZED FREQUENCY

MAGNITUDE

Windowed Sinc [Chebyshev] L=4 alpha= 40 wp=1)

0 0.2 0. 4 0.6 0.8 1

NORMALI ZED FREQUENCY

PHASE DELAY

(c) (d)

Figure 4.9 Frequency responses of windowed Sinc FIR FD filters: (a) Rectangular window; (b) Hamming window; (c) Kaiser window; (d) Chebyshev window.

d=0

49

NORMALI ZED FREQUENCY

MAGNITUDE

NORMALI ZED FREQUENCY

PHASE DELAY

NORMALI ZED FREQUENCY

MAGNITUDE

NORMALI ZED FREQUENCY

PHASE DELAY

NORMALI ZED FREQUENCY

MAGNITUDE

NORMALI ZED FREQUENCY

PHASE DELAY

(c) (d)

Figure 4.10 Frequency responses of various FIR FD filters: (a) General least-squares approximation; (b) Equirriple approximation; (c) Lagrange interpolation; (d) Cubic

d=0 d=0

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B-spline interpolation

4.4.2.2 Discrete-time Over-resampling Techniques [34,35,36]

The windowed-sinc and some other FD interpolators obtained from other key design techniques, discussed in the previous section are realized by resampling the reconstructed analog functions from the original discrete samples. Intuitively, pure digital signal interpolation is a fundamental approach for FD interpolation. One can perform digital “over-sampling” operations [35,36] to achieve high-resolution FD.

With N-times oversampling, one can split a unit delay into N divisions, as shown in Figure 4.11. In the figure, H(z) is an Nth-band low-pass filter. Note that the proto-type filter H(z) can be obtained by various optimization techniques, such as least-square and equirriple approximations.

N H(z)

Figure 4.11 Block diagram of a digital N-times over-sampling LTI interpolator.

An N-branch polyphase interpolator can be formed by polyphase decomposition techniques. In (4.33), z-transforms are used to derive a polyphase interpolator. Note that each branch is an L-tap filter, which is shown in Figure 4.12.

)

51

Figure 4.12 An oversampling interpolator in polyphase form: (a) the simplified polyphase structure; (b) and an equivalent polyphase interpolator with an output

commutator.

52

In the upsampling polyphsae structure, the kth branch is responsible for generating the samples with fractional delay of k/N, where k∈{0,1,...,(N−1)}. Although the upsampling operation is computationally intensive especially for high-resolution fractional delays, the complexity can be greatly reduced by only considering those required FD sampled. The upsampling-based digital FD interpolators are disadvantageous in that it can not realize arbitrary delay. To solve this problem, a well-known approach [28] is to approximate each branch’s polyphase filter coefficient as a pth-order polynomial of fractional delay d, as shown in (4.34). Usually, the approximating polynomial of the filter coefficients is obtained by fitting them in the least-squares sense.

}

where cm,n are real-valued coefficients of those approximating polynomials. Then the resulting interpolator will be able to produce continuous delay. In addition, the well-known Farrow structure can be applied to the approximating polynomials for low-complexity realization, which will be shown in the next section.

4.4.2.3 Farrow Structure [34,35,42]

Increasing filter length of an interpolator results in better phase and magnitude responses. However, the filter length of an interpolator cannot be arbitrarily long. Here are two reasons: First, the length of composite channel, including the transmission channel and the interpolator of the receiver, must be shorter than the guard interval to avoid ISI. Second, longer interpolator length means higher computational and hardware

53

complexities. After some trials, we found that a 4-tap interpolator is sufficient. To further reduce the complexity, Farrow structure is applied to implement the interpolator.

Since the fractional delay to be compensated varies over time. The design of high-quality FD filter is difficult. Farrow [35] suggested that every filter coefficient of the FIR FD filter could be expressed as a Pth-order polynomial in the variable delay parameter D.

Design a set of filters approximating a fractional delay in the desired range, 1

0≤ d, and then approximate each coefficient as a P-order polynomial of fractional delay. The transfer function of the filter becomes

This is the well-known Farrow structure, which is illustrated in Figure 4.13.

(.)

Figure 4.13 Farrow structure of an interpolator.

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An interpolator with Farrow polynomial approximation coefficients is able to produce continuous delays. The delay accuracy is affected by the filter length L and the Farrow polynomial order P. After some trials, we found that it is sufficient for an interpolator with L= 4 and P=3. Note that polynomial-based interpolator, such as Lagrange interpolation and B-spline interpolation, can be directly realized by the Farrow structure without further approximation.

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Chapter 5

Simulation Results and Comparisons

In this chapter, we will evaluate the performance of the discussed and proposed synchronization techniques, by applying them to IEEE 802.11n system, and compare the performances among various methods.

5.1 Simulation Environment

As for the simulation environment, AWGN channel and multi-path channel are assumed. Since IEEE 802.11 uses 5GHz band as the major carrier, we utilize the power delay profile measured in indoor environment at 5.3 GHz by using a wideband sounder

56

for simulations. Table 5.1 shows the model parameters.

Table 5.1 Channel Model Parameters [37] for simulations.

Tap No.

Delay (ns)

Power (dB)

Amplitude

Distribution Doppler Spectrum

1 0 0 Rayleigh Classical / Flat

2 36 -5 Rayleigh Classical / Flat

3 84 -13 Rayleigh Classical / Flat

4 127 -19 Rayleigh Classical / Flat

We assume the total transmit power from the multiple transmit antennas is the same as the transmit power from the single transmit antenna. It is also assumed the fading amplitudes from each transmit antenna to each receive antenna are mutually uncorrelated Rayleigh fading, and the averaged signal power at each receive antenna from each transmit antenna are the same.

Table 5.2 shows the simulated MIMO system parameters. Low mobility is considered in our simulations. Therefore, the Doppler shift frequency is set to 150Hz which corresponds to a mobility of 32 km/hr. We simulate some carrier frequency offset cases from 0.6 to 1.9 carrier spacing, and find the results are almost the same. For the reason, the carrier frequency offset is assumed as 1.35 carrier spacing in the following simulation environment. As for sampling clock offset, we simulate the clock offset by Lagrange interpolator with 50 interpolation taps, and try 50, 100, and 200 ppm cases, and find the results are almost the same. Therefore, the sampling clock offset is set to 100 ppm in the following simulations.

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Table 5.2 Simulated MIMO system parameters.

Sample period 50 ns

Total number of carriers 64

The number of pilot carriers 4

The number of data carriers 48

Symbol period 4µs

Guard interval 0.8µs

Modulation QPSK

Sampling frequency 20 MHz

Carrier spacing 312.5 kHz

Doppler shift frequency 150 Hz

Carrier frequency offset 1.35 carrier spacing

Sampling clock offset 100 ppm

Max. no. of Tx/Rx antennas 4/3

5.2 Performance of Frame Detection

Figure 5.1 shows the frame timing error probability due to frame detections. When the estimated frame timing is over 32 samples away from the exact frame start, we define it is a failed frame detection. The probability of failed frame detections is called the frame timing error probability. As the number of transmitter antennas is increased, the cyclical shift will also increase the difficulty of detecting the frame start. Even in

58

this condition, we can see that the probability is close to zero when the SNR is higher than 5 db.

Figure 5.1 The frame timing error probability vs. SNR due to the frame detection for various numbers of Tx antennas.

Figure 5.2 shows the estimated frame timing distribution due to the frame detection when the SNR is 10 db. The numbers of receiver antennas are all one. When the number of receiver antennas is more than one, the receiver antennas perform the frame detections independently. We can detect the frame start successfully, even if the number of spatial data streams is up to four.

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Figure 5.2 The estimated frame timing distribution due to the frame detection, SNR = 10 db, (a) NT=1. (b) NT=2. (c) NT=3. (d) NT=4.

60

Figure 5.3 The frame timing error probability vs. SNR due to the frame detection.

5.3 Performances of Symbol Timing Synchronization

For the reason mentioned above, the performance decreases slightly when the number of transmitter antenna increases. Figure 5.4 shows the probability of timing errors when there are more than 5 samples estimated error. We can find that the method we used for the coarse symbol timing estimation still works well even if the number of the spatial data stream is up to four.

Figure 5.5 shows the comparison among the three methods discussed in chapter 4 for the fine symbol timing estimation. The DTDFS method achieves the similar performance with the conventional CFDFS method. Its major drawback is the high computation complexity compared with the conventional CFDFS method. However,

61

the STDFS method has a smaller complexity than the previous two methods. Since the search range of fine symbol synchronization can be reduced to +/- 5 samples by the coarse symbol timing estimation, we can reduce the computation complexity significantly. The performance of the simplified time-domain method is also similar to the other two methods mentioned above as shown in Figure 5.5.

In Figure 5.7 and 5.8, it is assumed that the number of receiver antennas is one and the SNR is 10db. Figure 5.6 shows the MSE comparison between the coarse and fine symbol timing estimations by using the double-sliding-window method and the STDFS method, respectively. In this figure, the numbers of the transmit antennas and receive antennas are set to two and three, respectively. In these figures, we can find that the fine symbol timing estimation can achieve a significant improvement of the timing estimation accuracy. Table 5.3 shows the error probability comparison between the coarse and fine symbol timing estimations.

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Figure 5.4 The symbol timing error probability vs. SNR due to the coarse symbol timing estimation with the double-sliding-window method for various Tx antenna

numbers.

Figure 5.5 BER performance vs. SNR comparison of the discussed methods for fine symbol timing estimation.

63

Figure 5.6 MSE performance vs. SNR comparison between the coarse symbol timing estimation and the combined coarse and fine symbol timing estimation, NT=2,

NR=3.

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Figure 5.7 The estimated symbol timing distribution due to the coarse symbol timing synchronization, SNR = 10 db, (a) NT=1. (b) NT=2. (c) NT=3. (d) NT=4.

Figure 5.8 The estimated symbol timing distribution due to the fine symbol timing synchronization with STDFS method, SNR = 10 db, (a) NT=1. (b) NT=2. (c) NT=3. (d)

NT=4.

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Table 5.3 The error probability of the symbol timing estimation.

(a) The error is within +/-3 samples

1×1 2×3 4×3

NT×NR

SNR Coarse Fine Coarse Fine Coarse Fine

0 0.5787 0.4260 0.3413 0.1720 0.4633 0.2480

5 0.2013 0.0847 0.1100 0.0127 0.1840 0.0213

10 0.0133 0.0047 0.0180 0.0020 0.0220 0.0027

15 0 0 0.0027 0 0 0

20 0 0 0 0 0 0

25 0 0 0 0 0 0

(b) The error is within +/-1 samples

1×1 2×3 4×3

NT×NR

SNR Coarse Fine Coarse Fine Coarse Fine

0 0.7407 0.4553 0.6847 0.1987 0.6987 0.2773

5 0.4513 0.0933 0.5020 0.0193 0.4380 0.0340

10 0.1433 0.0053 0.3987 0.0027 0.2500 0.0087

15 0.0073 0 0.3407 0.0013 0.0733 0.0020

20 0 0 0.2713 0.0007 0.0053 0

25 0 0 0.1480 0 0 0

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5.4 Performance of Carrier Frequency Offset Synchronization

Here, we test the three discussed methods. We can see the improvement of the proposed smoothed method clearly in Figure 5.9. Since the other two methods use only one point to estimate the frequency offset, they have high noise level. The new

Here, we test the three discussed methods. We can see the improvement of the proposed smoothed method clearly in Figure 5.9. Since the other two methods use only one point to estimate the frequency offset, they have high noise level. The new

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