pendent double-gate (IDG) configuration. The device features oxide–nitride–oxide (ONO) stack as the charge storage medium in one of the two gated sides with pure oxide in the other. Owing to the IDG feature, the shift in the device’s transfer characteristics due to a change in the amount of storage charges can be sensed with two different modes, which have one of the two gates applied with a sweeping bias (driving gate) and the other with a fixed bias (control gate). Our analysis and experimental data show that a larger memory window is obtained when the gate of the ONO side is used as the driving gate. Moreover, the memory window of this mode is essentially independent of the bias applied to the control gate. Based on this finding, a novel Flash structure featuring IDG cells with a common control gate is proposed.
Index Terms—Independent double gate (IDG), nanowire
(NW), poly-Si, read disturb, silicon–oxide–nitride–oxide–silicon (SONOS).
I. INTRODUCTION
R
ECENTLY, driven by the tremendous increase in the demand of portable electronic products, the market of semiconductor nonvolatile memory, which is dominated by the floating-gate (FG) Flash technology, has been rapidly grow-ing. However, the aggressive scaling of FG Flash devices has encountered some serious challenges, including reliability issues caused by stress-induced leakage current, as well as critical short-channel and FG coupling effects [1]–[4]. Several types of devices with a nonvolatile property, including phase-change memory [5], ferroelectric and magnetoresistive mem-ory [6], [7], and silicon–oxide–nitride–oxide–silicon (SONOS) [8]–[11] memory have been proposed to overcome these scaling issues. Among these options, SONOS devices built with a multiple-gate (MG) poly-Si nanowire (NW) channel are very appealing due to their great potential for realizing 3-D mono-lithic integration of memory devices. A good example is the bit-cost scalable (BICs) Flash technology with the advantage Manuscript received May 7, 2011; revised July 4, 2011; accepted August 1, 2011. Date of publication September 12, 2011; date of current version October 21, 2011. This work was supported by the Ministry of Education in Taiwan under ATU Program, and National Science Council under Contract NSC 99-2221-E-009-167-MY3. The review of this paper was arranged by Editor H. S. Momose.H.-C. Lin is with the Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, and also with the National Nano Device Laboratories, Hsinchu 300, Taiwan (e-mail: [email protected]).
Z.-M. Lin,W.-C. Chen, and T.-Y. Huang are with the Department of Electron-ics Engineering and Institute of ElectronElectron-ics, National Chiao Tung University, Hsinchu 300, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2011.2164251
Fig. 1. Schematic structure of the n-type IDG device for analysis.
of ultrahigh density and reduced bit cost [12], [13]. These previous studies have shown that the use of an ultrathin NW channel can help relieve inherent threshold voltageVth
fluctu-ation problem caused by the grain boundaries contained in the poly-Si film. On the other hand, the adoption of MG schemes can enhance the gate controllability and increase the device’s immunity to the short-channel effects. Among a number of MG configurations, the independent double-gate (IDG) scheme is particularly worth studying [14]–[18]. Such scheme provides high flexibility in Vth adjustment; therefore, the demands for
high ON-state current Ion and low OFF-state current Ioff are
achievable [14]. Recently, we have proposed and developed a novel IDG NW poly-Si thin-film transistor [15]–[17] and also applied it to forming a SONOS device [18]. In our study, an oxide–nitride–oxide (ONO) was used as the gate dielectric for one of the independent gates, whereas a gate oxide layer was used for the other gate. Our study showed that greatly enhanced program/erase (P/E) speed can be obtained with appropriate IDG bias conditions as the channel is sufficiently thin [18]. A similar IDG SONOS structure can be found in the work of Walker [19] who demonstrated that the read–pass disturb can be suppressed. In this paper, we further study the read charac-teristics of IDG NW poly-Si SONOS devices. Special attention is paid on the operation of different read modes and the impact on memory window. Based on the results, a novel scheme is proposed for future high-density Flash memory application.
II. THEORETICALANALYSIS
The 2-D simplified structure of the n-type IDG silicon device is shown in Fig. 1. During measurements, the gate bias applied to the driving gate is swept to obtain the transfer characteristics, whereas a fixed voltage is applied to the control gate [18]. Fig. 2 illustrates the simplifiedVthcharacteristics of the device
Fig. 2. Vth(dri)−VG(con)characteristics of the n-type IDG device. Three distinctly different regions corresponding to various channel surface conditions of the control gate side can be defined.
Vth(dri) as a function of the control gate biasVG(con).
Accord-ing to the theory developed by Lim and Fossum [20], [21], the aboveVthcharacteristics can be divided into three regions,
as indicated in the figure. In regions I and III, the channel surface of the control gate side is respectively accumulated and inverted; thus, the Vth of the driving gate is pinned at Vth(dri),acc(con)andVth(dri),inv(con)and can be expressed as
Vth(dri),acc(con)= VFB(dri)+ 1+ Csi Cox(dri) 2φB−2Qdepl Cox(dri) (1)
Vth(dri),inv(con)= VFB(dri)+ 2φB−2Qdepl Cox(dri)
(2) respectively, where VFB(dri) is the flatband voltage of the
driving gate, Csi= ε0εsi/tsi is the silicon depletion
capaci-tance, Qdepl= qNAtsi is the total charges in the depleted Si
film,φB= (kT/q)ln(NA/ni) is the Fermi potential of the Si
channel, andCox(dri)= ε0εox/tox(dri)is the gate oxide
capaci-tance of the driving gate. In addition,NAis the doping density
in the silicon film,tsiis the thickness of the silicon film,kT /q is
the thermal energy, andniis the intrinsic carrier concentration.
In region II, the channel surface of the control gate side is de-pleted, and theVth(dri)can be adjusted by the appliedVG(con).
Boundaries of these regions are atVG(con,acc)andVG(con,inv),
which represent the onsets of the accumulated and inverted sur-faces of the control gate, respectively, and can be expressed as
VG(con,acc)= VFB(con)− Csi Cox(con)
2φB− Qdep
2Cox(con)
(3)
VG(con,inv)= VFB(con)+ 2φB− Qdep
2Cox(con)
(4) whereVFB(con)andCox(con) = ε0εox/tox(con)are the flatband
voltage of the control gate and oxide capacitance, respectively. AsVG(con)increases from VG(con,acc) toVG(con,inv), Vth(dri)
is linearly decreased from Vth(dri),acc(con) to Vth(dri),inv(con);
therefore, the Vth of the driving gate in region II can be
expressed as Vth(dri),depl(con)=Vth(dri),acc(con) − CsiCox(con) Cox(dri) Csi+Cox(con) VG(con)−VG(con,acc). (5)
Fig. 3. Schematic structure of the n-type IDG devices with extra negative charges incorporated in the gate oxide of G1.
Fig. 4. (a)Vth(dri)versusVG(con)characteristics and (b) memory window versusVG(con)read in mode I with or without extra charges incorporated. Furthermore, its slope is defined as the body factorβ, which is
expressed as β = CsiCox(con) Cox(dri) Csi+ Cox(con) . (6)
Next, we consider another situation shown in Fig. 3, which has two independent gates denoted as gate 1 (G1) and gate 2 (G2), and an amount of negative charges is contained in the gate oxide of G1. Since the two gates can be independently operated, two read modes can be applied. In mode I, the device is driven by G2, whereas G1 serves as the control gate to adjustVth(dri).
TheVth2(dri)−VG1(con) characteristics in mode I are shown in
Fig. 4(a), where the solid and dashed lines are individually related to the cases with and without the aforementioned extra fixed charges. The dashed line is the same as the one shown in Fig. 2. As shown in the figure, the Vth2(dri)− VG1(con)
V (Q)G1(con,acc)= VG1(con,acc)− qQ Cox1 (7) V (Q)G1(con,inv)= VG1(con,inv)− qQ Cox1 (8) Q = tox1 0 xρ dx tox1 (9) wheretox1,x, and ρ individually mean the oxide thickness of
G1, position, and charge density of the charges in the gate oxide of G1. The difference in Vth between the two characteristic
curves in Fig. 4(a) is defined as the memory window. Due to the right shift caused by the incorporated charges, the memory window operated in the region between points A and B is shown in Fig. 4(b), which shows a linear relation with respective to the bias of control gateVG1. In addition, its slope is determined by
body factorβ [see (6)]. Therefore, the memory window can be
expressed as
ΔVth = β
VG1− VG1(con,acc) (10)
β(body factor) = CsiCox1 Cox2(Csi+ Cox1).
(11) Next, we examine the properties of mode II in which G1 and G2 serve as the driving and control gates, respectively. In other words, the roles of G1 and G2 in mode I are switched in the present case. TheVth1(dri)−VG2(con)characteristics in mode II
are shown in Fig. 5(a), where the solid and dashed lines are re-spectively related to the cases with or without negative charges contained in the gate oxide of G1. It should be noted that the extra fixed charges contained in the gate oxide of G1 have no influence on the surface conditions of the channel gated by G2. This means that the voltages corresponding to the onsets of the accumulated and inverted surfaces of the channel gated with G2 remain unchanged. However, it indeed affects the threshold voltage as G1 serves as the driving gate. As a result, a parallel shift toward the positive direction of the threshold voltage (y-axis) is observed in Fig. 5(a). Furthermore, the associated
threshold voltages with negative charges contained in the gate oxide of G1 in mode II at the onsets of accumulation and inversion of the channel gated with G2, i.e.,V (Q)th1(dri),acc2
andV (Q)th1(dri),inv2, respectively, can be expressed as Vth1(dri),acc2(con)(Q) = Vth1(dri),acc2(con)− qQ Cox1, (12) Vth1(dri),inv2(con)(Q) = Vth1(dri),inv2(con)− qQ Cox1. (13) Fig. 5(b) shows the memory window operated in the region between points A and B shown in Fig. 5(a), which has no dependence on the gate bias of the control gate owing to
Fig. 5. (a)Vth(dri)versusVG(con)characteristics and (b) memory window versusVG(con)read in mode II with or without extra charges incorporated.
Fig. 6. Stereo view of the n-type IDG poly-Si NW SONOS device character-ized in this paper. ONO and oxide are used as the gate dielectrics of the first and second gates, respectively.
the upward parallel shift with incorporation of electrons. The memory window is
ΔVth= − qQ Cox1
(14) which is proportional to the amount of charges incorporated.
III. EXPERIMENTALRESULTS ANDDISCUSSION We employ a novel scheme that was previously developed [18] to explore the characteristics of the IDG SONOS devices and verify the theoretical model derived in the previous section. The schematic of the investigated structure and the cross-sectional transmission electron microscopic (TEM) image of a fabricated device are shown in Fig. 6. As shown in the figure,
Fig. 7. Measured transfer characteristics of (dotted lines) the programmed and (solid lines) erased states in (a) mode I and (b) mode II.
the poly-Si NW channels are horizontally sandwiched by two independent gates denoted as the first and second gates. Basi-cally, the structure and its fabrication flow are the same as those described in our previous work [16], except the replacement of the gate oxide of the first gate by an ONO (4 nm/7 nm/7 nm) stack. Thicknesses of the NW Si channel and the gate oxide of the second gate are 10 and 12 nm, respectively. In the following discussion, for simplicity, the first gate and its gate bias are denoted as the ONO gate andVG−ONO, respectively,
whereas the second gate and its gate bias are the oxide gate andVG−O, respectively. The device is programmed and erased
using Fowler–Nordheim tunneling by applying a high gate bias to the ONO gate while the oxide gate, source, and drain are grounded. As aforementioned, due to the flexibility offered by the IDG configuration, two read modes depending on the choice of the driving gate are feasible. TheID–VG characteristics of
the programmed and erased states measured under modes I and II are shown in Fig. 7(a) and (b), respectively. Program-ming was executed withVG−ONO= 15 V, VG−O= 0 V, and
t = 5 ms, and erasing was executed with VG−ONO= −12 V,
VG−O= 0 V, and t = 20 ms. The memory window is defined
as the Vth difference between the erased and programmed
states. Fig. 8 shows the results of the memory window for the two read modes extracted from the data shown in Fig. 7(a) and (b). Fig. 9 shows the simplified 2-D schematic SONOS
Fig. 8. Memory window’s read in modes I and II. The dash and solid lines refer to calculated results for modes I and II, respectively, and the circle and square symbols are the extracted results from the transfer characteristics shown in Fig. 7(a) and (b), respectively.
Fig. 9. Two-dimensional schematic structure of the n-type IDG poly-Si NW SONOS device, including detailed device parameters applied in the calculation.
structure with certain amount of electrons contained in the nitride layer. Detailed device parameters for the analysis are also included. In the figure,Neff is the effective channel
dop-ing concentration resultdop-ing from the grain-boundary trappdop-ing centers in the poly-Si film [22] and is estimated to be about 5× 1017cm−3[15].The difference of the present structure from that shown in Fig. 3 is the replacement of the gate oxide of G1 by the ONO stack; thus, the analytical form of the memory window given in (10) and (14) for modes I and II, respectively, can be applied if a modification in the oxide capacitance of G1 is made. The revised form, which is denoted as effectiveCox1,
is expressed as
Cox1(eff)= ε0εox
toxt+εoxεN × tN+ toxb
(15)
where toxt,tN, andtoxbare the thicknesses of the tunneling
oxide, nitride, and blocking oxide, respectively, andεN is the
Fig. 10. (a) Proposed Flash structure consisted of a series string of IDG SONOS cell devices and a common control gate. (b) Previous structure con-sisted of a series string of IDG SONOS cell devices. Each cell has its own control gate.
electrons in the nitride layer shown in Fig. 9 is taken into account, (14) can be modified into the following form [24]:
ΔVth = qQtot tBox ε0εox+ tN− xmean ε0εN (16) Qtot = tN 0 ρ dx (17) xmean= 1 Qtot tN 0 ρx dx (18)
where Qtot, xmean, tbox, tN, and ρ are the total amount of
trapped electrons, trapped electrons’ mean vertical position in the nitride, thickness of the blocking oxide, thickness of the nitride, and charge density of trapped electrons, respectively. By substituting the device parameters shown in Fig. 9 to the above equations, the individual memory windows in modes I and II can be calculated, and theoretical results are shown and compared with the experimental data in Fig. 8. According to the work of Lue et al. [24], most of the trapped electrons in the nitride layer distribute close to the middle of nitride. Therefore,
xmean and Qtot used in the above calculation are set to be
3.5 nm and 5× 1012 cm−2, respectively. As shown in Fig. 8, the calculated results well describe the measured memory windows extracted from the ID–VG characteristics shown in
Fig. 7(a) and (b).
a structure also adopt an ONO gate for charge storage and an oxide gate underneath the channel. During read operation, the oxide gates of the cells, except for the one to be accessed, are applied with a bias Vread−pass in order to reduce the parasitic
series resistance. Such scheme can eliminate the necessity of applying a high bias to the ONO gates of the cells neighboring the accessed cell. As a result, the read–pass disturb can be effectively suppressed. One major issue associated with such a structure is the alignment of the top ONO gate to the bottom oxide gate in the cell devices, making fabrication complicated. Such a constraint can be relieved with the proposed scheme shown in Fig. 10(a), in which the SONOS cells in the series string share a common bottom oxide gate. During read opera-tion, the common bottom oxide gate serves as the control gate and is applied with Vread−pass, whereas the top ONO gate for
the cell to be accessed is applied withVread. The top ONO gates
of the neighboring cells are either floating or with a low voltage. Such a scheme is feasible because, based on the above analysis, the memory window is independent ofVread−passapplied to the
bottom oxide gate. With the present scheme, not only the merit of the previous structure shown in Fig. 10(b) in eliminating the read–pass disturb can be retained but also the fabrication can be greatly simplified since the aforementioned demand on the precise alignment of the top and bottom gates can be lifted. Additional advantages of the proposed structure include the following: 1) Similar to the conventional DG structure [19]–[25], the common bottom gate provides electrostatically enhanced short-channel effect control, which is helpful for device scaling. 2) The P/E efficiency can be improved as an appropriate bias is applied to the bottom control gate, as has been demonstrated in one of our previous studies [18]. 3) Although not clearly depicted in Fig. 10(a), it is possible to eliminate the n+ source/drain (S/D) regions by adopting
the junction-free (JF) scheme that has been recently proposed [26], [27]. Such a scheme skips the S/D implant steps and utilizes the fringe field from the neighboring gates to induce an inversion layer in the junctionless S/D areas and reduce the series resistance therein. As the present IDG configuration adopts the JF scheme, fabrication can be further simplified. Moreover, the series resistance is expected to be lower than the previous JF versions [26], [27] as an appropriate bias is applied to the common gate. 4) Fabrication involves mainly mature poly-Si preparation techniques and has low thermal budget, making it suitable for monolithic 3-D integration. In addition, the concept is not restricted to the planar scheme shown in Fig. 10(a). If some modifications are made, it can be also applied to 3-D Flash structures with vertical-channel cell devices, such as the BICs [12], [13].
IV. CONCLUSION
The operation mechanisms of IDG poly-Si NW SONOS devices are characterized. The theoretical analysis indicates that the memory window is larger and independent of the bias applied to the control gate as the gate of the charge storage side is used as the driving gate for sensing Vth. Such predictions
are confirmed with the experimental results. Based on the above finding, a novel scheme containing a series string of JF SONOS cell devices with a common control gate is proposed for monolithic 3-D Flash application. Such a scheme can retain the inherent merits associated with the IDG configuration, such as good control over the short-channel effects, improved P/E efficiency, and suppressed read disturb. Furthermore, the implementation of the common control gate and JF features can greatly simplify the device fabrication and thus advancing the feasibility of poly-Si NW devices for future 3-D nonvolatile memory manufacturing.
ACKNOWLEDGMENT
The authors would like to thank the National Nano Device Laboratories (NDL) and Nano Facility Center of National Chiao Tung university for assistance in device fabrication.
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Horng-Chih Lin (S’91–M’95–SM’01) was born in
I-Lan, Taiwan, on August 1, 1967. He received the B.S. degree from National Central University, Chung-Li, Taiwan, in 1989 and the Ph.D. degree from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1994.
From 1994 to 2004, he was with the National Nano Device Laboratories, where he was engaged in the research projects of nanoscale device technol-ogy development. He joined the faculty of NCTU, Taiwan, in 2004, where he has been a Professor with the Department of Electronics Engineering and the Institute of Electronics since 2007. Currently he is also a joint-appointment researcher with the National Nano Device Laboratories. He has authored or coauthored more than 200 technical papers published in international journals and conferences related to his areas of interest. His current research interests include thin-film transistor fabrication and characterization, reliability of complementary metal–oxide–semiconductor devices, and nanowire device technology.
Dr. Lin served on the Program Committee of the International Reliability Physics Symposium (2001 and 2002) and the International Conference on Solid State Devices and Materials (2005–2008).
Wei-Chen Chen was in born in Taoyuan, Taiwan,
in 1984. He received the B.S. degree in electro-physics in 2006 from National Chiao Tung Univer-sity, Hsinchu, Taiwan, where he is currently working toward the Ph.D. degree in the Department of Elec-tronics Engineering and the Institute of ElecElec-tronics.
His current research interests include fabrication and characterization of nanowire transistors and germanium-based devices.
Dr. Huang was the recipient of the Semiconductor International’s Technology Achievement Award for his invention and demonstration of the fully overlapped lightly doped drain metal–oxide–semiconductor transistors.
