Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 1, MARCH 2006 95

Impact of STI on the Reliability of Narrow-Width

pMOSFETs With Advanced ALD N/O Gate Stack

Steve S. Chung, Fellow, IEEE, Chang-Hua Yeh, Hsin-Jung Feng, Chao-Sung Lai, Jiuun-Jer Yang,

Chi-Chun Chen, Ying Jin, Shih-Chang Chen, Member, IEEE, and Mong-Song Liang, Fellow, IEEE

Abstract—For the first time, a shallow trench isolation

(STI)-induced enhanced degradation in pMOSFETs for ultrathin

gate oxide devices has been observed. The I

degradation is

enhanced as a reduction in the gate width and the hot carrier

(HC) or negative bias temperature instability (NBTI) effect.

Ex-tensive studies have been compared for atomic layer deposition

(ALD)-grown and plasma-treated oxide pMOSFETs. Different

temperature dependences were observed. At room temperature,

hole trap is dominant for the device degradation, in which

hole-trap-induced V

is significant, whereas at high temperature under

NBTI stress, interface trap becomes more significant, which

dom-inates the device I

degradation. In addition, the V

rolloff can

be modeled as a width narrowing effect specifically for STI. More

importantly, the NBTI-induced interface/oxide traps are strongly

related to the hydrogen and N

content in the gate oxide formation

process. The interface trap generation is suppressed efficiently

using the ALD-grown gate oxide. These results provide a valuable

guideline for the understanding of the HC and NBTI reliabilities

in an advanced ALD-grown gate oxide processes/devices.

Index Terms—Atomic layer deposition (ALD), gate stack,

narrow-width effect, negative bias temperature instability (NBTI),

shallow trench isolation (STI).

I. I

I

N PREVIOUS studies [1], for the previous-generation

quarter-micrometer CMOS technology, in which the gate

oxide is larger than 30 Å, narrow-width shallow trench isolation

(STI) exhibits severe degradation after hot-carrier (HC) stress

with a reducing gate width. The degradation of pMOSFETs

was attributed to an off-state leakage current increase [2] and

channel-length shortening [3] because electron trapping exists

for a thicker gate oxide. In comparison, for a very thin gate

ox-ide (< 20 Å), the hole trap is the dominant mechanism instead,

which leads to an off-state current reduction which is good.

However, there are several other issues that become significant

with device scaling. According to experimental observations,

devices with the STI structure exhibit different degradation

mechanisms at various temperatures. Generally, the negative

bias temperature instability (NBTI) in pMOSFETs is attributed

to the generation of interface traps and oxide trap charges [4].

Manuscript received October 16, 2004; revised July 6, 2005. This work was supported by a Taiwan Semiconductor Manufacturing Company (TSMC) joint development project under Contract 91C209 and in part by the National Science Council under Grant NSC92-2215-E009-058.

S. S. Chung and H.-J. Feng are with the Department of Electronic Engineer-ing, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.

C.-H. Yeh, C.-S. Lai, and J.-J. Yang are with the Department of Electronic Engineering, Chang-Gung University, Taoyuan 333, Taiwan, R.O.C.

C.-C. Chen, Y. Jin, S.-C. Chen, and M.-S. Liang are with Taiwan Semicon-ductor Manufacturing Company, Ltd., Hsinchu 300, Taiwan, R.O.C.

Digital Object Identifier 10.1109/TDMR.2006.871415

So far, none has been reported on the enhanced degradation

of narrow-width devices in relation to the NBTI effect,

espe-cially for a very high-end atomic layer deposition (ALD) gate

oxide stack.

In this paper, the aforementioned enhanced degradation at

both room temperature (HC effect) and high-temperature

stress-ing (NBTI) has been demonstrated on an advanced ultrathin

ALD gate nitride/oxide (N/O) stack. Furthermore, to get more

insight into the detailed degradation mechanism, a unique

neu-tralization technique on the oxide charges has been provided,

which allows us to identify the generation of interface traps and

oxide trap charges. Various experiments have been conducted

to confirm that ALD is effective in suppressing the enhanced

degradation effect.

II. D

P

The devices were prepared based on the 90-nm foundry

technology. The ALD N/O gate stack was prepared by an

advanced remote plasma-enhanced ALD (RPEALD) technique

with less H-precursor and N

content [5]. The control sample

with a heavily plasma-nitrided oxide served as a reference. The

ALD and plasma samples have an equivalent oxide thickness

(EOT) of 15.4 and 15.5 Å, respectively. The devices with a

masked gate length of 0.15 µm and various gate widths were

used for the reliability measurement.

III. R

D

A. Narrow-Width Effect at Room Temperature

Fig. 1 shows the measured device drain–current degradation

after the HC stress for pMOSFETs, including I

, I

,

and V

= V

stress conditions, respectively. It is generally

known that the largest degradation in the ultrathin gate oxide

thickness device occurs at V

= V

stress as expected. Fig. 2

shows one set of measured drain–current at V

=

−2 V for

a device with a width W = 2 µm before and after V

=

V

=

−2 V stresses. The fresh device curve is represented

by curve (1), whereas a decrease of the current is represented

by curve (2) for the device after the stress. The decrease of

the drain–current for devices after the stress can be regarded

as an increase of the threshold voltage with the generation of

interface trap N

and hole trap Q

. The steps in Fig. 3 will help

us clarify the generation of either N

or Q

. First, for a fresh

device, the drain–current at V

=

−2 V (curve (1) in Fig. 2)

and the gate-induced drain leakage (GIDL) current (curve (1)

96 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 1, MARCH 2006

Fig. 1. Drain–current degradation of the thin oxide ALD device under

IG,max, IB,max, and VG= VDstresses, respectively.

Fig. 2. Drain–current at VG=−2 V for the device before stress [curve (1)],

after stress [curve (2)], and after neutralization is completed [curve (3)]. The stress condition is given at VG= VD=−2 V. Note that the ∆IDcaused by Qotis larger than that due to Nit.

in Fig. 3) are measured. Then, both currents are measured after

the device was stressed for 1000 s under V

= V

=

−2 V.

Here, we see a clear shift of the GIDL curve to the right, i.e.,

curve (2). This shift corresponds to a positive threshold voltage

shift V

, caused by Q

, which is an indication of the positive

oxide trap. Consequently, a neutralization process is performed

by injecting electrons from the substrate into the gate oxide as

shown in two steps [6] and with bias conditions given in the

figure to fill those positive traps. Here, we see that a shift of

the GIDL current, curve (2), will be moved back to curve (3)

and then aligned with the fresh one, curve (1). In Fig. 2, the

difference of I

between curves (1) and (3) shows the effect of

the generated N

, whereas the difference between curves (2)

and (3) gives the effect of the generated Q

. From the

afore-mentioned GIDL measurement technique, we can accurately

separate the contribution of the interface trap and oxide trap to

the drain–current degradations. In a similar manner, we can

ob-tain the same set of curves for narrower width devices, and their

comparison with a wide device is given in Fig. 4. In Fig. 3, the

Fig. 3. GIDL currents for the fresh, stressed, and after neutralized. A two-step neutralization is achieved by hot-electron injection to eliminate hole traps.

Fig. 4. Comparison of the measured drain–currents for devices with W = 0.11 and 2 µm. Note that the generated Qotis enhanced for narrow-width

devices.

contribution of oxide traps Q

to the drain–current degradation

∆I

is much larger when compared with that contributed

from the generation of interface traps ∆I

. These results

show that the HC degradation depends mostly on the oxide

traps, whereas it depends weakly on the generated interface

traps with reducing gate width. It is believed that there are only

few oxide traps in the ultrathin gate oxide device. Consequently,

a much larger generated Q

found here should mainly depend

on the high nitride density in the gate oxide. Obviously, we can

see an enhancement of the Q

with reducing channel width,

i.e., a device with W = 0.11 µm has a larger shift (18%) of

I

as compared with that with W = 2 µm (11.4%).

To further study the variation of the threshold voltage with

the device gate width, we plotted ∆V

as a function of the

channel width (solid circles) in Fig. 5, from which we can

see a large enhancement of the narrow-width effect. This is

attributed to the STI mechanical stress as reported in [3]. We

know that the STI-enhanced HC stress degradation area is

CHUNG et al.: IMPACT OF STI ON RELIABILITY OF NARROW-WIDTH pMOSFETs WITH ALD N/O GATE STACK 97

Fig. 5. Calculated threshold voltage shift as a function of width, where the comparison between two different gate oxide processes is also shown.

Fig. 6. Model to show the STI damage area, which can be used to predict the

VTshift for devices over a wide range of gate widths.

confined in the edge region of the STI such that the STI edge

ratio (i.e., the ratio of the edge region to the total gate width) of

a narrower width device is larger. In other words, the threshold

voltage shift at the STI edge as caused by the quality of the STI

or the mechanical stress is believed to be much larger than that

at the channel center, as shown in Fig. 6. Therefore, HC stress

degradation is enhanced for a reduction of the channel width

and hence induces a larger threshold voltage shift.

To predict the STI effect for the different channel-width

devices, from more than two sets of measured V

and

calculated V

(solid symbols in Fig. 5) for different widths and

from the following equation, we can calculate the V

at another

gate width. Here, the total variation of the threshold is given by

{∆V

× ∆W + ∆V

× (W − ∆W )} ×



W

= ∆V

(1)

where

∆V

threshold voltage shift in the STI edge;

∆V

threshold voltage shift in the channel center;

∆V

total threshold voltage shift in the whole channel;

∆L

length of the HC damage area;

∆W

STI edge width;

L, W

device channel length and width.

Fig. 7. Measured gated-diode currents for two different gate widths, where the first peak shift in the gated-diode currents shows the generation of more oxide traps for a narrow-width device.

In the preceding equation, the total threshold voltage shift ∆V

is a combination of ∆V

from the channel center region and

∆V

from the gate edge region. Assume ∆L and ∆W are

the same for two different gate-width devices, and from two

known values of ∆V

measured at two different gate widths,

we may calculate ∆V

and ∆V

for any gate width according

to (1) such that the total ∆V

can be calculated.

The aforementioned method has an advantage of predicting

the degradation V

for devices over a wide range of gate widths.

To further identify whether this V

is caused by the STI effect,

we measured the gated-diode currents [7] for two different

gate-width devices as shown in Fig. 7. The first peak shift to the

left is a result of width reduction because the first peak in the

gated-diode measurement is an indication of the generated Q

,

which causes the threshold voltage shift. As commonly known,

the increase of the peak currents (the difference between the

fresh and stressed ones, e.g., the peaks at V

= 1.7 V) implies

the generation of N

after the HC stress. According to the

results of the gated-diode measurement in this figure, obviously,

the increment of the gated-diode current is larger for

narrow-gate-width devices. This further shows that not only Q

was

generated but also N

was increased as a result of width

reduction. Therefore, the STI-enhanced degradation in

narrow-width devices can be further justified via this gated-diode

measurement.

To show a higher gate oxide quality of ALD, the result for

the control sample (plasma-treated device) is also shown for

comparison in Fig. 5. Note that the V

rolloff is much worse

for the plasma-treated sample. It is commonly believed to be

due to a much higher density of the nitrogen in the gate oxide,

which induces much larger degradation of oxide traps after the

HC stress.

B. Observation of Narrow-Width-Dependent NBTI Effect

To investigate the width dependence of the NBTI effect,

Fig. 8 shows the measured drain–currents for two different

gate-width devices, where the measurement step is similar to

98 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 1, MARCH 2006

Fig. 8. NBTI measurement. The drain–current for the device with W = 0.11 and 2 µm before stress, after stress, and after neutralization are completed. Note that the ∆IDcaused by Nitis dominant.

Fig. 9. (a) Threshold voltage shift caused by the NBTI-induced interface traps. (b) IDdegradation caused by the NBTI-induced interface traps.

that given in Fig. 2. As a result of the recovery of V

after

turning off the NBTI stress, it was found by comparing the data

with the dashed lines and the open circles that Q

becomes

smaller. Therefore, N

will become the dominant factor of the

drain–current degradation as well as the V

shift. Here, the

drain–current degradation ∆I

becomes much larger from

the comparison of the dashed lines and solid circles. Q

is

nearly negligible here. It is attributed to the near interface oxide

Fig. 10. Drain–current before and after NBTI stress and the comparison for two different gate oxide processes. ALD has much better reliability.

Fig. 11. Illustration of the width narrowing model, in which the shaded area is stillOFFwhen the channel begins to conduct.

traps, which are recovered in a very thin gate oxide. Therefore,

we plot in Fig. 9(a) and (b) the enhancement of the V

rolloff

and I

due to the generated N

only. In other words, the

observed Q

after NBTI becomes weaker compared with the

generated N

at an elevated temperature, and the interface traps

become the dominant mechanism for the I

degradation. The

narrow-width-dependent NBTI degradations for two different

gate oxide processes are shown in Fig. 10.

C. Further Insight of the Trap Generation and the Model

To reasonably explain the observed enhancement effect

caused by the STI, for the first time, a model called width

narrowing, which is different from that in [3], is proposed

in Fig. 11. In a comparison between a wide- and a

narrow-width device, after the HC stress, the STI corner exhibits an

area where the channel beneath this region has a larger local

threshold voltage due to the positive hole trap (Q

)-induced

damage, in which a larger local threshold voltage is observed at

the gate edge. If the local threshold voltage shift is sufficiently

high, it results in an effective width, W

− ∆W , such that ∆V

is enhanced for a narrower width device [Figs. 5 and 9(a)].

Another most important implication from Fig. 8 is showing that

the NBTI effect will generate more interface traps N

for a

narrower device as a result of the STI effect. By combining

the two preceding factors, the result and physical mechanism

CHUNG et al.: IMPACT OF STI ON RELIABILITY OF NARROW-WIDTH pMOSFETs WITH ALD N/O GATE STACK 99

Fig. 12. Comparison of the hydrogen release between ALD and plasma samples. Note that ALD has lower H2 content and hence a slower H2

re-moval rate.

in an ultrathin gate oxide device are quite different from the

last-generation quarter-micrometer generation devices in that

the degradation comes from the channel shortening [3] or

elec-tron traps.

The mechanisms related to an N

increase and a Q

re-laxation after NBTI are more interesting and can be drawn

as follows.

1) Both N

and Q

are caused by the hydrogen release

from the surface toward the polygate [8], [9]. The

gen-eration of N

is smaller for ALD because ALD has less

hydrogen content (see the comparison in Fig. 12) and

hence a slower release rate of H

.

2) The hole trap generation can be measured by the

low-voltage stress-induced leakage current (LV-SILC) method

[10] with results given in Fig. 13, where we see that

ALD exhibits smaller SILC and hence smaller hole traps,

smaller SILC, and V

(Fig. 5).

3) Resulting from the recovery of V

or Q

(Fig. 10,

especially under NBTI), the N

in the plasma sample is

aggravated due to a heavier N

content at the interface as

hole traps are moved back to the substrate.

We therefore have the following conclusions.

1) NBTI and HCI device degradations are enhanced with

reducing gate width, which show the STI effect.

2) Under NBTI stress, ALD exhibits much less N

gener-ation and hence much better reliability compared with

plasma film.

3) Gate oxide formation process with ALD is proved to be

more reliable than that of the plasma film in terms of

the HC stress effect (at room temperature) and NBTI

reliabilities (at high temperature).

IV. C

The origins of enhanced drain–current degradation and its

dependence on the narrow-width effect in pMOSFETs have

been extensively studied. New results on the HC- and

NBTI-stress-induced device degradations in scaled STI pMOSFETs

have been reported. The separation of the degradation type,

including interface trap and oxide trap via a so-called

neutral-ization step and GIDL measurement, is proposed to verify the

generated oxide trap and interface trap.

For the evaluation of the HC and NBTI reliabilities, different

temperature dependences are observed. At room temperature,

from the HC test, the hole trap is dominant for the device

V

shift, whereas the interface trap is more significant and

Fig. 13. LV-SILC measurement at low VG, which shows that much more Nit’s are generated near the conduction band for plasma-treated sample.

responsible for the I

degradation after NBTI stress at high

temperature. Moreover, the V

rolloff can be well explained by

a width narrowing effect physically, and a quantitative model is

further proposed. Results have clearly shown that the generated

interface/oxide traps are strongly related to the hydrogen and

N

content in the gate oxide formation process. Therefore, the

results provide us a useful guideline for understanding the

HC-and NBTI-related reliabilities in an advanced gate N/O stack

60 nm and beyond CMOS processes/devices.

R

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100 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 1, MARCH 2006

Steve S. Chung (SM’83–M’85–SM’95–F’06) received the Ph.D. degree in electrical engineer-ing from the University of Illinois at Urbana-Champaign in 1985. His Ph.D. thesis advisor was the world-famous scholar and CMOS coinventor Prof. C. T. Sah.

In 2001, he was a Research Visiting Scholar at Stanford University, Stanford, CA. Between 2004 and 2005, he was the first Department Head of the EECS Honors Program to promote a new under-graduate program for academic excellence at the National Chiao-Tung University (NCTU), Hsinchu, Taiwan, R.O.C., where he has served since 1987. He is currently a Chair Professor at NCTU and also a UMC Research Chair Professor. He was also a Consultant to Taiwan Semiconductor Manufacturing Company (TSMC) and UMC on de-veloping CMOS and Flash memory technologies. He has published more than 140 journal and conference papers, 1 textbook, and holds more than 18 patents in CMOS and Flash memory. His current research areas include CMOS device technology, Flash memory technology, reliability characteriza-tion and modeling, etc.

Dr. Chung is an elected AdCom Member, a Distinguished Lecturer, a Regions/Chapters Vice-Chair of the EDS, and the Editor of IEEE ELECTRON

DEVICE LETTERS (EDL). He has served on the committees of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, IPFA, etc. For the first time in Taiwan history, at the 50th anniversary of the IEEE, the ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the Chapter Chair. He was awarded the Outstanding Research Award for excellence in research three times, as well as ranking the Top-PI in 2003, from the National Science Council, Taiwan, R.O.C. He was also granted both the Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan.

Chang-Hua Yeh received the B.S. and M.S. degrees

in electronic engineering from the Chung-Gung University, Taoyuan, Taiwan, R.O.C., in 2002 and 2004, respectively. His thesis was codirected by Prof. S. S. Chung of the National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.

He is currently with the Research and Devel-opment Division, Nanya Technology Corporation, Taoyuan, Taiwan, R.O.C., focusing on the develop-ment of DRAM. His interests are in the areas of MOSFET device reliability and characterization.

Hsin-Jung Feng received the B.Sc. degree in electrical engineering from the

National Central University, Taoyuan, Taiwan, R.O.C., in 2001 and the M.Sc. degree in electronic engineering from the National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2004. His thesis was on the development of a charge pumping technique for ultrathin gate oxide CMOS devices.

Chao-Sung Lai was born in I-Lan, Taiwan, R.O.C.,

on May 20, 1969. He received the B.Sc. and Ph.D. degrees from the National Chiao-Tung Uni-versity, Hsinchu, Taiwan, R.O.C., in 1991 and 1996, respectively.

In 1996, he joined the National Nano Device Laboratory, Hsinchu, Taiwan, R.O.C., where he was engaged in the research of silicon-on-insulator de-vices. In 1997, he was an Assistant Professor at the Chang Gung University and Tao-Yuan, Taiwan, R.O.C., where he was engaged in the research of the characterization and reliability of deep submicron MOSFETs, nitrided thin gate oxides, shallow trench isolation, and the modeling of the dielectrics’ reliability. Since 1997, he has been a Consultant for the 0.18-µm Logic Team at the Nanya Technology Corporation, Taoyuan, Taiwan, R.O.C. In 2001, he was an Associate Professor. In 2001, he was a Visiting Scholar in Prof. C. Hu’s group at the University of California-Berkeley.

Dr. Lai won the Lam Award in 1997.

Jiuun-Jer Yang received the B.Sc. degree from the

National Cheng-Kung University, Tainan, Taiwan, R.O.C., in 1989, and the M.Sc. and Ph.D. degree from the National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1991 and 1995, respectively, all in electrical engineering.

From 1995 to 1997, he was with the Technology Development Center, Winbond Electronics Corpo-ration, Hsinchu, Taiwan, R.O.C., working on tech-nology computer-aided design, device design, and reliability engineering. From 1997 to 2000, he was with the Worldwide Semiconductor Manufacturing Corporation, Hsinchu, Taiwan, R.O.C., where he worked first at the Technology Development Center, and then switched to the Fab working on device characterization, yield enhance-ment, and process integration. From 2000 to 2003, he was an Assistant Profes-sor at the Department of Electronic Engineering and Institute of Semiconductor Technology, Chang-Gung University, Taiwan, R.O.C. He is currently with the Semiconductor Manufacturing International Corporation, Beijing, China, in charge of northern-site quality and reliability engineering division. His research interests include device integration, process/device modeling and simulation, and reliability study of advanced technologies.

Chi-Chun Chen received the B.S., M.S., and Ph.D.

degrees in electronics engineering from the National Chiao-Tung University (NCTU), Taiwan, R.O.C., in 1996, 1997, and 2000, respectively.

At NCTU, his research was focused on the process-related oxide reliability of ultrathin gate ox-ides. In 2000, he joined the Taiwan Semiconduc-tor Manufacturing Company, Ltd., Hsinchu, Taiwan, R.O.C., where he was responsible for the HDPCVD process for STI and ILD gapfill, thin gate oxide process, and Cu CMP process for 0.13-µm logic process development in the 300-mm pilot line. From 2001 to 2004, he worked on the research and development of advanced gate stack process. He is currently the Project Manager of the Advanced Module Technology Division of the Research and Development organization. He is responsible for gate stack module development, including wet clean and surface preparation, thermal process, oxynitride/poly gate stack process, and related metrology technologies. He has authored or coauthored about 40 technical papers in the advanced semiconductor process area, especially in gate dielectrics-related process. He also holds more than ten patents in semiconductor manufacturing technologies.

Ying Jin was born in Beijing, China. He received the

Ph.D. degree in semiconductor physics from Peking University, Beijing, China.

He was a Research Fellow at the City University of Hong Kong, where he was responsible for the diffusion module of Research and Development at the Chartered Semiconductor Manufacturing Ltd., Singapore. In 2002, he joined the Taiwan Semi-conductor Manufacturing Company, Ltd., Hsinchu, Taiwan, R.O.C., where he is currently the Project Manager at the Advanced Module Technology Di-vision, responsible for advanced gate stack process, such as high-k/metal gate, for 45-nm and beyond devices.

CHUNG et al.: IMPACT OF STI ON RELIABILITY OF NARROW-WIDTH pMOSFETs WITH ALD N/O GATE STACK 101

Shih-Chang Chen (M’00) was born in Taiwan,

R.O.C. He received the B.S., M.S., and Ph.D. degrees in electrical and electronics engineering from Hosei University, Tokyo, Japan.

In 1986, he joined the VLSI Research and Devel-opment Center, Oki Electric Industry Company, Ltd., Tokyo, Japan, where he worked on gate electrode and interconnect process technologies development, em-ploying refractory metals and their silicides/nitrides for very large scale integrations. He was also in charge of the process development of high-k capaci-tor and electrode films for high-density DRAMs. Afterward, he was responsible for the process development of advanced interconnects employing copper and low-k materials until January 2000. In February 2000, he joined the Worldwide Semiconductor Manufacturing Corporation, Hsinchu, Taiwan, R.O.C., where he was responsible for all advanced process technology developments at the Advanced Process Technology Division, Technology Development Center. In July 2000, he joined the Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, R.O.C., where he is currently the Deputy Director and is responsible for the advanced front-end process at the Advanced Module Technology Division. His research interests include advanced front-end-of-the-line process development, including ultrathin gate oxide or high-k gate stacks, strained Si process, and ultrashallow junction formation for 65-nm and beyond devices.

Mong-Song Liang (F’06) received the B.S. and

M.S. degrees from the National Cheng-Kung Uni-versity, Taiwan, R.O.C., in 1975 and 1977, respec-tively, and the Ph.D. degree from the University of California (UC), Berkeley, in 1983, all in electrical engineering and computer sciences.

At UC Berkeley, his research was on the scal-ing of ultrathin gate dielectrics and on device re-liability physics. In 1983, he joined the Advanced Micro Devices, Sunnyvale, CA, where he worked on nonvolatile memory technologies (EEPROM and EPROM). From 1988 to 1992, he was with the Mosel Electronics Corporation, Sunnyvale, CA, where he worked on SRAM technology development. In 1992, he jointed the Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, R.O.C. He worked on DRAM and embedded memory technology (Emb-DRAM, Emb-SRAM, and Emb-Flash) development. He was the Director of the Memory Division of the Research and Development organization until 1998. He is currently the Director of the Advanced Module Technology Division of the Research and Development organization. He is responsible for all advanced modules development, including etch, thin film, diffusion, CMP, and Cu/low-k interconnect.