IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 5, MAY 2006 399
Two-Frequency
C
–
V
Correction Using
Five-Element Circuit Model for High-
k
Gate Dielectric and Ultrathin Oxide
W. H. Wu, B. Y. Tsui, Senior Member, IEEE, Y. P. Huang, F. C. Hsieh, M. C. Chen,
Y. T. Hou, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang, Fellow, IEEE
Abstract—A new circuit model of five elements has been
pro-posed for the two-frequency capacitance–voltage (C–V ) correc-tion of high-k gate dielectric and ultrathin oxide. This five-element circuit model considered the static and dynamic dielectric losses in a lossy MOS capacitor, the parasitic well/substrate resistance, and the series inductance in the cables and probing system. Each of the circuit elements could be easily extracted from the two-frequency
C–V and static current–voltage (I–V ) measurements if some
criteria are well satisfied. In addition, this model can also be transformed into another two four-element circuit models to sim-plify the analysis and calculations, depending on the gate leakage current.
Index Terms—High-k dielectric, MOS capacitor, two-frequency
capacitance–voltage (C–V ) correction, ultrathin oxide.
I. INTRODUCTION
W
ITH the rapid progress of very large scale integra-tion (VLSI) technologies, the gate dielectric thickness continues to scale down to ensure the device performance in great advance. The gate dielectric capacitance of advanced devices is of great importance for obtaining the equivalent oxide thickness (EOT), inversion layer charge, and interface state density. However, the tunneling current through ultrathin gate oxides may lead to difficulties in performing the quasi-static and typical 100-kHz capacitance–voltage characteriza-tions. Although the problem of severe capacitance drop under large tunneling current can be improved by measuring at higher frequencies (≥ 1 MHz), the influences of parasitic components on the measured capacitance must be taken into account at such high frequencies.The series resistance Rs arising from the well/substrate
and the contact resistance was first added to the parallel cir-cuit model(Cp−G), and a two-frequency capacitance–voltage
(C–V ) correction method was proposed to extract the accurate dielectric capacitance from this three-element circuit model [1], [2]. In practice, the validity of this correction method seems to depend upon the two frequencies adopted and the device area.
Manuscript received February 13, 2006; revised February 27, 2006. This work was supported by the National Science Council, Taiwan, R.O.C., under Contract 93-2815-C-009-019-E. The review of this letter was arranged by Editor K. De Meyer.
W. H. Wu, B. Y. Tsui, Y. P. Huang, F. C. Hsieh, and M. C. Chen are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: bytsui@mail.nctu.edu.tw).
Y. T. Hou, Y. Jin, H. J. Tao, S. C. Chen, and M. S. Liang are with the Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan, R.O.C.
Digital Object Identifier 10.1109/LED.2006.873423
The applicability limits of this two-frequencyC–V correction method had been further examined in terms of frequency and device area selection guidelines [3]. Later, some researchers recommended that the dielectric energy absorption and other parasitic components should be considered as well. An im-proved two-frequency method of capacitance measurement us-ing a four-element circuit model was proposed for the SrTiO3 high dielectric constant (high-k) dielectrics [4]. The shunt resistance was replaced by the loss tangent tan δ (or called the dissipation factor) due to the dynamic dielectric loss of high-k dielectrics, and series inductance was added due to ca-bles and the probing system. In addition, a newC–V correction method using another four-element circuit model to extract the EOT of ultrathin gate dielectrics with high gate leakage current was also proposed [5]. The shunt resistance was to simulate the static dielectric loss from the gate leakage current, and the parasitic capacitance in parallel withRswas added due to the
device structure, probe contact arrangement, and stray cable capacitance. In this work, a new five-element circuit model has been proposed to consider both the dielectric imperfections and the parasitic components, and this circuit model could also be transformed into another two four-element circuit models to simplify the analysis and calculations, depending on the gate leakage current.
II. GENERALCIRCUITMODEL OFFIVEELEMENTS
Fig. 1(a) shows the two-element parallel circuit model used for a typical C–V characterization in an impedance meter. However, this simple parallel circuit model may not be enough to describe the behavior of the small-signal frequency response of ultrathin oxides and high-k gate dielectrics in various situa-tions. Therefore, a more general circuit model of five elements as shown in Fig. 1(b) is proposed to be employed in the two-frequency C–V correction. In this five-element circuit model,
C0is the ideal dielectric capacitance,Rpis the shunt resistance
due to gate leakage current, tan δ is the loss tangent due to dielectric energy absorption, Rs is the series resistance due
to well/substrate and contact resistance, and Ls is the series
inductance due to extension cables and the probing system. It seems to have two types of dielectric losses in a lossy MOS capacitor, namely, 1) the static dielectric loss due to the actual flow of charge carriers, and 2) the dynamic dielectric loss due to the local movements of atoms or molecules in an alternating electric field.
400 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 5, MAY 2006
Fig. 1. Small-signal equivalent circuit models of MOS capacitors. (a) Simple parallel circuit model. (b) New five-element circuit model. (c) Four-element circuit model for low leakage high-k dielectrics. (d) Four-element circuit model for ultrathin oxides and leaky high-k dielectrics.
Equating the real and imaginary parts of the total impedance in Fig. 1(a) and (b) results in
Real: G G2+ ω2Cp2 = Rs+ Rp(1 + tan2δ + ωC0Rptan δ) 1 + (ωC0Rp+ tan δ)2 (1) Imaginary: Cp G2+ ω2Cp2 = −Ls+ C0Rp2 1 + (ωC0Rp+ tan δ)2. (2)
The above two equations could be simplified for easy alge-braic operations if the criteria tan2δ 1 (ωC0Rp)2 are
satisfied, i.e., Real: G G2+ ω2Cp2 = Rs+ tan δ ωC0 + 1 ω2C2 0Rp (3) Imaginary: Cp G2+ ω2Cp2 = −Ls+ 1 ω2C0. (4)
IfRpis defined asVg/Ig from the staticIg−Vg measurement
sinceRp Rsis valid in most cases, the above criteria could
be rearranged as tan δ < 0.1 and Jg< 0.01 A/cm2 for quick
verification. In addition,C0and the other three circuit elements could be easily solved from (3) and (4) with the known Rp
by measuring Cp and G in parallel mode at two different frequencies, i.e., C0= ω2 2− ω12 G2 1+ ω12Cp12 G2 2+ ω22Cp22 ω2 1ω22 Cp1G22+ ω22Cp22 − Cp2G21+ ω12Cp12 . (5) When it comes to the high-k dielectrics with low gate leakage current,Rpcould almost be regarded as infinity (open circuit),
and tan δ in series with C0 could be transformed into the equivalent one in parallel. This four-element circuit model, as shown in Fig. 1(c), is the one proposed by Lue et al. for SrTiO3 high-k dielectrics [4]. Equations (3) and (4) can be applied to their model if the1/ω2C02Rpterm in (3) is deleted,
and the same results were obtained from Lue et al.’s and our equations.
When it comes to ultrathin oxides or leaky high-k dielectrics, the static dielectric loss due to tunneling leakage current is much more significant than the dynamic one. This is the four-element circuit model for leaky MOS capacitors as shown in Fig. 1(d) [6]. Equations (3) and (4) can also be applied to this model if thetan δ/ωC0term in (3) is deleted. Sometimes, if the dielectric is too leaky, the criteria 1 (ωC0Rp)2 andRp
Rs may not be valid. The two equations from just equating
the total impedance in Fig. 1(a) and (d) without any reduction should be employed to obtainC0Rpfirst in similar ways above
and then use this C0Rp to obtain C0 and the other circuit elements, i.e., C0Rp= Cp1 G2 2+ ω22Cp22 − Cp2G21+ ω21Cp12 G1G22+ ω22Cp22 − G2G21+ ω12Cp12 . (6)
III. RESULTS ANDDISCUSSION
The test structures used in this study are simple MOS capac-itors with two-terminal top gate and wafer backside contacts, and all the C–V measurements were performed using the Agilent 4284A precision LCR meter in parallel mode. Figs. 2 and 3 show the measured and two-frequency-corrected C–V curves of the TiN/ALD HfO2/SiO2/p-Si MOS capacitors with gate area= 10 000 and 400 µm2, respectively. The details of the fabrication process could be found elsewhere [7], and the EOT was extracted as 1.38 nm using the C–V simulation program that has taken the quantum effect into account [8]. It has been demonstrated that the frequency dispersion of the clamped and amplified C–V curves at high frequencies (> 500 kHz) can be effectively eliminated when considering the influences of the parasitic componentsRsandLsand that the value of each circuit element at a specific applied gate voltage could be independently obtained from (3) and (4) for the given device as listed in the figures. Note that tan δ is
∼ 0.3%–0.35% and is independent of the gate area, and this
dynamic dielectric loss might be a materials issue. It has been reported that tan δ is ∼ 3% in BaSrTiO3 high-k dielectrics and can be improved to 1% with the appropriate doping of Al2O3 [9]. In addition, the parasitic components Rs andLs
exhibit significant area dependences (Rs∼ 1/area1/2[10] and
Ls∼ 1/area) as shown in the two insets. These findings could
be explained by considering the electric flow lines from the small top gate electrode on a flat surface of a semi-infinite substrate to the wafer backside contact (similar to measuring the spreading resistance) and the phase compensation problems between the measurement signal voltage and signal current when the connection scheme of probing through the chuck with switch matrix (Agilent E5250A) is employed in the probing system.
WU et al.: TWO-FREQUENCY C–V CORRECTION USING A FIVE-ELEMENT CIRCUIT MODEL 401
Fig. 2. Measured and two-frequency-correctedC–V curves of the TiN/ALD HfO2/SiO2/p-Si MOS capacitor with gate area = 10 000 µm2. The fre-quency dispersion of clamped C–V curves could be observed at high frequencies (> 500 kHz).
Fig. 3. Measured and two-frequency-correctedC–V curves of the TiN/ALD HfO2/SiO2/p-Si MOS capacitor with gate area = 400 µm2. The frequency dispersion of amplifiedC–V curves could be observed at high frequencies (> 500 kHz).
Fig. 4 shows the measured, two-frequency-corrected, and theoretical C–V curves of the ultrathin oxynitride with EOT= 1.65 nm. Although the severe capacitance drop could not be completely recovered, adopting two high frequencies in the two-frequencyC–V correction using (6) could obtain the corrected C–V curve more close to the theoretical one. Then, use theC–V simulation program considering both poly-depletion and quantum effects [8] to perform the curve fitting at the overlapping transition region. This may provide a simple and practical approach to extract the EOT of ultrathin oxides. In addition, radio frequency (RF)C–V measurement and short channel devices are highly suggested to be accompanied with the above method [11], [12].
IV. CONCLUSION
The two-frequency C–V correction using adequate circuit models can effectively eliminate the frequency dispersion of clamped and amplified C–V curves for low leakage high-k dielectrics, and thisC–V correction method can also improve the capacitance drop of ultrathin oxides to an acceptable level
Fig. 4. Measured, two-frequency-corrected, and theoreticalC–V curves of the ultrathin oxynitride with EOT= 1.65 nm. Adopting two high frequencies in the two-frequency C–V correction and then using the C–V simulation program to perform the curve fitting may provide a simple and practical way to extract the EOT of ultrathin oxides.
in order to perform the curve fitting using aC–V simulation program. This technique could be readily integrated into the routineC–V measurements since only simple algebraic opera-tions are needed.
REFERENCES
[1] J. F. Lonnum and J. S. Johannessen, “Dual-frequency modified C–V technique,” Electron. Lett., vol. 22, no. 9, pp. 456–457, Apr. 1986. [2] K. J. Yang and C. Hu, “MOS capacitance measurements for
high-leakage thin dielectrics,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500–1501, Jul. 1999.
[3] A. Nara, N. Yasuda, H. Satake, and A. Toriumi, “Applicability limits of the two-frequency capacitance measurement technique for the thickness extraction of ultrathin gate oxide,” IEEE Trans. Semicond. Manuf., vol. 15, no. 2, pp. 209–213, May 2002.
[4] H. T. Lue, C. Y. Liu, and T. Y. Tseng, “An improved two-frequency method of capacitance measurement for SrTiO3as high-k gate dielectric,”
IEEE Electron Device Lett., vol. 23, no. 9, pp. 553–555, Sep. 2002.
[5] Z. Luo and T. P. Ma, “A new method to extract EOT of ultrathin gate dielectric with high leakage current,” IEEE Electron Device Lett., vol. 25, no. 9, pp. 655–657, Sep. 2004.
[6] B. Y. Tsui, Y. P. Huang, F. C. Hsieh, and W. H. Wu, “A new method to correct capacitance of high-leakage ultra-thin gate dielectric,” in Proc. Int.
Conf. Solid State Devices Mater., 2005, pp. 496–497.
[7] V. S. Chang, Y. T. Hou, P. F. Hsu, P. S. Lim, L. G. Yao, F. Y. Yen, C. L. Hung, J. C. Jiang, H. J. Lin, Y. Jin, C. C. Chen, H. J. Tao, S. C. Chen, S. M. Jang, and M. S. Liang, “Modeling and engineering of hafnium silicate (HfSiO) gate dielectric deposited by nano-laminated atomic layer deposition (NL-ALD),” in Proc. 208th Meeting J.
Elec-trochem. Soc. Conf., 2005. #483.
[8] J. R. Hauser and K. Ahmed, “Characterization of ultrathin oxides using electricalC–V and I–V measurements,” in AIP Conf. Proc. Charact.
Metrol. ULSI Technol., 1998, vol. 449, pp. 235–239.
[9] K. B. Chong, L. B. Kong, L. Chen, L. Yan, C. Y. Tan, T. Yang, C. K. Ong, and T. Osipowicz, “Improvement of dielectric loss tangent of Al2O3doped Ba0.5Sr0.5TiO3thin films for tunable microwave devices,”
J. Appl. Phys., vol. 95, no. 3, pp. 1416–1419, Feb. 2004.
[10] S. H.-M. Jen, C. C. Enz, D. R. Pehlke, M. Schroter, and B. J. Sheu, “Accurate modeling and parameter extraction for MOS transis-tors valid up to 10 GHz,” IEEE Trans. Electron Devices, vol. 46, no. 11, pp. 2217–2227, Nov. 1999.
[11] J. Schmitz, F. N. Cubaynes, R. J. Havens, R. de Kort, A. J. Scholten, and L. F. Tiemeijer, “RF capacitance–voltage characterization of MOSFETs with high leakage dielectrics,” IEEE Electron Device Lett., vol. 24, no. 1, pp. 37–39, Jan. 2003.
[12] J.-S. Goo, T. Mantei, K. Wieczorek, W. G. En, and A. B. Icel, “Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length,” IEEE Electron Device Lett., vol. 25, no. 12, pp. 819–821, Dec. 2004.
