A Novel Transmission-Line Deembedding Technique for RF Device Characterization

Abstract—A novel transmission-line deembedding technique

is presented in this paper. With this technique, the left- and right-side ground–signal–ground probe pads can be extracted directly using two transmission-line test structures of length L and 2L. An additional through structure is designed using via-stack deembedding, which is unique among current deembedding methods. The advantages of the proposed method include the following: 1) smaller silicon area; 2) discontinuity between the pad and interconnect; 3) substrate coupling and contact effects; and 4) employment of via-stack deembedding. The proposed novel methodology is a great breakthrough in the area of ultrahigh-frequency deembedding and should enable more accurate RF models to be developed. In the proposed methodology, intrinsic slow-wave CPW transmission-line structures are placed on the interlevel metallization layers, as they are the most appropriate RF device for cascade-based deembedding method involving the via-stack deembedding technique. Experimental results have demon-strated that attenuation loss and wavelength can be optimized by changing the metal density and the position of the metal layer on the floating shields. Both measurement and electromagnetic-wave simulations were performed up to 50 GHz. With a shortened wavelength, a reduction in silicon area of more than 66% can be achieved by using optimized slot-type floating shields.

Index Terms—Characterization, deembedding, slow wave,

transmission lines.

I. INTRODUCTION

T

HE EXTREME importance of accurate parasitic deem-bedding techniques to RF device characterization has already been established. In general, the parasitic contributions of device-under-test (DUT) structures mainly arise from probe pads, the interconnection lines connected to the intrinsic on-chip DUT structure, and the silicon substrate. Deembedding techniques can be classified as two groups. The first group is called the lumped-equivalent-circuit-model-based technique [1]–[9]. Between four to six deembedding structures are needed to obtain accurate results. However, this method involves a more complicated extraction and a larger chip in advanced CMOS processes. In this group, an extra grounded metal strip, which adds resistance and inductance to the short structure, is used as a connection between the two ports. The parasitic con-tribution of the extra grounded metal strip cannot be ignored if Manuscript received April 24, 2009; revised August 19, 2009. Current ver-sion published November 20, 2009. This work was supported by the National Science Council (NSC), Taiwan, under Grant NSC 97-2221-E-009-179. The review of this paper was arranged by Editor C.-Y. Lu.

H.-Y. Cho, J.-K. Huang, C.-W. Kuo, and S. Liu are with the Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan.

C.-Y. Wu is with National Chiao Tung University, Hsinchu 300, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2009.2032608

the frequencies are high or if the DUT structures are large. The second group involves a cascade-based deembedding technique [10]–[15] which enables the extraction of interconnection pa-rameters using through structures. To obtain the most practical test-key design, the metal interconnection from the probe pad to the intrinsic DUT structure should be around 20–40 μm. It is important to design a good “through” structure where the left and right pads are effectively uncoupled and do not suffer from the effects of an extra grounded metal strip. Therefore, cascade-based techniques are suitable for larger DUT structures, such as transmission lines, inductors, or MOSFETs with larger widths. In situations where real silicon is involved, RF DUT struc-tures are connected to the probe pad using low- to high-level metallization, and the cascade sequence is first metallization, then stacked metallization connected through via holes, and fi-nally top metallization. The contribution of the interconnection and the proposed methodology becomes important as the fre-quencies increase. Unfortunately, currently existing techniques do not account for via-stack parasitic methodology. In this paper, a novel transmission-line deembedding method, which requires two transmission-line structures of length L1and L2

and one additional through structure, is proposed to create a more accurate RF device characterization. Investigations on methodologies using via-stack deembedding, which have not been conducted previously, are performed in this paper. Two transmission-line structures are set up to achieve direct ex-traction of the left and right sides of ground–signal–ground (GSG) pads. One additional through structure is designed to solve the bottleneck resulting from via-stack deembedding and the uncertainty associated with direct measurement. Based on the experimental and simulation results from this paper, it can be concluded that direct extraction of the left- and right-side GSG pads and the via-stack deembedding method are the best options. When compared with conventional deembedding methods, the advantages of the proposed method include the following features: 1) smaller silicon area; 2) discontinuity between the pad and interconnect; 3) substrate coupling and contact effects; and 4) via-stack deembedding.

Coaxial transmission lines offer significant advantages for the design of integrated millimeter-wave circuits when com-pared to those offered by microstrip or coplanar-waveguide (CPW) transmission lines [16], [17]. Since coaxial transmission lines are shielded, lines and components can be closely spaced, and they can even pass over each other with minimal crosstalk, allowing for complex and compact signal routing. A slow-wave CPW transmission-line structure, where floating shields are both above and below the CPW structure, can be regarded as a rectangular coaxial transmission-line structure. Moreover, 0018-9383/$26.00 © 2009 IEEE

Fig. 1. Two transmission lines of lengths L1and L2are designed in a GSG configuration. (a) Transmission line of length L1[T L_l1]. (b) Transmission line of

length L2[T L_l2].

the design and performance of coaxial transmission lines are independent of any substrate. The slow-wave theory in the microwave range has been investigated with most grounded slow-wave structures [18]–[30]. As demonstrated in this paper, attenuation loss and wavelength can be adjusted by changing the metal density and the position of the floating shields on the metal layers.

II. NEWDEEMBEDDINGMETHODOLOGY

A. Left- and Right-Side GSG Pad Extraction

Fig. 1(a) and (b) shows the proposed deembedding test structures. Two transmission lines of length L1 and L2 are

in a GSG configuration. The discontinuity between the pad and interconnect is combined with that of the left- and right-side GSG pads. The transmission-line structure is decoupled into a series cascade of three two-port networks, including the left- and right-side GSG pads, together with the intrinsic transmission line. If the length is properly designed as L1=

2∗L2, the multiplication sum of ABCD matrix [PLEFT] and

[PRIGHT] can be extracted using the following:

[T Ll1] = [PLEFT][Ml1][PRIGHT] = [PLEFT][Ml2][Ml2][PRIGHT] (1) [T Ll2] = [PLEFT][Ml2][PRIGHT] (2) [PLEFT][PRIGHT] = [T Ll2][T Ll1] −1_{[T L} l2] =  ALR BLR CLR DLR  (3) where

[PLEFT] and [PRIGHT] ABCD matrices for the left- and

right-side GSG pads;

Fig. 2. Equivalent representation of a symmetrical structure.

[T Ll1] and [T Ll2] ABCD matrices for the

transmission-line structures of lengths L1and L2;

[Ml1] and [Ml2] ABCD matrices for the intrinsic

transmission-line structures of lengths L1and L2.

The left- and right-side GSG pad structures are symmetrical, and the equivalent circuit is shown in Fig. 2. By definition [31], [PLEFT] and [PRIGHT] can be represented as

[PLEFT][PRIGHT] =  1 1/Y2 Y1 1 + Y1/Y2   1 + Y1/Y2 1/Y2 Y1 1  (4)  1 1/Y2 Y1 1 + Y1/Y2   1 + Y1/Y2 1/Y2 Y1 1  = [T Ll2][T Ll1] −1_{[T L} l2] =  ALR BLR CLR DLR  (5)  1 + 2Y1/Y2 2/Y2 2Y1(1 + Y1/Y2) 1 + 2Y1/Y2  =  ALR BLR CLR DLR  . (6) Therefore, [PLEFT] and [PRIGHT] can be obtained using (7) and

(8), shown at the bottom of the page. After extracting [PLEFT]

and [PRIGHT], the performance of both the transmission lines

[PLEFT] =  1 BLR/2 CLR/ (1 + (ALR+ DLR)/2) 1 + BLRCLR/2 (1 + (ALR+ DLR)/2)  (7) [PRIGHT] =  1 + BLRCLR/2 (1 + (ALR+ DLR)/2) BLR/2 CLR/ (1 + (ALR+ DLR)/2) 1  (8)

Fig. 3. Connection between the low- and high-level metallization layers. (a) Top view of the ABCD matrix [A] of the DUT structure. (b) Cross section along the A–E cut.

Fig. 4. Matrix manipulation for the series cascade of [T hruLEFT][T hruRIGHT] with [T HRU ], [T LLEFT], and [PRIGHT]. (a) Cascade of

[T hruLEFT][T hruRIGHT]. (b) One additional through structure [T HRU ]. (c) Left-side transmission line of length L2[T LLEFT]. (d) Right-side GSG pad

[PRIGHT].

of lengths L1 and L2 can be extracted using the following,

allowing for additional extraction data: [Ml1] = [PLEFT]

−1_{[T L}

l1][PRIGHT]

−1 ₍₉₎

[Ml2] = [PLEFT]−1[T Ll2][PRIGHT]−1. (10)

Since [PLEFT], [PRIGHT], [Ml1], and [Ml2] can be extracted,

more variable combinations can be further cascaded to create more flexible deembedding dummy structures, which can also lead to the creation of an additional through structure.

B. Via-Stack Deembedding

Fig. 3(a) shows a top view of the ABCD matrix [A] of a DUT structure, where the ABCD matrices [T hruLEFT] and

[T hruRIGHT] are the left- and right-side interconnections. In

real tape-out, the intrinsic DUT structure can be placed on the interlevel metallization layer, while RF DUT structures are con-nected to the probe pad using low- to high-level metallization. First metallization, stacked metallization connected through via holes, and top metallization are included along the B–E cut, as shown in Fig. 3(b), using the proposed via-stack deembedding technique. An estimation of the impedance is obtained from an electromagnetic (EM) simulation (Ansoft HFSS), and the resistance ratio of the B–D cut over the B–E cut cannot be ignored. The ratio would be higher if either low-level metalliza-tion M1 or a shorter length D–E is involved. Since the minimum interconnect length between port1 and port2 is around 40 μm, probe-to-probe coupling with such short interconnect could be a potential limitation. For medium or large devices, or small-cascaded devices, the distance between port1 and port2 in Fig. 3(a) is above 100 μm. Therefore, it is necessary to design a good “through” test structure in order to obtain stable

measurement results. One additional through structure is de-signed, as shown in Fig. 4(b), and its ABCD matrix [T HRU ] is equal to [T LLEFT][T hruLEFT][T hruRIGHT][PRIGHT], where

the ABCD matrix [T LLEFT] is the left-side transmission line

of length L2 and is equal to [T Ll2][PRIGHT]−1, as shown in

Fig. 4(c). The optimized length of L2is designed based on two

criteria: 1) The maximum length cannot be too long because the parasitics of interest will represent a smaller faction of the measured structure, and 2) the minimum length cannot be so short as to decrease probe-to-probe coupling.

[T hruLEFT][T hruRIGHT] can be extracted from the

fol-lowing equation, and the corresponding explanation is shown in Fig. 4:

[T hruLEFT][T hruRIGHT]

= [T LLEFT]−1[T HRU ][PRIGHT]−1. (11)

Using (7) and (8), the matrices [T hruLEFT] and [T hruRIGHT]

can be calculated, respectively. The length of [T hruLEFT] and

[T hruRIGHT] cannot be too long in order to maintain the

validity of the deembedding technique when high frequen-cies are involved. After determining [PLEFT], [T hruLEFT],

[T hruRIGHT], and [PRIGHT], the ABCD matrix [A] of the

intrinsic DUT structure can be extracted using (12) through the matrix manipulation of the ABCD matrix [A] of the DUT struc-ture with the and right-side interconnections and the left-and right-side GSG pad, as shown in Fig. 3(a). The proposed deembedding method can also be used with asymmetrical DUT structures by designing another through dummy structure [A] = [PLEFT]−1[T hruLEFT]−1[A]

Fig. 5. Comparison of the measured transmission-line performances for Deembedding_L2L, Deembedding_LS [14], Deembedding_OS, and EM simulation with (a) resistance and (b) inductance.

C. Deembedding Procedure

The proposed deembedding procedure involves the following steps:

1) measurement of the scattering matrices of the transmis-sion lines of lengths L1 and L2, the one additional

through structure, and the DUT structure, as shown in Figs. 1(a) and (b), 3(a), and 4(b), respectively;

2) conversion of the scattered matrices of the transmission lines of lengths L1 and L2, the one additional through

structure, and the DUT structure to their ABCD matrices [T Ll1], [T Ll2], [T HRU ], and [A], respectively;

3) calculation of the ABCD matrices of the left- and right-side GSG pads [PLEFT] and [PRIGHT], respectively,

using (1)–(8);

4) calculation of the ABCD matrices of the left- and right-side through [T hruLEFT] and [T hruRIGHT],

respec-tively, using (11), and (7) and (8);

5) calculation of the ABCD matrix [A] of the intrinsic DUT structure using (12).

III. EXPIMENTALRESULTS ANDDISCUSSION

A. Comparative Results of Deembedding Techniques

One open, one short, and two microstrip transmission lines of lengths L1= 1000 μm and L2= 500 μm were designed. The

S-parameters of the transmission-line DUT structures were mea-sured up to 50 GHz using an Agilent 8510C. The proposed test structures were fabricated using 65-nm RF-CMOS technology. The results of a comparison of the proposed technique denoted as Deembedding_L2L, the Mangan’s method [14] denoted as Deembedding_LS, an open-short deembedding technique de-noted as Deembedding_OS, and an EM simulation are shown in Fig. 5. Lesser resistance and inductance values remain after the conventional open-short deembedding is performed. An extra grounded metal strip of the short structure results in over deembedding. Fig. 5 shows an adequate agreement between the proposed deembedding technique and EM simulation.

In general, the assumption for a two-step, a three-step, and a four-step deembedding method is valid only if the lengths of the DUT devices are much smaller than the distances be-tween port1 and port2. However, this is not always true for larger DUT devices and may result in over deembedding when

intrinsic device performance is involved. Therefore, the pro-posed deembedding technique can address the problem of over deembedding. Moreover, it is the best choice when larger DUT devices are involved, such as transmission lines, inductors, and MOSFETs with larger widths. As the left- and right-side GSG pads are extracted directly, in addition to substrate coupling and contact effects provided by a four-step deembedding method, the proposed method accounts for the discontinuity between the pad and interconnect.

B. Via-Stack Deembedding Applications and Slow-Wave CPW Transmission Lines

A capacitor device is chosen as the subject of a study to com-pare with and without via-stack deembedding methods. The B–E cut is deembedded using the via-stack technique, while the D–E cut is deembedded without the via-stack technique, as shown in Fig. 3(b). As the ideal deembedded data are known, the comparative results based on the 40% resistance ratio of the B–D cut over B–E cut are shown in Fig. 6. It is shown that there is an obvious improvement in accuracy and capacitance performance using the via-stack deembedding method. Intrinsic slow-wave CPW transmission-line structures are placed on the interlevel metallization layers as they are the most appropriate RF device for cascade-based deembedding methods involving the via-stack deembedding technique.

Two types of transmission lines were fabricated as listed in Table I, including as follows: 1) a CPW transmission line with-out shields (CPW) and 2) three slow-wave CPW transmission lines with slot-type floating shields (FSCPW1, FSCPW2, and FSCPW3), as shown in Fig. 7. A slow-wave CPW transmission line was designed where periodically aslot-type floating shields are located both above and below the CPW structure, and they are oriented transversely to the CPW structure. For all the transmission lines in Table I, the CPW structure is formed on the eighth (M8) metal layer, and the lower slot-type shields are created on either the seventh (M7) or second (M2) metal layer. The CPW part has a signal/ground linewidth of 10 μm/10 μm, with a 20-μm space between the signal and ground lines. The upper floating shields are formed on the ninth (M9) metal layer with a fixed strip length (SL) of 2 μm and a fixed strip space (SS) of 2 μm. The SL of lower floating shields is designed to be the minimum length required to achieve a high performance

Fig. 6. Comparison of the simulated capacitor performances for via-stack deembedding and without via-stack deembedding with (a) quality factor and (b) capacitance.

TABLE I

TRANSMISSIONLINESTRUCTURES

Fig. 7. Schematic view of a slow-wave CPW transmission line with slot-type floating shields.

with minimal eddy-current loss. The lower slot-type floating shields are designed with the following dimension splits: 1) the SL on M7 is 0.1 μm and the accompanying SS is either 0.1 or 0.9 μm, and 2) the SL on M2 is 0.1 μm and the accompanying SS is 0.1 μm.

The performance of a transmission line can be characterized by attenuation loss per unit length α in N eper/m, character-istic impedance Zc in Ω, and effective relative permittivity εr, which can be expressed, respectively, as follows:

α = real(γ) ZC=  R + jωL γ  εr= 9· 1016·  β ω 2

where ω is the angular frequency, R is the resistance per unit length, L is the inductance per unit length, γ is the propagation constant, and β = 2π/λ is the phase constant [32]. Generally, lower attenuation loss and shorter wavelength are required to achieve high-performance transmission line and compactness.

Fig. 8(a) shows that the attenuation loss of FSCPW3 is lower than that of FSCPW1, because the dielectric thickness between the signal line on M8 and the floating shields on M2 is greater than the dielectric thickness between the signal line on M8 and the floating shields on M7. These results indicate that the currently prevalent opinion which supports the view that highest density shields are the best choice [33] is not always true. As frequencies increase, lower density coverage FSCPW2 exhibits a lower attenuation loss than does FSCPW1. In summary, the smaller the SL and the greater the thickness between the signal line and the floating shields, the lower the induced attenuation loss.

Fig. 8(b) shows that lower characteristic impedance can be achieved by increasing floating shield density or by raising the position of the metal layer. Characteristic impedance tuning by changing the metal density and the position of the metal layer in the slot-type floating shields offers a new design approach.

The wavelength of a transmission line indicates whether the transmission-line design is compact. Therefore, the wave-lengths of transmission lines with a variety of slot-type floating-shield designs are compared in Fig. 8(c). From this, it is shown that the best choice is FSCPW1, whose wavelength is reduced to 1.19 mm, i.e., by a factor of more than three when compared to that of a conventional CPW transmission line with a wavelength of 3.58 mm. As a result, a reduction in silicon area of more than 66% can be achieved, which demonstrates that this approach is potentially highly attractive for MMIC applications.

An optimized design requires a good quality factor, such as

Q = β/2α, where β is the phase constant and α is the

atten-uation loss, and it should be used to judge an overall tradeoff between attenuation loss and wavelength. Guidelines for de-signing a transmission line with a high quality factor are shown in Fig. 8(d). It is shown that FSCPW1 is the most appropriate choice for designs operating at frequencies below 50 GHz. As discussed earlier and demonstrated in the experiments,

Fig. 8. Comparison of the measured transmission-line performances for different floating shields. (a) Attenuation loss. (b) Characteristic impedance. (c) Wavelength. (d) Quality factor.

Fig. 9. Simulated slow-wave CPW transmission-line performance versus parameter R with different SL and metal layer position at signal frequency of 50 GHz. (a) Effective relative permittivity and attenuation loss. (b) Optimization index value of εr· α−1.

the lower the attenuation loss, the longer the wavelength usually obtained. Therefore, a designer must weigh up the pros and cons between SL and SS dimensions together with metal layer positions in order to design a suitable slow-wave CPW to achieve a functional circuit at the desired operating frequency.

C. Optimized Simulation for Slot-Type Floating Shields in Transmission Lines

The optimization of slot-type floating shields to reduce simultaneously attenuation loss and wavelength is performed. Optimization analyses on SL, SS, and the position of floating shields are conducted by analyzing the EM simulation results. The density R of the slot-type floating shields is defined as follows:

R = SL

SL + SS. (13)

Fig. 9(a) shows that a higher effective relative permittivity is achieved with a smaller SL, higher density R, and smaller dielectric thickness between the signal line and the floating shields. When the attenuation loss is taken into consideration, a minimized SL is the best choice for both effective relative permittivity and attenuation loss performance. The optimization index of the slot-type floating shields is defined as εr· α−1in millimeters per decibel, and Fig. 9(b) shows that an optimized performance is achieved when the SL = 1 μm and SS = 2 μm on M7. The optimized floating shields include a minimized

SL, medium density R, and high metal layer position. Only

after the specification requirements for the attenuation loss is determined, the density of the slot-type floating shields can be calculated. Consequently, the effective relative permittivity can be predicated from the minimized SL and the density of the slot-type floating shields. Since both SL and the SS can be adjusted in accordance with technology scaling, a scaled

fects provided by existing four-step deembedding methods, the proposed method also accounts for the discontinuity between the pad and interconnect. Current deembedding techniques do not deembed via-stack parasitic and the contribution of the pro-posed method becomes more important as frequency increases. As [PLEFT], [PRIGHT], [Ml1], and [Ml2] can be extracted,

more flexible deembedding dummy structures can be created. Therefore, an additional through structure can be designed to perform via-stack deembedding. The proposed deembedding method can be extended to other RF devices, and this will allow for more accurate RF device characterization.

It has been shown that attenuation loss and wavelength can be optimized by changing the SL, SS, and metal layer position of the slot-type floating shields while keeping the same area. An optimization index of the slow-wave CPW transmission lines has been developed to enable circuit designers to determine expediently the most appropriate slot-type floating shields to meet design specifications. Designers, therefore, must weigh up the pros and cons concerning SL and SS dimensions, as well as with metal layer positions, in order to design a slow-wave CPW with suitable slot-type floating shields. The proposed floating slow-wave CPW transmission line has a better quality factor of 15 at 50 GHz and a shorter wavelength which results in a reduction of silicon area of more than 66% when compared to that of conventional CPW transmission lines. In short, a significant advantage for future technology scaling and RF circuit designing is made available through the use of more suitable SL and SS.

REFERENCES

[1] H. Cho and D. Burk, “A three-step method for the de-embedding of high-frequency S-parameter measurements,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1370–1375, Jun. 1991.

[2] T. E. Kolding, “A four-step method for de-embedding gigahertz on-wafer CMOS measurements,” IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 734–740, Apr. 2000.

[3] E. P. Vandamme, D. M. M.-P. Schreurs, and C. van Dinther, “Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures,” IEEE Trans.

Electron Devices, vol. 48, no. 4, pp. 737–742, Apr. 2001.

[4] C. Andrei, D. Gloria, F. Danneville, and G. Dambrine, “Efficient de-embedding technique for 110-GHz deep-channel-MOSFET characteriza-tion,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 4, pp. 301–303, Apr. 2007.

[5] A. Issaoun, Y. Z. Xiong, J. Shi, J. Brinkhoff, and F. Lin, “On the de-embedding issue of CMOS multigigahertz measurements,” IEEE Trans.

Microw. Theory Tech., vol. 55, no. 9, pp. 1813–1823, Sep. 2007.

[6] J. Cha, J. Cha, and S. Lee, “Uncertainty analysis of two-step and three-step methods for deembedding on-wafer RF transistor measurements,” IEEE

Trans. Electron Devices, vol. 55, no. 8, pp. 2195–2201, Aug. 2008.

[7] Q. Liang, J. D. Cressler, G. Niu, Y. Lu, G. Freeman, D. C. Ahlgren, R. M. Malladi, K. Newton, and D. L. Harame, “A simple four-port para-sitic de-embedding methodology for high-frequency scattering parameter and noise characterization of SiGe HBTs,” IEEE Trans. Microw. Theory

Tech., vol. 51, no. 11, pp. 2165–2174, Nov. 2003.

[11] M.-H. Cho, G.-W. Huang, K.-M. Chen, and A.-S. Peng, “A novel cascade-based de-embedding method for on-wafer microwave characterization and automatic measurement,” in Proc. IEEE MTT-S Int. Microw. Symp. Exhib., Jun. 2004, vol. 2, pp. 1237–1240.

[12] M. H. Cho, C. S. Chiu, G. W. Huang, Y. M. Teng, L. H. Chang, K. M. Chen, and W. L. Chen, “A fully-scalable de-embedding method for on-wafer S-parameter characterization of CMOS RF/microwave devices,” in Proc. IEEE RFIC Symp. Dig. Papers, Jun. 2005, pp. 303–306. [13] M.-H. Cho, G.-W. Huang, L.-K. Wu, C.-S. Chiu, Y.-H. Wang,

K.-M. Chen, H.-C. Tseng, and T.-L. Hsu, “A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp. 2926–2934, Sep. 2005.

[14] A. M. Mangan, S. P. Voinigescu, M.-T. Yang, and M. Tazlauanu, “De-embedding transmission line measurements for accurate modeling of IC designs,” IEEE Trans. Electron Devices, vol. 53, no. 2, pp. 235–241, Feb. 2006.

[15] K. H. K. Yau, A. M. Mangan, P. Chevalier, P. Schvan, and S. P. Voinigescu, “A transmission-line based technique for de-embedding noise parame-ters,” in Proc. IEEE Int. Conf. Microelectron. Test Struct., Mar. 2007, pp. 237–242.

[16] J. Reid, E. Marsh, and R. Webster, “Micromachined rectangular-coaxial transmission lines,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 8, pp. 3433–3441, Aug. 2006.

[17] E. Marsh, J. Reid, and V. Vasilyev, “Gold-plated micromachined millimeter-wave resonators based on rectangular coaxial transmission lines,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 1, pp. 78–84, Jan. 2007.

[18] R. D. Lutz, V. K. Tripathi, and A. Weisshaar, “Enhanced transmission characteristics of on-chip interconnects with orthogonal gridded shield,”

IEEE Trans. Adv. Packag., vol. 24, no. 3, pp. 288–293, Aug. 2001.

[19] X. Wang, W. Y. Yin, and J. F. Mao, “Parameter characterization of silicon-based patterned shield and patterned ground shield coplanar waveguides,” in Proc. GSMM, Apr. 21–24, 2008, pp. 142–145.

[20] T. S. D. Cheung and J. R. Long, “Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1183–1200, May 2006.

[21] I. C. H. Lai and M. Fujishima, “High-Q slow-wave transmission line for chip area reduction on advanced CMOS processes,” in Proc. IEEE

ICMTS, Mar. 19–22, 2007, pp. 192–195.

[22] Z. Lei, “Guided-wave characteristics of periodic coplanar waveguides with inductive loading—Unit-length transmission parameters,” IEEE

Trans. Microw. Theory Tech., vol. 51, no. 10, pp. 2133–2138, Oct. 2003.

[23] T. S. D. Cheung, J. R. Long, K. Vaed, R. Volant, A. Chinthakindi, C. M. Schnabel, J. Florkey, and K. Stein, “On-chip interconnect for mm-wave applications using an all-copper technology and mm-wavelength reduc-tion,” in Proc. ISSCC Dig. Tech. Papers, Feb. 2003, pp. 396–501. [24] A. Komijani, A. Natarajan, and A. Hajimiri, “A 24-GHz, +14.5-dBm

fully integrated power amplifier in 0.18-μm CMOS,” IEEE J. Solid-State

Circuits, vol. 40, no. 9, pp. 1091–1098, Sep. 2005.

[25] I. C. H. Lai, Y. Kambayashi, and M. Fujishima, “60-GHz CMOS down-conversion mixer with slow-wave matching transmission lines,” in Proc.

IEEE ASSCC, Nov. 2006, pp. 195–198.

[26] W. Kim and M. Swaminathan, “Characterization of co-planar silicon transmission lines with and without slow-wave effect,” IEEE Trans. Adv.

Packag., vol. 30, no. 3, pp. 526–532, Aug. 2007.

[27] M. H. Cho, G. W. Huang, K. M. Chen, H. C. Tseng, and T. L. Hsu, “Slow-wave characteristics of interconnects on silicon substrates,” in Proc. Int.

Semicond. Device Res. Symp., Dec. 2003, pp. 188–189.

[28] G. Wang, W. Woods, H. Ding, and E. Mina, “Novel low-cost on-chip CPW slow-wave structure for compact RF components and mm-wave applications,” in Proc. 58th ECTC, May 27–30, 2008, pp. 186–190. [29] D. B. Lin, “Signal integrity of bent differential transmission lines,”

Hsiu-Ying Cho received the M.S. degree in

elec-tronic engineering from National Tsing Hua Uni-versity, Hsinchu, Taiwan. She is currently working toward the Ph.D. degree at National Chiao Tung University, Hsinchu.

In 1999, she joined as an Engineer of Process Inte-gration with the Taiwan Semiconductor Manufactur-ing Company, Hsinchu, where she moved onwards to the SPICE Modeling Department in 2003. Her cur-rent research activity is focused on development of high-frequency device characterization, and device modeling and simulation.

Jiun-Kai Huang was born in Taichung, Taiwan, in

1981. He received the B.S. degree in nuclear sci-ence from National Tsing Hua University, Hsinchu, Taiwan, in 2003 and the M.S. degree in electrical engineering from the National Chiao Tung Univer-sity, Hsinchu, in 2005. His thesis was focused on the design and fabrication of silicon carrier for the system-on-package application in RFICs.

He joined the Taiwan Semiconductor Manufactur-ing Company, Hsinchu, where he is currently work-ing on high-frequency characterization and modelwork-ing of RF devices in addition to RF circuit design.

Chin-Wei Kuo was born in Keelung, Taiwan, in

1976. He received the M.S. and Ph.D. degrees from the Department Electric Engineering, National Cen-tral University, Chung-Li Taiwan, in 1997 and 2003, respectively. His doctoral dissertation was focused on the CMOS model and its application in the optical and microwave circuits.

In 2003, he joined the Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, where he is working in the area of CMOS device modeling and characterization and is currently the Manager of the RF Device Modeling Team.

include in the research and development of device modeling and simulation, circuit simulation and optimization, statistical modeling and design centering, circuit verification, IP characterization, and EDA framework.

Chung-Yu Wu (S’76–M’76–SM’96–F’98) was born

in 1950. He received the M.S. and Ph.D. degrees from the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 1976 and 1980, respectively.

Since 1980, he has been serving as a Consultant to high-tech industry and research organizations and has built up strong research collaborations with high-tech industries. From 1980 to 1983, he was an Asso-ciate Professor with National Chiao Tung University, where since 1987, he has been a Professor and is currently the President and Chair Professor. From 1984 to 1986, he was a Visiting Associate Professor in the Department of Electrical Engineering, Portland State University, Portland, OR. From 1991 to 1995, he was rotated to serve as the Director of the Division of Engineering and Applied Science, National Science Council, Taiwan. From 1996 to 1998, he was honored as the Centennial Honorary Chair Professor with National Chiao Tung University. In the summer of 2002, he conducted postdoctoral research with the University of California, Berkeley. He has published more than 250 technical papers in international journals and conferences. He is the holder of 19 patents, including nine U.S. patents. His research interests are nanoelectronics, biochips, neural vision sensors, RF circuits, and CAD analysis.

Dr. Wu is a member of Eta Kappa Nu and Phi Tau Phi Honorary Scholastic Societies. He was the recipient of the IEEE Fellow Award in 1998 and a Third Millennium Medal in 2000. In Taiwan, he was the recipient of numerous research awards from the Ministry of Education, National Science Council, and professional foundations.