The design of wideband and low-power CMOS active polyphase filter and its application in RF double-quadrature receivers

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The Design of Wideband and Low-Power CMOS

Active Polyphase Filter and its Application in RF

Double-Quadrature Receivers

Chung-Yun Chou, Student Member, IEEE, and Chung-Yu Wu, Fellow, IEEE

Abstract—In this work, a new technique to implement the

transfer function of polyphase filter with CMOS active com-ponents is proposed and analyzed. In the proposed polyphase filter structure, the currents mirrored from capacitors and the transistors in a single-stage are used to realize high-pass and low-pass functions, respectively. The multistage structure expands the frequency bandwidth to more than 20 MHz. Furthermore, a constant-gm bias circuit is employed to decrease the sensitivity of image rejection to temperature and process variations. HSPICE simulations are performed to confirm the performance. With the current-mode operation, the low-voltage version of proposed active polyphase filters was designed. It can be operated at 1-V power supply with similar performance but with only 50% of the power dissipation of the normal-voltage version. The proposed four-stage polyphase filter is fabricated in 0.25- m CMOS 1P5M technology. The measured image rejection ratio is higher than

48 dB at frequencies of 6 1 MHz 30 MHz. The measured

voltage gain is 6.6 dB at 20 MHz and IIP3 is 8 dBm. The power dissipation is 11 mW at a supplied voltage of 2.5 V and the active chip area is 1162 813 m2.

Index Terms—CMOS technology, double-quadrature

architec-ture, low intermediate frequency architecarchitec-ture, polyphase filter, RF receiver.

I. INTRODUCTION

T

HE fast growth of wireless applications in recent years has driven intense efforts to design highly integrated, high-per-formance, low-cost RF integrated circuits (ICs). Both low inter-mediate frequency (IF) [1]–[3] and double-quadrature [4]–[6] architectures have been adopted as promising receiver topolo-gies to realize these design goals because they combine the ad-vantages of IF and zero-IF architectures. In the low-IF receiver [1]–[3], the RF signal is amplified and down-converted to a low IF signal in a single step through the quadrature converter. After down-conversion, polyphase filters must be used to filter image signals at the intermediate frequency for both and channels. DC offsets and -noise do not disrupt the desired signal since this signal is brought to the intermediate frequency beyond the -noise corner. The use of on-chip polyphase filters facilitates

Manuscript received April 1 2004; revised October 5, 2004. This work was supported by the National Science Council (NSC), Taiwan, R.O.C., under Grant NSC 91-2215-E-009-080. This paper was recommended by Associate Editor B. Maundy.

The authors are with the Integrated Circuits and Systems Laboratory, Department of Electronics Engineering and Institute of Electronics, Na-tional Chiao Tung University, Hsingchu 300, Taiwan, R.O.C. (e-mail: cywu@alab.ee.nctu.edu.tw; m8711581@alab.ee.nctu.edu.tw).

Digital Object Identifier 10.1109/TCSI.2005.846672

the integration of low-IF receivers. In the double-quadrature re-ceiver (DQR) [4]–[6], the low-IF architecture is incorporated to further improve the sensitivity in multipath mismatches on a low-IF receiver. In the DQR, both RF and image signals are sep-arated into quadrature phases. After down-conversion, on-chip polyphase filters are also required to sieve out the desired signal at the intermediate frequency and achieve high integration.

To avoid the signal-to-noise ratio (SNR) degradation by image interferences, a polyphase filter should provide high se-lectivity between the desired and image signals. Moreover, the power consumption must be low to prolong the lifetime of the batteries for use in portable wireless communications systems. Polyphase filters in some current standard applications require wide bandwidths. For example, a 20-MHz channel bandwidth is required for WLAN IEEE 802.11a and HIPERLAN. Ac-cordingly, the design of high-performance, wideband, and low-power on-chip polyphase filters for these applications are critically needed.

So far, many polyphase filters have been proposed [3], [7]–[11]; they can be divided into two types, namely passive RC polyphase filters and active polyphase filters. Passive RC polyphase networks are used in passive RC polyphase filters [3], [7], [8]. The voltage transfer function of the RC polyphase networks depends on the phase order of the input sequence; it can distinguish between signals with positive frequencies and those with negative frequencies. The passive RC polyphase filter can exhibit a high image rejection ratio (IRR), but has a limited range of operating frequencies. The desirable filtering function can only be obtained in the narrow band around the pole frequency, which depends on the RC time constant. To increase the bandwidth, a multistage network is proposed to achieve the broadband response [3], [7], [8].

The expense of the multistage passive polyphase filter is that it is lossy, so its output signal decays. Additional buffers should be inserted among the stages to compensate the loss. However, these buffers significantly increase the power consumption. More power is consumed as more stages are used to increase the bandwidth. Furthermore, the variation of resistances and capacitances should be kept within a desired small range to achieve a high IRR. This means large chip area is required because the variations of adjacent on-chip resistances and capacitances are inversely proportional to their surface area. As the area of resistors increases, it also increases the parasitic capacitance and lowers the cut-off frequencies of resistors. Thus, a critical tradeoff must be made among IRR, chip area 1057-7122/$20.00 © 2005 IEEE

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826 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 5, MAY 2005

and maximum operational frequency of passive RC polyphase filters.

Active polyphase filters have the general advantages of low power dissipation, small chip area and high signal gain. All the active polyphase filters proposed so far [9]–[11] have op-erating frequencies in the range of several hundreds of kilohertz to several of megahertz. The polyphase filter in [9] provides a good IRR at 250 kHz by using op-amp circuits. In [10], the ac-tive gm-c polyphase filter provides a dB of IRR at 3 MHz without tuning circuits by using a well-controlled special analog process. In [11], the gm-c polyphase filter with common-mode feedback (CMFB) and common-mode feed forward (CMFF) circuits and frequency-tuning circuits, can achieve more than dB of IRR in a bandwidth of 1 MHz with a central fre-quency of 2 MHz.

In this work, a new broadband CMOS active polyphase filter with a wide range of operating frequencies is proposed and de-signed by using the basic polyphase filter architecture which is used to implement passive RC polyphase filter. A constant-gm bias circuit is used to decrease the sensitivities of the filter gain and the bandwidth to temperature and process variations. Ad-ditionally, the multistage approach is also applied to achieve the wide bandwidth. Due to the high input impedance in each stage, the proposed active polyphase filter can avoid the degra-dation of gain between pairs of stages when connected in cas-cade. Thus, power-consuming buffers are not required. Using 0.25- m CMOS 1P5M technology, the proposed four-stage ac-tive polyphase phase filter can achieve an IRR of dB in the MHz MHz band. The filter consumes 11 mW (5.5 mW) with a power supply of 2.5 V (1 V). A higher IRR can be achieved by increasing the number of cascaded stages although the achievable IRR is limited by matching.

The active polyphase filter has been designed and integrated into a DQR in 0.18- m CMOS 1P6M technology [5], [6]. The measured dB IRR verifies that the proposed active polyphase filter is suitable for wireless communication appli-cations.

The rest of this paper is organized as follows. Section II presents the models of a polyphase filter and DQR. Section III describes the circuit implementations of the proposed active polyphase filter. HSPICE simulation results verify the func-tions of the circuits. Section IV presents experimental results. Finally, Section V draws conclusions.

II. MODELS FORPOLYPHASEFILTERS ANDDQR A. Model for Polyphase Filters

The polyphase filter is a complex filter because its frequency response is not symmetrical around dc. The transfer function

of a complex filter can be represented as [8]

(1) where and are the real and imaginary parts of the complex transfer function. If a complex signal

Fig. 1. Signal flowgraph for realizing a single-stage complex filter [8].

is applied to this complex filter, the output signal can be written as

(2) (3) (4) where and are the real and imaginary parts of , respectively. If can be generated by a circuit from the input complex signal according to (3) and (4), then the complex transfer function can be realized by this circuit. Fig. 1 [8] shows the signal flowgraph for the realization of by using (3) and (4). In this way, any complex filter can be realized by a combination of the real and imaginary parts of its transfer functions.

The transfer function of the one-stage RC network can be used to implement a polyphase filter, according to the ap-proach presented above. The resultant transfer function is represented as

(5)

where and are the gain and pole frequency, respectively, of the first-order low-pass filter and the high-pass filter . The combination of and forms a block de-noted as the low-high-pass filter (LHF) in Fig. 1. According to (5), the transfer curves of and versus fre-quency for and MHz are shown in Fig. 2 in solid lines. Notably, the desired signal with negative frequency falls in the filter’s passband while the image signal at positive frequency is attenuated. is lowest at where is also called the rejected frequency. Using the equation in (5), the IRR of the polyphase filter defined as the ratio of the magnitude in the attenuation band to that in the passband, can be derived as

(6)

As may be seen from (6), the can be zero at frequency if the gains and pole frequencies of and are perfectly matched.

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Fig. 2. Transfer curves ofjH(s)j versus frequency.

If the gains and pole frequencies of and are not identical because of mismatching, then (5) can be rewritten as

(7) where and are the mismatch quantities of and , respectively. The simulated and versus fre-quency with 20% variations are shown by the dashed lines in Fig. 2. It is shown that the transfer curves of and are shifted to the opposite directions and the resulting at is degraded. Using (7) and ne-glecting high-order terms, the IRR with mismatch ef-fects can be derived as (8) at the shown at the bottom of the page. Fig. 3 depicts the exact with the corre-sponding mismatches and , where the numbers on the curves denote the values in decibels. The figure

demonstrates that if or , then

the at is degraded to dB. Therefore, the gains and locations of the pole frequencies in and should be kept highly consistent to achieve the desired image rejection performance.

A broadband polyphase filter can be realized by cascading several stages of one-stage polyphase filter. The resultant IRR of the -stage polyphase filter can be derived by

Fig. 3. Simulated IRR values (indicated on the curves) of one-stage polyphase filter at! = ! with gain and pole frequency variations.

multiplying all values of the constituent one-stage polyphase filters as

(9)

where is the of the th-stage polyphase filter. Ideally, the IRR can be improved with a cascaded mul-tistage structure, as indicated by (9). But in the practical case, the highest achievable IRR is limited by the inevitable circuit mismatches among stages. Note that the range of operating fre-quencies can also be expanded by assigning a different value of

to each one-stage polyphase filter. B. Model for the DQR

Fig. 4 shows the structure of a DQR, in which polyphase fil-ters are used in both and channels. The difference between the DQR and the conventional low-IF receiver is that, after the LNA has amplified the RF input signal, the quadrature gener-ator transforms this into the in-phase and quadrature-phase sig-nals and . Both and signals are sent to the four down-conversion mixers, along with the input quadrature signals and from the quadrature VCO, to realize the complex multiplication function

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Fig. 4. Block diagram of DQR.

Fig. 5. Signal spectra in the DQR (a) before the down-conversion and (b) after the down-conversion.

and generate the intermediate frequency sig-nals and . The poylphase filters are used to filter the image signals at the intermediate frequency to prevent interfer-ence with the desired signals.

Using the complex signal representation [4], Fig. 5(a) and (b) display the signal spectra in the DQR before and after down-conversion, respectively. and in Fig. 5(a) refer to the spectra of the desired signals and the image signals at the output of the quadrature generator, respectively. refers to the spectrum of the quadrature local oscillation signals. Thus,

and .

, and represent the crosstalk image signals of , and , respectively. The image-to-signal

ratio (ISR) , and

can be calculated by the corresponding phase and amplitude mismatches [4]. After the frequency translation, as shown in

Fig. 5(b), the , , and are

down-converted to , , and , respectively.

The image mixes with at and cannot be re-moved by the following polyphase filters. The value of can be represented as

(10)

where , and denote the ISRs caused

by imbalances in the quadrature generator, the local oscil-lator and the mixers, respectively. For , and , the term in (10) is negligible relative to . Therefore, is determined by the gain/phase errors of the mixers and . The DQR exhibits better image rejection performance than the conven-tional low-IF receiver, because is smaller and almost unaffected by .

The image , which is down-converted from , is located at whereas the desired signal is at . The polyphase filters should reject at to prevent interference with the . If the multistage polyphase filter can provide an IRR , then the total IRR

of the DQR can be derived by using (10), and the relations

, and

. Neglecting the high-order terms yields

(11) As may be seen from (11), the overall IRR of the DQR is de-termined mainly by the ISR of the mixers and the IRR of the polyphase filter. To achieve high , the symmetry of the layout in mixers between the and channels should be re-garded as reducing the amplitude of crosstalk image signals. Additionally, the polyphase filter must have a high capacity for rejecting images at intermediate frequencies.

III. CIRCUITIMPLEMENTATION A. 2.5-V Polyphase Filter

The proposed polyphase filter structure in Fig. 1 consists of a low-pass filter and a high-pass filter in each of the two LHF blocks. The CMOS realization of a LHF block is shown in Fig. 6(a) where the functions of and are combined. In Fig. 6(a), the nMOS device converts the input voltage to current and then the current is mirrored to and by the pMOS current mirrors , , and . The diode-connected transistor and the capacitor then divide the mirrored current into and , , respectively. The currents and can be derived as

(12) (13)

where and are the transconductances of and , respectively. Using the mirrored currents and , the required

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Fig. 6. (a) Circuit of LHF. (b) Differential type of LHF and its equivalent functionality block LHFD. (c) Block diagram ofH(s).

low-pass and high-pass transfer functions and can be realized as

(14)

(15)

where is the current ratio of and , is the current ratio of ( ) and ( ), and ( ) is the transcon-ductance of ( ). The capacitor connected between node and is used to pass the ac current , but block the dc voltage. The rejected frequency can be adjusted by changing since the poles of both transfer

func-tions and are determined by .

The parasitic effects of the LHF circuit in Fig. 6(a) are ana-lyzed. The parasitic capacitance at node has the largest value as compared to those at other nodes, because consists of the parasitic capacitance of and the device capacitance of

and . With at node , the transfer function of can be derived as

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As (16) shows, the second pole at

is generated. Since may affect the magnitude and phase of and thus degrade the IRR of the polyphase filter, should be kept at least ten times larger than to minimize the degradation of IRR.

Based on the structure illustrated in Fig. 1, a one-stage polyphase filter with a differential structure can be real-ized by the combination of LHF circuits. In general, the mixers used in the receiver are designed in differential circuits to cancel the LO-to-IF feedthrough. Thus the proposed polyphase filter is designed in differential type to process the differential output signals from the mixers. Fig. 6(b) shows the differential LHF, LHFD. The LHFD consists of two LHFs with a common current source device , which is used to provide the bias cur-rent of LHF and reject the input common mode signal. Fig. 6(c) shows the complete circuit of one-stage polyphase filter, based on the structure in Fig. 1. The output node of is connected to the output node of to realize the subtraction function in Fig. 1, whereas the summation function in Fig. 1 is realized by connecting the output node of to the output node of . Finally, the output currents are converted to voltages by connecting them to diode-connected transistors , , and . Fig. 6(c) realizes the signal flowgraph of Fig. 1 in differential structure.

A broadband multistage polyphase filter can be realized by cascading several stages of one-stage polyphase filters. Unlike the passive RC polyphase filter, cascading the proposed active polyphase filters can avoid the degradation of gain among stages because the input impedance in each stage is high. In each stage, should be adjusted to obtain different reject frequencies. All other circuits in Fig. 6(c) remain unchanged, greatly reducing the complexity of the design of a multistage polyphase filter.

According to (14) and (15), both the gains and the poles of the transfer functions and are dependant on the transconductances of transistors. Therefore, the transconduc-tances are important parameters and must be stabilized. The sta-bility of gm is achieved by using a constant-gm bias circuit [12], as shown in Fig. 7. With the parameters shown in Table I, the HSPICE simulation shows that the transconductance variations of in Fig. 7 can be kept within 2.3% and 2% with the four corners (FF, FS, SF, and SS) of device model parameters and

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Fig. 7. Circuit of constant-gm bias.

TABLE I

DIMENSIONS OFDEVICES INCONSTANT-GMBIASCIRCUIT AND

POLYPHASEFILTER

variations in the temperature between 0 and 80 , respectively. The performance of a one-stage polyphase filter that incorpo-rates the constant-gm bias circuit with MHz is veri-fied. The at 25 MHz can exceed dB and dB, respectively. Accordingly, the desired can be achieved under process and temperature variations.

As seen from (7) and (8), the is degraded if the gain and pole frequencies of and are not identical. Since the pole frequencies of and shown in (14) and (15) are identically determined by and , the pole frequencies mismatch can be avoided. The gain mismatch

between and can be reduced

to the balance between and . and

are current ratios and the mismatch can be kept small. To re-duce the mismatch of and , the layout of and can be put in common centroid. Moreover, minimum channel

Fig. 8. HSPICE simulated transfer curve and IRR of the 2.5-V four-stage CMOS polyphase filter.

length is not used in this design to further reduce the gain mis-match. In the passive RC polyphase filter, the gain mismatch depends on not only the matching in RC values and transcon-ductances of buffers in paths, but also parasitic capacitors of resisters. In comparison with the mismatch effects of cur-rent ratio and tansconductance in the proposed active polyphase filter, the will not be worse than the one in passive RC polyphase filter.

With the random variations among components, the one-stage polyphase filter ( MHz) biased with a constant-gm circuit is verified by 30-times of Monte Carlo simulations. Except pF, all other device dimensions are the same as the values listed in Table I. The variations of tran-sistor parameters (channel width), (channel length) and (threshold voltage) are randomly distributed according to the values provided by the corner parameters

of the MOS device model, such that m,

m, and .

The relative variations of capacitance and resistances are 10%. The results of the simulation show that the worst at 25 MHz still exceeds dB.

A wide bandwidth polyphase filter with an IRR of dB is realized in 0.25- m 1P5M CMOS technology with a power supply of 2.5 V. Four one-stage polyphase filters are cascaded in this design to expand the bandwidth and enhance the toler-ance of bandwidth variations. The capacitors in the four one-stage polyphase filters are 3.5, 5.5, 10, and 16 pF, respec-tively. The resultant rejected frequencies are 24.5, 15.5, 8.5, and 5.4 MHz, respectively. Fig. 8 plots the simulated transfer curves at positive and negative frequencies and the IRR of the designed polyphase filter. It is shown that the can exceed dB by the four-stage polyphase filter over the band-width MHz MHz. The total power consumption is 11 mW at a power supply of 2.5 V. The simulated common-mode-rejection ratio (CMRR) within the bandwidth in each one-stage polyphase filter is 41 dB.

HSPICE simulations are performed to verify the effects of process and temperature variations. The results in Fig. 9 show

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Fig. 9. HSPICE simulated IRR variations of the four-stage CMOS polyphase filter with four corners (FF, FS, SF, and SS) of MOS device models.

Fig. 10. Low-voltage version of LHF.

that the exceeds dB over the range of MHz MHz under the four corners of the MOS device models. As the temperature varies from 0 to 80 , an of dB can also be achieved within 4.75 to 27 MHz. Thus, the perfor-mance of the proposed polyphase filter can be well controlled as the process and temperature are varied.

B. 1-V Polyphase Filter

With the advantage of currents operation, the proposed active polyphase filters can be modified to operate at a low supplied voltage. Fig. 10 shows the low-voltage version of LHF where the transistor is connected in a folded structure. Therefore, the required power supply can be as low as the threshold voltage

of plus the drain–source voltage of . works as a current source, which provides a constant dc current to . Because of the high impedance at the drain of , the current , which is generated from the input voltage signal by , flows to and then mirrored to . The functions of other transistors are similar to those of the corresponding tran-sistors in Fig. 6(a). With a supplied voltage of 1-V and 0.25- m 1P5M CMOS technology, the transfer curves and the

of a low-voltage four-stage polyphase filter are shown in Fig. 11. Fig. 11 shows that an of dB can be achieved

Fig. 11. HSPICE simulated transfer curve andIRR of the low-voltage four-stage CMOS polyphase filter.

Fig. 12. Die micrograph of fabricated four-stage polyphase filter in 0.25-m CMOS technology.

Fig. 13. Measured IRR of fabricated four-stage polyphase filter in 0.25-m CMOS technology.

within the frequency range MHz MHz. The simulated CMRR within this bandwidth is 40 dB. The 1-V polyphase filter consumes 5.5 mW, which is only about 50% of the power con-sumption in the 2.5-V version.

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Fig. 14. Two-tone test forf = 19:5 MHz and f = 20:5 MHz.

IV. EXPERIMENTALRESULTS

Fig. 12 shows the die micrograph of a four-stage polyphase filter, which is designed and fabricated in 0.25- m 1P5M CMOS technology. The four-stage polyphase filter consumes 11 mW at a supplied voltage of 2.5 V and occupies a die area of 1162 813 m . All of the capacitors are implemented by metal-insulator-metal (MIM) capacitors.

For measurement purposes, on-chip test buffers are placed after the polyphase filter to analyze the output signals. In the measurement set-up, a splitter converts a single-ended signal into differential signals, which are then sent to a six-stage off-chip RC polyphase filter to generate the required input quadra-ture signals. The off-chip RC network can provide an IRR of more than dB in the frequency range MHz MHz. After the gain loss of the off-chip RC network has been compen-sated for, the measured voltage gain of the fabricated four-stage polyphase filter at 20 MHz is 6.6 dB. The measured is shown in Fig. 13, an IRR of dB can be achieved in the fre-quency range MHz MHz. A two-tone test is performed to measure spurious-free dynamic range (SFDR). As shown in Fig. 14, when the input signals are at 19.5 and 20.5 MHz, the dif-ferences between noise floor to fundamental and third-order in-termodulation signals are 72.2 and 21.5 dB, respectively. Thus, a 65 dB in-band SFDR can be achieved by the polyphase filter. Fig. 15 shows that the measured input third intercept point (IIP3)

Fig. 15. Measured IIP3 of fabricated four-stage polyphase filter in 0.25-m CMOS technology.

is 8 dBm. The measured CMRR is 41 dB and the input referred noise is 78.1 V, which includes the noise contributed by output buffers.

The performance comparison between the proposed polyphase filter and the passive RC polyphase filter [7] is given in Table II. As seen from Table II, the proposed polyphase filter has much lower average power dissipation per stage for the same power supply and higher passband gain while maintaining the same IRR per stage. In the passive RC

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TABLE II

COMPARISONBETWEENPROPOSEDPOLYPHASEFILTER ANDPASSIVERC

POLYPHASEFILTER[7]

polyphase filter, large power is needed in interstage buffers. In the proposed four-stage polyphase filter, the power dissipation can be reduced further to 1.375 mW/stage at 1-V power supply.

V. CONCLUSION

A wide-band and low-power active polyphase filter has been proposed and analyzed. The wide-band performance is achieved by simple CMOS single-stage filter circuit and directly cascaded multistage structure. Without inter-stage buffer, the power dissi-pation is kept low. The simulations have shown that by biasing with a constant-gm circuit, the variations in process and tem-perature are effectively reduced. Due to the advantage of cur-rent-mode operation, the proposed active polyphase filter has been successfully modified to fit the operation of 1-V power supply. The performance of the filter has been verified through measurement on the fabricated chip in 0.25- m 1P5M CMOS technology. The measured IRR of four-stage polyphase filter is higher than dB over the frequency range of MHz

MHz. The power consumption is 11 mW with 2.5-V power supply. It has been shown from measurement results that the proposed active polyphase filter is suitable in wireless commu-nication applications.

ACKNOWLEDGMENT

The authors would like to thank the Chip Implementation Center (CIC), National Science Council, Taiwan. R.O.C., for the fabrication of the testing chip.

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Chung-Yun Chou (S’01) was born in Miaoli,

Taiwan, R.O.C., in 1970. He received the B.S. degree in electrical engineering from the National Central University, Chung-li, Taiwan, in 1998. He is currently working toward the Ph.D. degree at the National Chiao-Tung University, Hsinchu, Taiwan.

His current research interests are in analog inte-grated circuits design and low-power radio-frequency integrated circuits design for wireless LAN systems.

Mr. Chou is a member of Phi Tau Phi.

Chung-Yu Wu (S’76–M’76–SM’96–F’98) was

born in 1950. He received the M.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, R.O.C., in 1976 and 1980, respectively.

Since 1980, he has served as a Consultant in the high-tech industry and research organizations and has built up strong research collaborations with high-tech industries. From 1980 to 1983, he was an Associate Professor at NCTU. From 1984 to 1986, he was a Vis-iting Associate Professor in the Department of Elec-trical Engineering, Portland State University, Portland, OR. Since 1987, he has been a Professor at NCTU. From 1991 to 1995, he was rotated to serve as the Director of the Division of Engineering and Applied Science on the National Science Council, Taiwan. From 1996 to 1998, he was honored as the Centen-nial Honorary Chair Professor, NCTU. In addition, he conducted postdoctoral research at UC Berkeley in summer of 2002. He has published more than 250 technical papers in international journals and conferences. His research inter-ests are nanoelectronics and very large-scale integration, including circuits and systems in low-power/low-voltage mixed-signal design, and systems, biochips, neural vision sensors, RF circuits, and CAD analysis. He also holds 19 patents, including nine U.S. patents.

Dr.Wu is a member of Eta Kappa Nu and Phi Tau Phi Honorary Scholastic So-cieties. He was a recipient of the IEEE Fellow Award in 1998 and the Third Mil-lennium Medal in 2000. In Taiwan, he received numerous research awards from the Ministry of Education, National Science Council, and professional founda-tions.