Low-Complexity All-Digital Sample Clock Dither for
OFDM Timing Recovery
You-Hsien Lin, Student Member, IEEE, and Terng-Yin Hsu
Abstract—Based on phase adjustment, this work investigates
a low-complexity all-digital sample clock dither (ADSCD) to perform coherent sampling for orthogonal frequency-division multiplexing (OFDM) timing recovery. To reduce complexity, only tri-state buffers are acquired to build a multiphase all-digital clock management (ADCM), which can generate more than 32 phases over gigahertz without phase-locked or delay-locked loops. Following divide-and-conquer search and triangulated approxi-mation, the phase adjustment is simple but efficient, such that four preambles are adequate to make analog-to-digital (A/D) sampling coherent. Performance evaluation indicates that the proposed ADSCD can tolerate 400-ppm clock offsets with 0 8 1 3-dB signal-to-noise ratio (SNR) losses at 8% PER in frequency-se-lective fading. Hence, this scheme involves a little overhead to ensure fast recovery and wide offset tolerance for OFDM packet transmissions.
Index Terms—Low complexity, multiphase clock, orthogonal
frequency-division multiplexing (OFDM), phase adjustment, timing recovery.
I. INTRODUCTION
D
IGITAL signal processing (DSP) can enhance wire-less access performance, in terms of error probability, data rate, and link reliability. For many wireless applica-tions, powerful standards have been presented to make packet transmissions be more robust and efficient, e.g., multi-band (MB)-orthogonal frequency-division multiplexing (OFDM) UWB, WiFi, WRAN and WiMAX. Timing recovery is one of the most important factors in obtaining a good signal-to-noise ratio (SNR) for wireless OFDM systems. Fixed sampling with an interpolation filter [1]–[4] is a well-developed method in which datums are sampled at Nyquist or higher rate. Inter-polation techniques [1]–[4] are usually employed to recover analog-to-digital (A/D) converters samples that the variable fractional-delay (VFD) filters are useful in designs. Then the Farrow structure with VFD filter becomes an efficient method, optimized by exploiting symmetries [5]. The other timing recovery involves adaptive sampling (synchronized sampling) to make A/D coherent. Since lower information loss corre-sponds to better performance, adaptive sampling (synchronized sampling) outperforms fixed sampling (non-synchronized sam-pling) [6]–[8]. The key of adaptive sampling is to adjust A/DManuscript received September 22, 2008; revised January 03, 2009; accepted February 25, 2009. First published August 04, 2009; current version published June 25, 2010. This work was conducted under “A plan to actively participate in international standard organizations for wireless communications” of the In-stitute for Information Industry, and supported by the National Science Council of Taiwan, ROC under Grant and NSC 97-2220-E-009-016.
The authors are with the Department of Computer Science, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: tyhsu@cs.nctu.edu.tw).
Digital Object Identifier 10.1109/TVLSI.2009.2019079
Fig. 1. Block diagram of non-PLL/DLL all-digital sample clock dither for OFDM timing recovery.
clock accurately, efficiently and stably. Several mixed-mode schemes [9]–[13] have been developed to control A/D sam-pling frequency. Instead of analog techniques, an all-digital phase-locked loop (ADPLL) with eight uniform phases [14] has been realized to reduce power dissipation and implementation costs of MB-OFDM UWB systems. Yet, the large number of multiphase of ADPLL is hard to implement over several hundred megahertz. Additionally, pilot-based timing recovery is difficult to use for initial acquisition in WiFi and UWB because OFDM pilots can only be obtained after successful synchronization [8].
This study deals with a low-complexity all-digital sample clock dither (ADSCD) implementation, which allows for fast recovery and provides wide offset tolerance in OFDM packet accesses, as shown in Fig. 1. Unlike other multiphase tech-niques, e.g., phase-locked loops (PLLs), delay-locked loops (DLLs), and analog circuits, the proposed mechanism is simple yet useful to ensure A/D coherent sampling. This mechanism is also well-suited to new specifications as discussed in IEEE 802.15.3c and IEEE 802.11 very high throughput working group (VHT WG).
The rest of this paper is organized as follows. Section II states the system description and problem statement. Section III de-scribes the low-complexity non-PLL/DLL ADSCD. To verify this work, both MATLABand software-defined radio (SDR) plat-forms are built. Section IV shows and discusses the results. Con-clusions are finally drawn in Section V.
II. SYSTEMASSUMPTIONS
A. System Descriptions
In most WiFi and UWB systems, each OFDM packet contains several short preambles for pre-fast Fourier transfer (FFT) syn-chronization and a few long preambles for channel estimation.
Fig. 2. Phase adjustment-based multiphase A/D sampling: preamble and datum versus clock phases.
Each OFDM (datum) symbol includes several frequency-do-main pilots, modulated by QPSK or BPSK, for post-FFT
syn-chronizations [8]. If is a short
pre-amble with samples, the transmitted signal is given by (1) where is a function of BPSK modulation and is the symbol period of short preambles. is filtered by (shaping filter) to be consistent with the spectrum mask, and up-converted to (carrier frequency). After RF down conver-sion, the received short preamble becomes
(2) where is an auto gain controller (AGC) compensated error; is the carrier frequency offset; is the frequency-se-lective fading response, and is the equivalent response of filters in receiver. After RF down conversion, all preambles and datums are sampled using one of clock phases, as shown in Fig. 2. The received short preamble is
and
(3) where represents additive white Gaussian noise (AWGN), is the delta function, and is the sampling error. The cross correlation [6]–[8], [15] can be obtained by
(4)
Fig. 3. Proposed timing detection in frequency-selective fading.
where , is a phase offset,
and is the overall response of fading channel
and filters. Because is a constant within each packet in indoor frequency-selective fading (time-invariant or WSSUS [6]–[8]), the window-based timing detection (TD) is proposed by
(5) where is the response of filters. Fig. 3 plots the characteristic curve of the proposed TD that a minimal sampling error almost corresponds with a maximum in frequency-selective fading.
B. Problem Statements
“Multiphase A/D clocking” is one of keys to make phase ad-justment as simple as possible. PLLs and DLLs are popular in implementations; however, most of them occasionally ex-hibit unduly serious phase transients, namely, hang-up phenom-enon [16]. It is also difficult for all-digital multiphase PLLs or DLLs to provide a lot of clock phases over gigahertz. Al-though most high-speed multiphase clocking can be built using analog techniques, the turnaround time is too long. Due to dif-ferent clock phases causing various timing errors, the coherent clock phase can be found via “step-by-step” scan per preamble
Fig. 4. Structure of the proposed2 -multiphase ADCM and its Hspice simu-lation of0 180 (16 phases), 1 GHz in a 90 nm in-house digital CMOS process.
in maximizing . Yet, this process increases cycles. Un-fortunately, most wireless systems do not have sufficient pream-bles. Hence, the objective of this study is to derive a simple and low-complexity multiphase mechanism, assuring fast and robust recovery without PLL, DLL, and analog circuits.
III. NON-PLL/DLL ADSCD A. Multiphase Clocking
PLL and DLL techniques are not used but delay interpolators [17] with tri-state buffers are built to produce all-digital multi-phase clocking with controllability, as plotted in Fig. 4, in which the proposed ADCM is composed of a four-phase gener-ator, two banks of tri-state buffers and a Schmitt trigger-based driver. Two groups of tri-state buffers with -order control are connected with wire-or logic ( phases are obtained), namely, Bank_E and Bank_L, where the control words of Bank_E and Bank_L are complementary. Because two groups of tri-state buffers cannot skew more than 1/4 cycle, a 2 system clock is applied to generate four 1 clocks, divided by D-type flip flop, with 0 , 90 , 180 , and 270 skews. As a result, the input of Bank_L is skewed referring to Bank_E, and two 4-to-1 multiplexers are adopted to yield all needed 1/4-cycle combinations of four 0 , 90 , 180 , and 270 skews. For instance, if Bank_E is entirely active (all tri-state buffers of Bank_L are OFF), the input current flows via Bank_E to output (without any skew). On the other hand, the output
Fig. 5. Phase adjustment-based multiphase A/D sampling—lock phases versus timing detection.
current is all supported by Bank_L (output with 90 skew), if Bank_E is entirely inactive. Half of the tri-state buffers of Bank_E and Bank_L are enabled, and then the output current is combined by the two banks, being 45 skew. Based on various settings of buffers to change current balance, a phase with skews can be performed. The three-stage deriver with 1 , 5 , and 16 driving capabilities is a key of ADCM because the current summation of two delay banks may create glitches. To eliminate glitches, a Schmitt trigger buffer is applied at the 1st stage to stabilize clock transitions and both second and third stages to enhance the driving capability. Hence, a -multiphase ADCM with full-cycle controllability is realized by cascading the above modules. Although the disadvantage of using such mechanism is a nonuniform skew of clock phases (caused by rise time fall time), it is easy to produce multi-phase over gigahertz using an in-house digital cell library. The simulations suggest that 32 nonuniform phases are sufficient in OFDM systems with 64 QAM. Fig. 4 also displays the Hspice simulation of 32-multiphase clocking, up to 1 GHz, in a 90 nm in-house digital CMOS process. The power dissipation is 1.67 W at 40 MHz and 1.0 V supply voltage. This result is applied to model ADCM in simulations and measurements.
B. Phase Adjustment
Following Tau-Dither tracking loop [15] and divide-and- con-quer search [18], each sample of preamble (datum) is divided into sections and utilize an -phase clock ( ) to con-trol A/D sampling per symbol, reducing errors via time sharing. The sampling error of the th phase equals
(6) In Fig. 5, the first step is to adjust the A/D sampling clock with M/L-phase changes per preamble. Then there are short pream-bles sampled by the
and phases, respectively. Both maximum and second of can be obtained after sorting, namely, coarse search—an addressing region of coherent clock phases with large is found. Substituting (6) into (5), the candidate addresses of coherent
(9) This simple method measures only “ ” preambles to adjust A/D clock phases coherently. With large , additional pream-bles are required; with large , high quality of A/D coherent sampling is achieved. Thus, and must reach a balance be-tween cycle count and quality. For 32 phases ( ), 120 per section ( ) is a good choice—then only four preambles are used. During datums, continuous tracking of OFDM pilots will obtain the next coherent clock phase with maxi-mizing via maximum correlation methods [7].
C. Hardware Architecture
Fig. 1 shows the architectures of the proposed non-PLL/DLL ADSCD, where four functional modules are derived: 1) a dis-tance-based acquisition for searching a good clock phase to make A/D sampling coherent; 2) a pilot-based tracking for mea-suring the sampling errors of OFDM pilots to retain A/D sam-pling coherently; 3) a phase CTRL for generating the phase ad-dresses of ADCM; and 4) an ADCM for realizing multiphase clocking within acceptable complexity. In Fig. 6, there are three major blocks of the phase adjustment: 1) four registers to store timing detection; 2) a sorter to search a maximum and a second; 3) an address interpolation with triangulation method to enhance addressing accuracy. Four key components of the phase CTRL
to begin the search procedure where the first preamble is sam-pled using the first phase; the second preamble is samsam-pled using the th phase; and the third preamble is sampled using the th phase. Their are measured and stored in reg-isters. A sorter is used to find the “Max” and “Second” of the first, th and th phases to decide the ad-dressing region of coherent clock phases. Based on and
, the new phase of is decided and
the direction of clock offset is obtained. With , and , a triangulation-based address interpolator is adopted to en-hance accuracy. During datums, the correlation-based tracking uses OFDM pilots to keep the A/D sampling coherent. of the first OFDM pilot is stored as a reference, and of remainder OFDM pilots is then continuously measured and the reference is subtracted therefrom. The A/D clock phase must be adjusted to retain coherent sampling if the new is smaller than the reference; the phase addressing of A/D clock does not need to change if the new exceeds the reference. D. Implementation and Complexity
Both hardware-description language (HDL) and synthesis tool are sufficient to implement the modules of sorter, address interpolator, phase controller and pilot-based tracking. The crit-ical part is the layout of the proposed 32-phase ADCM whose issues and problems are as follows. 1) The input and output buses of tri-state buffers must be balanced to avoid additional skews. So the metal layer of such buses must be fixed (can not change layers) because the resistances of different VIAs and metals are easy to induce an extra delay in layouts. For
(7a) (7b) for for for others (8)
Fig. 6. Architecture (L = 3) of phase adjustment in non-PLL/DLL ADSCD for OFDM timing recovery.
an example of an in-house 90-nm 1P9M CMOS technology, VIA_1 is 31.8 and VIA_2 is 28.6 , which produces serious skews at 1.0 V supply voltage. 2) Considering power bounce, it affects the phase jitter of ADCM. In order to stabilize the power bounce, the placement of ADCM layout must be close to the power lines and power PADs to obtain sufficient current in operations.
The hardware complexities of the proposed ADSCD are: the gate count of a sorter is 700; an address interpolator needs about 1250 gates; the timing detector is 780 gates; the phase CTRL requires 900 gates. Because the pilot-based tracking needs only “addition” and “subtraction”, the main cost is the register that 420 gates include in implementations (less than 100 bits; using 8-bit A/Ds). For 32-multiphase ADCM, six tri-state buffers (total 80 gates), two D-type flip flops (10 gates per each), two 4-to-1 multiplexes (16 gates per each), two deriving buffers (total 18 gates) and a Schmitt trigger buffer (30 gates) are just used. The total gate count of 32-multiphase ADCM is 180. Because the computation complexities of the pilot-based tracking without multiplication and ADCM without digital control oscillator (DCO), voltage control oscillator (VCO), PLL and DLL are constant; the computation com-plexity of address interpolator with division and multiplication is . The overall computation complexity is dominated by
divide-and-conquer search, being [18]. Hence,
this multiphase mechanism is less complex than multiphase ADPLL [14] and interpolation filters [19]–[21].
IV. PERFORMANCEEVALUATION
Two platforms are constructed to evaluate this multiphase mechanism; one is MATLABsimulation, and the other one is software-defined radio (SDR) platform. MATLAB simulations include AWGN, frequency-selective (multipath) fading, carrier frequency offset (CFO), clock offset, path loss, and circuit noises. Circuit noises in the proposed clock dither are: 1) A/D random errors and 2) phase jitter of ADCM. Monte Carlo is applied to generate the phase jitter with uniform distribution, ranging of clock period (A/D sample clock). The nonuni-form behavior of the proposed ADCM is built via 128 over sample. After down sample to 1 , the jitter effect of A/D clock is then created using an interpolator. The required packet-error
Fig. 7. Offset tolerance with circuit noises, 25-dB path loss, 50-ppm CFO, and 50-ns RMS delay spreading: (a) 16 QAM; (b) 64 QAM.
rate (PER) is 8% under 8-bit A/Ds, 256-step non-ideal AGC with a dynamic range of 70 dB, a packet length of 1024 byte, IEEE frequency-selective fading with an RMS delay spread of 50 ns, a maximum path loss of 65 dB and a CFO of 50 ppm. In Fig. 7(a) and (b), the offset tolerance with various SNR and modulations can be as high as 400 ppm, much larger than the 25 ppm in most wireless standards, in that the tracking error of adaptive sampling involves less distortion than the filtering losses associated with interpolation. The SNR losses are about 0.8 dB of 16 QAM and 1.3 dB of 64 QAM compared with perfect synchronization. Table I summarizes the features with related works [9], [10], [14], and [19]–[21].
RF signals are linked with MATLABand FPGA to verify the proposed multiphase mechanism. Two XilinxDSP Develop-ment Kits with on-board 14-bit A/Ds, 14-bit digital-to-analog (D/A) converters and 2-million-gate field programmable gate array (FPGA, Xilinx Virtex-II) are connected with in-house
Fig. 8. SDR platform and the measurements of 64-QAM constellations with circuit noises and a clock offset of+400 ppm before and after recovery.
TABLE II
SUMMARY OF THEMEASUREDEVM
2.4-GHz RF modules at 20-MHz bandwidth to transmit and re-ceive real OFDM packets, as displayed in Fig. 8. The proposed method is also mapped onto the FPGA. Yet, the maximal clock rate of on-board 14-bit A/Ds in XilinxDSP Development Kits is 105 MHz – only over sample with uniform phases is available, being different to the real. Thus, an interpolator is uti-lized to simulate additional sample errors of nonuniform sample
phase and to model the phase jitter of ADCM. Before mea-surements, the natural clock offset between TX and RX must be calibrated and precompensated. TX packets with man-made clock offsets are first generated by MATLABand transferred by
14-bit D/A. The packets are then transmitted using RF module (MATLAB to RF through D/As). After RF down conversion, wireless signals are fed into 14-bit A/Ds and transferred to field-programmable gate array (FPGA) and PC via USB (RF to FPGA and MATLAB through A/Ds), where 32 over sample with such interpolation realizes phase-adjustment behavior in receivers. Fig. 8 also displays 64-QAM constellations before and after recovery. The measured EVM with/without circuit noises are listed in Table II. They demonstrate that the proposed ADSCD functions in certain wireless situations.
V. CONCLUSION
For OFDM timing synchronization, a low-complexity ADSCD is investigated to offer fast recovery and wide tol-erance. The proposed multiphase clocking is constructed by tri-state buffers and has low complexity; it can produce more than 32 phases over gigahertz without any multiphase PLL, DLL, or analog circuit. The A/D phase adjustment is simple but efficient to perform coherent sampling within four preambles. At 8% PER and up to ppm clock offsets, the SNR loss is only dB in frequency-selective fading. Hence, this multiphase mechanism produces promising results for WiFi, UWB and new specifications discussed in IEEE 802.15.3c and IEEE 802.11 VHT WG.
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You-Hsien Lin (S’07) received the M.S. degree in
computer science and information engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2004, where he is currently pursuing the Ph.D. degree in computer science.
He has been a Lecturer with the Department of Electronics Engineering, Ming Hsin University of Science and Technology, since 2006. His current research interests include synchronization and signal processing for wireless communication, multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) systems, and associated VLSI architectures.
Terng-Yin Hsu received the B.S. and M.S. degrees
from Feng Chia University, Taichung, Taiwan, in 1993 and 1995, respectively, and the Ph.D. degree from the National Chiao-Tung University, Hsinchu, Taiwan, in 1999, all in electronic engineering.
In 2003, he joined the Department of Computer Science, National Chiao-Tung University, where he is currently an Assistant Professor. His research interests mainly include VLSI architectures, wire-less communications, multi-spec transmissions, high-speed networking, analog-like digital circuits, system-on-chip (SoC) design technology, and related ASIC designs.
