IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, SEPTEMBER 2008 1053
Method for Extracting Gate-Voltage-Dependent
Source Injection Resistance of Modified
Schottky Barrier (MSB) MOSFETs
Bing-Yue Tsui, Senior Member, IEEE, Chi-Pei Lu, Student Member, IEEE, and Hsiao-Han Liu
Abstract—The modified Schottky barrier (MSB) MOSFET with
low-resistance metal source/drain and good short-channel effect immunity is one of the promising nanoscale device structures. In this letter, a modified external load resistance method was proposed to extract the bias-dependent source injection resistance of the MSB MOSFET for the first time. The effect of the thermal budget of the MSB process on the source injection resistance is reported. The injection resistance is exponentially proportional to (VGS− Vth− 0.5VDS) and would be close to the source/drain resistance of conventional MOSFETs at high gate bias. This work provides a good method to directly evaluate the efficiency of the MSB junction.
Index Terms—Carrier injection, implantation-to-silicide (ITS),
modified Schottky barrier (MSB), multigate FET (MuGFET).
I. INTRODUCTION
T
HE SCHOTTKY barrier (SB) MOSFET is one of the candidates for future nanoscale devices because of its easy processing, ultrashallow junction, and low source/drain (S/D) external resistance compared to the conventional p-n junction MOSFETs [1]–[5]. Recently, modified SB (MSB) MOSFETs have been proposed to improve the driving cur-rent and reserve the advantages of SB MOSFETs. The MSB junction is a Schottky junction with a very thin but high doping concentration layer located at silicide/Si-channel inter-face, which not only drastically improves driving capability by reducing and thinning the SB at source junction but also can significantly suppress the OFF-state leakage due to the thick SB at the drain junction. The MSB junction can be accom-plished by either the implantation-to-silicide (ITS) method or the dopant segregation method [6], [7]. Several researches have been devoted to evaluate the efficiency of the MSB junction. Zhang et al. reported that the effective Schottky barrier height can be reduced to about 0.1 eV at high gate bias [8]. Kinoshita et al. reported the carrier injection velocityenhance-Manuscript received March 7, 2008; revised June 8, 2008. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC-95-2221-E-009-302-MY3. The review of this letter was arranged by Editor X. Zhou.
The authors are with the Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]).
Digital Object Identifier 10.1109/LED.2008.2001478
ment associated with the velocity overshoot [9]. It has been also reported that the current transport mechanism of SB and MSB MOSFETs may change from thermionic emission and tunneling to drift diffusion as the gate bias increases [10]. The gate bias for transport mechanism change decreases with the increase of the thermal budget for MSB junction formation. However, the source injection resistance and its gate bias depen-dence have not been reported. In this work, a modified external loading method is proposed to extract the bias-dependent S/D resistance. The bias-dependent source injection resistance of MSB MOSFETs provides a good indicator to evaluate the efficiency of the MSB junction and would be useful for device and circuit simulation.
II. DEVICEFABRICATION
Fully depleted n-channel SOI MSB MOSFETs fabricated by the ITS technique are used in this work. The process flow of an MSB MOSFET has been previously described in detail [11]. Therefore, we list some important process and structure parameters here. The thicknesses of the Si active layer and buried oxide layer were 40 and 150 nm, respectively. A thick SiO2hard mask layer was deposited on the Si layer so that only
sidewall channels could be conducted. A 3-nm-thick SiO2was
thermally grown as the gate dielectric followed by a 150-nm-thick poly-Si film deposition. The poly-Si gate was doped by P+31 ion implantation at 40 keV to a dose of 5× 1015 cm−2 followed by a rapid thermal activation at 1025 ◦C for 10 s. Then, a SiO2 (10 nm)/Si3N4 (20 nm) composite spacer was
formed. The S/D region was completely converted into NiSi by a two-step annealing silicidation process. To form the MSB S/D junction, P+31ions were implanted into the nickel silicide (ITS) at 20 keV to a dose of 5× 1015 cm−2 followed by a post-ITS annealing step at 600◦C for 30 min or 30 s. During this annealing step, phosphorus ions diffused out of the silicide and piled up at the Si/silicide interface to form the MSB junction [11]. For the reference devices, phosphorus ions were implanted into the S/D region at 10 keV to a dose of 5× 1015 cm−2 followed by a rapid thermal activation at 1025◦C for 20 s before the Ni-salicide process. The silicide thickness is about 25 nm.
Fig. 1 shows the typical transfer characteristics of an MSB MOSFET with W/L = 80 nm/5 µm biasing at VDS= 0.05 V
and operating at different temperatures. The inset shows the
1054 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, SEPTEMBER 2008
Fig. 1. Typical transfer characteristics of an MSB MOSFET with W/L = 80 nm/5 µm biasing at VDS= 0.05 V and operating at a different device temperature. The inset shows the device structure. The reversal of tempera-ture dependence at VGS= 1.35 V indicates the change of current transport mechanism.
Fig. 2. −RL0versus 1/(VGS− VTH− 0.5VDS) plot of the conventional MOSFET. The insets show the circuit diagram of the external loading method and the device structure. The VDSis 0.05 V.
schematic device structure. TheON-state current increases with temperature, increasing at low VGS. While at high VGS, the
temperature dependence is reversed, and the intersecting point occurs at about VGS= 1.35 V. This intersection indicates that
the ON current of the MSB MOSFET is dominated by a thermionic emission mechanism or a tunneling mechanism at low gate bias [10].
III. MODIFIEDEXTERNALLOADINGMETHOD
The external loading method was proposed to extract the S/D resistance of the MOSFET by Hsu [12]. The benefit of this method is that only one device is measured, and the extracted result is exactly the S/D resistance of the measured device. The inset in Fig. 2 shows the circuit diagram of this method. An external load resistor with a suitable range of impedance is connected to the source terminal. The total resistance of the circuit is composed of external load resistance (RL), source
resistance (RS), drain resistance (RD), and channel resistance,
Fig. 3. −RL0versus 1/(VGS− VTH− 0.5VDS) plot of the MSB MOSFET with W/L = 80 nm/5 µm obtained by the modified external loading method. The VDSis 0.05 V, and the post-ITS annealing time is 30 min.
where RS and RD depend on the properties of the MSB
junction. The channel current (IDS) of the MOSFET operating
at a linear region is given by
IDS= W LµCox VGS − VTH− 1 2V DS VDS = K [VGS− IDS(RS+ RL)− VTH] −1 2[VDS− IDS(RS+ RD+ RL)] × [VDS− IDS(RS+ RD+ RL)]
where K = (W/L)µCox, W is the channel width, L is the
channel length, µ is carrier mobility, and Cox is gate
capaci-tance. This equation models the intrinsic channel property and is independent of the S/D junction. After some manipulations, this equation becomes
1 IDS = RT+ RL VDS + 1 K VGS− VTH− 12VDS VDS (1)
where RT= RS+ RD, and RT represents the total external
resistance of this MOSFET. Then, by plotting 1/IDSversus RL
with VGSas a parameter, the x-axis intersection RL0could be
expressed as −RL0(VGS) = RT+ K−1 VGS− VTH− 1 2VDS −1 . (2)
By plotting−RL0versus 1/(VGS− VTH− 0.5VDS), the y-axis
intersection gives RT.
The −RL0 versus 1/(VGS− VTH− 0.5VDS) plot of the
MOSFET with a conventional S/D junction is shown in Fig. 2, where the VDS is 0.05 V. The good linearity as predicted by
(2) confirms that the external loading method can be applied to SOI devices well. However, Fig. 3 shows that when using
TSUI et al.: EXTRACTING GATE-VOLTAGE-DEPENDENT SOURCE INJECTION RESISTANCE OF MSB MOSFETs 1055
Fig. 4. Extracted RTas a function of the (VGS− VTH− 0.5VDS) of the MSB MOSFET with W/L = 80 nm/5 µm. The VDSis 0.05 V.
this method to the MSB MOSFET, the nonlinear−RL0 versus
1/(VGS− VTH− 0.5VDS) plot deviates from (1). This
differ-ence arises from that the RTof the MSB MOSFET is dependent
on the bias condition, which conflicts with the basic assumption of the external loading method.
To solve this problem, we assume that RTcan be treated as
a constant in a small ∆VGrange (VGX± ∆VG/2). The x-axis
intersection of the−RL0versus 1/(VGS− VTH− 0.5VDS) plot
extracted at VGS= VGX− ∆VG/2, VGX, and VGX+ ∆VG/2
could be explained as the RTat VGX. Consequently, the bias
dependence of RTcan be obtained by repeating this procedure.
Fig. 4 shows the extracted RT of the MSB MOSFET with
30-min and 30-s post-ITS annealing as a function of (VGS−
VTH− 0.5VDS), where the VDS is 0.05 V. It is observed that
the RT is exponentially proportional to the bias condition of
(VGS− VTH− 0.5VDS). This is reasonable because the S/D
resistance is dominated by the effective SB height at the source side, and the effective SB height is linearly proportional to VGS
in the measured VGS range [8]. The RT of the device with
30-min post-ITS annealing is much lower than that with 30-sec post-ITS annealing. This result indicates that a sufficient ther-mal budget is required to form an efficient MSB junction. Extrapolating RT to (VGS− VTH− 0.5VDS) = 0.5 V, RT is
1.17 KΩ−µm and is very close to that of the conventional MOSFET. It should be noted that as the device is biased at the
ON state, the effect of MSB at the drain side is much smaller than the MSB at the source side. Therefore, the decrease of
RTis mainly attributed to the decrease of the source injection
resistance.
IV. CONCLUSION
In this letter, a modified external load resistance method has been proposed to extract the bias-dependent source injection resistance of the MSB MOSFET. It is observed that the source injection resistance is exponentially proportional to (VGS−
VTH− 0.5VDS) and the S/D resistance of the MSB MOSFET
would be close to that of the conventional MOSFET at moder-ate high gmoder-ate bias. Without a sufficient post-ITS thermal budget, the source injection resistance cannot be effectively suppressed at reasonable VGS. This work provides a good method to
directly evaluate the efficiency of the MSB junction. ACKNOWLEDGMENT
The devices were fabricated at the Nano Facility Center of National Chiao Tung University and the National Nano Device Laboratory.
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