擁有寬捕獲範圍之全數位鎖相迴路電路設計

國 立 交 通 大 學

電信工程研究所

碩 士 論 文

擁有寬捕獲範圍之全數位

鎖相迴路電路設計

A Wide Capture Range PLL based on

All-Digital Design

研 究 生：謝進益

指導教授：高銘盛 教授

擁有寬捕獲範圍之全數位鎖相迴路電路設計

A Wide Capture Range PLL based on All-Digital Design

研 究 生：謝進益 Student：Chin-Yi Hsieh

指導教授：高銘盛 Advisor：Ming-Seng Kao

國 立 交 通 大 學

電信工程研究所

碩 士 論 文

Submitted to Institute of Communication Engineering College of Electrical and Computer Engineering

National Chiao Tung University in partial Fulfillment of the Requirements

for the Degree of Master

in

Communication Engineering

July 2011

Hsinchu, Taiwan, Republic of China

擁有寬

擁有寬

擁有寬

擁有寬捕獲範圍之全數位

捕獲範圍之全數位

捕獲範圍之全數位鎖相迴路

捕獲範圍之全數位

鎖相迴路

鎖相迴路

鎖相迴路

電路

電路

電路

電路設計

設計

設計

設計

學生:謝進益 指導教授:高銘盛 教授

國立交通大學

電信工程研究所

摘要

摘要

摘要

摘要

本論文設計一個擁有極寬捕捉頻帶的全數位鎖相迴路，其鎖定頻率範圍從 1kHz 到

1MHz。此鎖相迴路的最高頻率與最低頻率的倍率為 1000，並且使用者不需知道輸入頻率

的範圍，只要工作頻率位於此區間的應用，皆可使用此電路。為了能夠適用於充滿雜訊的

環境，所設計的電路擁有良好的抗雜訊能力，即使在 SNR=0dB 的惡劣環境中，它依然可以

正常的運作。

在設計時，我們著重於三個效能參數: 頻率鎖定的正確率、鎖定效率與抗頻率漂移能

力。為了能在各個面向都有良好的表現，我們設計三種不同的工作模式及對應的演算法，

其中包含捕獲模式、追蹤模式與相位修正模式，並且在實際電路中選擇使用雙迴路的方

式，以完成一個全數位雙迴路鎖相電路。最後，我們利用硬體描述語言實現此鎖相迴路，

以驗證其可行性。

A Wide Capture Range PLL based on

All-Digital Design

Student: Chin-Yi Hsieh Advisor: Prof. Ming-Seng Kao

Institute of Communication Engineering

National Chaio Tung University

Abstract

In this thesis we design an all-digital phase-locked loop (PLL) with ultra-wide capture range

which spans from 1kHz to 1MHz. The ratio of the highest frequency to the lowest frequency is

1000 and there is no need for prior information of the input frequency. With this PLL, all

applications whose working frequency is within this frequency range could use it to implement

the corresponding system. Also, for applying it in noisy environment, the PLL is asked to have

good noise immunity. It is designed to work efficiently when SNR=0dB.

On designing this PLL, we focus on three aspects: the frequency locked rate, the lock

efficiency and the capability of anti-frequency drift. For good efficiency in every aspect within

wide capture range under noisy environment, we design three different states which include the

acquisition state, the tracking state and the phase-fixing state. Moreover, we introduce the

dual-loop system to further improve the performance. Finally, to verify the feasibility of our approach,

we implement this PLL by Hardware Description Language based on all-digital design.

誌

誌

誌

誌謝

謝

謝

謝

當我需要寫到個段落時，也代表著我的交大生涯已在開始倒數，謹以此篇文章以表兩

年來給予我幫助的人獻上深深的敬意。

首先在我研究所期間影響最深的當屬我的指導教授高銘盛老師，除了專門學問之外，

老師給予我最大的學習就是何謂研究的態度，或許在未來我所扮演的角色會變，研究的學

問也會不斷的更新，但是這份學習精神卻是不容遺忘的。此外還有多虧兩位大學長，兩位

中學長和兩位小學弟，讓我兩年來在研究上不至於孤軍奮鬥，也充實我碩士生活的回憶。

最後當然也要感謝我的家人父母，讓我可以在這段時間安心的做好學生的本分，以本身的

辛勞來換取我學習的資源，就是這份支持才足以支撐我在求學期間所遭遇到的總總挫折與

困難，讓我最後能成功的獲得交大碩士的肯定，謝謝你們。

Contents

Abstract i

Acknowledgement iii

Contents iv

List of Tables vii

List of Figures viii

1 Introduction 1

1.1 PLL Overview ……….…………...……….……...1

1.1.1 History and Application ……….…………...………….………1

1.1.2 All-Digital Phase-Locked Loop ……….……….……...2

1.2 Research Motivation ……….….………2

1.2.1 Motivations and Purpose of Research……….……...……... 2

1.2.2 Research Approaches ……….……….………...………4

1.3 Thesis Organization ……….………...……...4

2 Phase-Locked Loop Basics 5

2.1 Linear Model of PLL ……….5

2.1.1 Phase Detector Characteristics ……….………..6

2.1.2 VCO Characteristics ………..6

2.1.3 Frequency Response of Linear PLL Model ………...7

2.1.4 Loop Filter Characteristics ……….………9

2.2.1 Analog PLL ……….………….12

2.2.2 Digital PLL ……….………..13

2.2.3 All-Digital PLL ……….……...15

2.3 An ADPLL Circuit Model ……….……...16

2.3.1 Phase Frequency Detector ……….……...17

2.3.2 Time to Digital Converter ………...……….18

2.3.3 Digital Integrator ……….…….………19 2.3.4 Digital-Controlled Oscillator ………...20 2.4 Design Challenges ……….……...20 3 System Architecture 23 3.1 Acquisition State ……….……….………23 3.2 Tracking State ………..30 3.3 Phase-Fixing State ……….…...33 3.4 Noise Problem ……….….36 3.4.1 Noise Effect ……….….36 3.4.2 Conversion of Noise ……….…38

3.4.3 Improvement in Acquisition State ………....44

3.4.4 Improvement in Tracking State ………. ………..45

3.4.5 Improvement in Phase-Fixing State ……….………47

3.5 Summary ……….………48

3.6 Dual-Loop PLL System ………...49

3.6.1 The Primary Loop and the Secondary Loop ……….………...50

3.6.2 Improvement of Dual-Loop System ………52

4 System Implementation by Digital Hardware 55

4.1.1 Phase Frequency Detector ……….………...56

4.1.2 Time to Digital Converter ……….………...57

4.1.3 Digital Loop Filter ………...58

4.1.4 Digital-Controlled Oscillator ………...60

4.1.5 State Control Unit ………62

4.1.6 Divider Control Unit ……….………...62

5 Simulation Results 64

5.1 Frequency Locked Rate ………...64

5.2 Lock Efficiency ……….………...67

5.3 Capability of Anti-Frequency Draft ……….………72

6 Conclusions 75

List of Tables

1.1 Performance parameters about several PLL systems ……….………3 3.1 Trigger times for several m ………..…………28 3.2 Decision rule of band change ……….………..28 3.3 NTrefand R∆f by the end of acquisition state with different noise environments ……….45

5.1 The reference period required for different cases in single-loop system ……….70 5.2 The reference period required for different cases in dual-loop system ……...………….71

List of Figures

2.1 The general function block of PLL ……….………...5

2.2 Phase detector characteristic ……….………...…………...6

2.3 Voltage-controlled oscillator characteristic ………..………..7

2.4 Linear model with PD and VCO ……….………...8

2.5 The AC model with PD and VCO ……….………....8

2.6 Frequency response and bandwidth of linear PLL model ………….………....9

2.7 A RRC low pass filter ………..10

2.8 Frequency response of RRC low pass filter ……….………10

2.9 Frequency response and bandwidth of complete linear PLL model ………….………...11

2.10 The complete linear PLL model ……….………..11

2.11 The multiplier PD characteristic ………..12

2.12 PI filter circuit ……….……….13

2.13 Block structure diagram of DPLL ……….………...13

2.14 (a) Two-state PFD structure (b) three-state structure ……….……...14

2.15 PFD characteristic of (a) two-state PFD (b) three-state PFD ……….………..14

2.16 Charge pump structure ……….………15

2.17 Function block diagram of ADPLL ……….……….16

2.18 An ADPLL model ………17

2.19 The improved structure of three-state PFD ……….……….17

2.20 Timing diagram of new three-state PFD ……….……….18

2.22 Timing diagram of TDC ……….………..18

2.23 Digital integrator structure ……….………..19

2.24 DCO constituted by parallel tri-state inverter ……….……….20

2.25 A series wrong judgment caused by an impulse ………..21

3.1 Two cases with large frequency difference ……….……….24

3.2 The trigger positions ………24

3.3 The divided bands ……….………...25

3.4 (a) Boundary in unit of period (b) boundary in unit of frequency ……….…………...25

3.5 Relation between triggers and phase differences ……….………26

3.6 (a) Use quadruple DCO frequency to count the phase difference (b) phase difference level ………..…………29

3.7 Phase difference converges to the same level ……….………….30

3.8 The superfluous behavior of DCO frequency ……….………….31

3.9 Phase difference converges to the same level N tines ……….………….33

3.10 Constant phase difference ……….………...33

3.11 The process of fixing phase ……….35

3.12 A lock process example ……….……...36

3.13 Error phase and error trigger ……….……...37

3.14 Noise effect for different signals ……….…….38

3.15 (a) Adjacent changes appeared (b) the separate change ……….…..38

3.16 Cascade approach to repair consecutive points ……….…...39

3.17 Observing more points to repair consecutive points ……….…...39

3.18 Comparison between two approaches of repairing two consecutive points ………40

3.19 (a) Wrong repairment with correct points (b) phase resolution problem ………….……40

3.20 Wrong repairment with multiple points approach ……….…...41

3.22 The error probability and ratio for repairing different points ………..42

3.23 Weak repair capability in 5kHz reference frequency ……….…..42

3.24 The performance comparison between repairing 5 points and accumulator approach ……….…..44

3.25 Phase difference detection with SNR=0dB in the acquisition state ……….……45

3.26 Phase difference detection with SNR=0dB in the tracking state ……….45

3.27 The phase difference leads to the oscillating DCO code ……….……46

3.28 Phase difference detection with averaging (a) two points (b) four points (c) eight points ……….…...48

3.29 Phase difference detection with SNR=0dB in the phase-fixing state ……….….47

3.30 The accumulator technique against noise effect in phase-fixing state ……….…47

3.31 Block diagram of dual-loop system ……….…50

3.32 Frequency variation phenomenon on DCO code of (a) original system (b) the primary loop of dual system (c) the secondary loop of dual system ………...51

3.33 Two inefficient processes on selecting appropriate center frequency ……….….52

3.34 The efficient hopping process of dual center frequencies ………....53

4.1 The architecture of the dual-loop PLL system ………..………...55

4.2 The noise treatment of PFD ………56

4.3 Phase frequency detection of PFD ……….………..57

4.4 Structure of Time to Digital Converter ………58

4.5 Overview of Digital Loop Filter structure ………...59

4.6 Structure of several integrators (a) Integrator 1 and Integrator 2 (b) Integrator 3 (c) Integrator 4 (d) Integrator 5 ………...………..………59

4.7 Structure of Digital-Controlled Oscillator ………...60

4.8 DCO characteristic on (a) linear scale (b) logarithmic scale ………...61

4.10 Overview of Divider Control Unit ……….………..63 5.1 Locked rate of single-loop system in (a) 100kHz-1MHz (b) 10kHz-100kHz (c) 1kHz-10kHz ……….…………..……..65 5.2 Locked rate of dual-loop system in (a) 100kHz-1MHz (b) 10kHz-100kHz (c) 1kHz-10kHz ……….………..……..66 5.3 The reference periods required in the acquisition stat for 10kHz-100kHz ………….….67 5.4 The reference periods required in the tracking stat for 10kHz-100kHz ……….….68 5.5 The reference periods required in the phase-fixing stat for 10kHz-100kHz ……….…...69 5.6 The total reference periods required for 10kHz-100kHz ……….……69 5.7 (a)The required periods and (b) locked rate for reference frequency drift in single-loop system ………...72 5.8 (a)The required periods and (b) locked rate for reference frequency drift in dual-loop system ………..………..………...73

Chapter 1

Introduction

1.1 PLL Overview

The phase-locked loop (PLL) is a very critical component in modern electronic circuits [1]. It is able to generate a stable output signal whose phase and frequency are the same as those of the input. The PLL is also a feedback system, whose output is directly connected to the input. Therefore the system will adjust its output signal constantly until the phase/frequency difference between input and output is near to zero.

1.1.1 History and Application

The history of PLL can be traced back to 80 years ago. Originally it had been used for the synchronous detection of radio in the 1930s. During the 1950s, it was used for television broadcasting and satellite tracking. Because of the high cost, the application of PLL was rather limited at that time. In recent years, thanks to the progress of the manufacturing technology of VLSI and the system on a chip (SoC) design, the scope of application is increased significantly. Until now, the role of PLL in system design is more and more important, which has become a versatile multi-function integrated circuit after the operational amplifier [2].

The phase-locked loop is widely used in the televisions, telecommunications, computers, and other electronic applications [3], [4]. It is able to generate or synthesize stable frequencies to select broadcasting stations or channels, synchronize the carrier frequency from noisy channel to demodulate the communication signals coherently, track the unknown frequencies

in wireless system, or recover clock pulses in digital logics. Therefore, the wide application range of PLL leads to continuous research on PLL circuits.

1.1.2 All-Digital Phase-Locked Loop

Although the PLL is applied ubiquitously, there are still some problems with integration of traditional PLL at the current trend. In the traditional designs, most of them use analog components to build the PLL. That is, all the circuits are implemented with the resistances, capacitances, or inductances. But the area of these passive components in IC manufacturing is relatively large and the exact values of them are not easy to be grasped. Moreover, in today’s single-chip system, merging analog circuits and digital logic on the same chip is inevitable, but it may cause many electrical problems such as noise interference, signal mask, power supply stability, etc [5], [6]. These will increase the difficulty in circuit verification and enlarge the risks of research and development.

Instead of analog approach, we could design the PLL by all-digital circuits to replace analog designs for avoiding above troubles. This PLL is called the “all-digital phase-locked loop (ADPLL)”. By this way, many of the problems mentioned above can be removed between the integration of analog and digital. Furthermore, in contrast to the analog PLL, the adaptability of ADPLL is rather high. Due to the programmable capability, it is easy to change the parameters for satisfying different system requirements, and then reducing the cost and time of development [7]-[9]. This is also the main reason why we choose the all-digital structure as our research topic.

1.2 Research Motivation

1.2.1 Motivations and Purposes of this Research

PLL can only work within a narrow frequency band; therefore we intend to design a PLL with ultra-wide capture range. This PLL is designed to work for the input frequency which spans from 1kHz to 1MHz, and we don’t have any prior information about the signal frequency. In this case, the ratio of the highest input frequency to the lowest input frequency is up to 1000. Moreover, we hope to have a good lock-in range and lock time to increase the application range. As displayed in Table 1.1, there are several researches about the PLL whose capture range ratios are over 3 at least. The lock time of analog PLL is larger in general such as the PLL in [5]. Although the PLL in [10], [11] have pretty good lock time, their phase resolutions, which isn’t shown in this table, are very poor. In other words, they have worse jitter performance even if they are in the locked-state. Therefore, in contrast to [7], [8], [12], we hope the lock time could be less than 100 cycles in our design. We don’t want to pay too much price for wide capture range.

Furthermore, there are other researches about ultra-wide capture range of PLL so far, but all of them have to work in the noiseless environment [7], [11], [13]-[15]. This is obviously not suitable for practical applications; it is necessary that the PLL is required to have good noise immunity.

Table 1.1 The performance parameters about several PLL systems Performance

parameter Ref [5] Ref [7] Ref [8] Ref [10] Ref [11] Ref [12] Circuit type Analog All-Digital All-Digital Digital All-Digital All-Digital

Capture range

(Hz) 8.5M-660M 2M-500M 87M-250M 0.3G-0.8G 50M-550M 500M-1.5G Lock time

1.2.2 Research Approaches

Because of the ultra-wide capture range, it is difficult to use only one control algorithm to handle all the status such as capturing the unknown signal or tracking the signal which is under control. Thus we classify the process of our system into multiple states [10], [11], [16]. Here we design three states for our system: the acquisition state, tracking state and phase-fixing state. Each state uses different control rule for different purposes. For example, we adopt comparatively wide loop bandwidth in acquisition state for capturing the input frequency quickly, but a narrow bandwidth phase-fixing state for fine-tuning.

Additionally, we intend to combine two loops together to get better performance. The PLL which has dual-loop is helpful in various aspects. For example, it uses the dual cascaded PLL to increase the capture range in [17], [18], and in [19] it could also enhance the phase resolution due to two loops. With dual-loop, we can get shorter lock time and wider lock range in our system. Finally, we will implement the PLL system by the digital Hardware Description Language (HDL) to verify the feasibility of our design.

1.3 Thesis Organization

This thesis is organized as following: In Chapter one, we introduce the background of PLL briefly. Next, we describe the structure of traditional PLL to understand its behavior in Chapter two. Chapter three will present all the details of our design concept, including the system architecture and the control algorithm. In Chapter four, we show the hardware circuit architecture of all the designed modules and summarize the operation of this system. Then, in Chapter five we show the simulation results, and make conclusions of this research in Chapter six finally.

Chapter 2

Phase-Locked Loop Basics

In this chapter, we will review some critical concepts about PLL and introduce three types of them: analog PLL (APLL), digital PLL (DPLL) and all-digital PLL (ADPLL). At first, we use a linear model to express the PLL system. Although most PLL are not linear, we can assume the input of PLL is a pure sinusoid and the system already in the lock-state. Then it can be represented as a linear system [1], [2].

2.1 Linear Model of PLL

The function block of PLL is shown in Figure 2.1. The phase detector (PD) is responsible for detecting the differences of frequency and phase between two input signals. Then the output voltage vd is entered into the voltage-controlled oscillator (VCO). The VCO

will send a new signal back to the phase detector accordingly. Usually, the objective of PLL is to generate a pure sinusoidal and merely two components PD and VCO are necessary to achieve it easily. i i i

V

ω

θ

V

ω

θ

ω

ω

θ

θ

d V d

θ

K

Figure 2.2 The phase detector characteristic 2.1.1 Phase Detector Characteristics

Because frequency is the time derivative of phase, we can use the phase difference θd to

represent both phase and frequency differences between two inputs as below:

θd = θi – θo (2.1)

The voltage vd is produced in response to θd. The relationship between vd and θd is shown in

Figure 2.2, which is normally a linear curve. In this figure, Kd is the PD gain and it is a

constant in the range–π/2 ≦ θd ≦ π/2, which is also the effective detection range of PD. The

Vdo corresponds to θd = 0, which means there is no difference between input phase and VCO

phase. Next, we can model the phase detector as

vd = Kdθd + Vdo (2.2)

2.1.2 VCO Characteristics

The voltage-controlled oscillator, as its name implies, can generate an output signal whose frequency is controlled by the input voltage. The I/O relationship of VCO is shown in Figure 2.3, where vc and ωo represent the input voltage and output frequency, respectively,

and the slope Ko is assumed to be constant for simplifying the analysis. When the PLL is in

lock, the frequency deviation ∆ωo is zero, where

o

ω

V

K

Figure 2.3 The Voltage-Controlled Oscillator characteristic

As shown in the Figure 2.3, in which ωi = 10 MHz, and vc = Vco = 2 is corresponding to ωo=ωi.

Beware that Vco is not a property of the VCO; it depends on the input frequency ωi. The

frequency deviation of VCO can be modeled as

∆ωo = Ko(vc – Vco) (2.4)

2.1.3 Frequency Response of Linear PLL Model

As mentioned above, we assume the input and output signals are pure sinusoids, that is:

vi = sin(ωit + θi) (2.5)

vo = sin(ωot) (2.6)

where the θi is the exact phase difference between vi and vo. But for phase detector, it

supposes that the frequency of vi and vo is the same. In other words, the phase detector

believes that all differences between vi and vo are made by both phases. Hence we can rewrite

vo as

vo = sin(ωit + θo) (2.7)

Then, the output frequency of VCO can be expressed as

ωo = d(ωit + θo)/dt = ωi + dθo/dt (2.8)

∆ωo = dθo/dt (2.9)

or

θo = ∫ ∆ωo dt (2.10)

Now we combine above equations with PD and VCO, and the resulting linear model of PLL is shown in Figure 2.4.

Next, we discuss the frequency response of this model. From the frequency response we can observe if ωo can reasonably follow ωi which may vary temperately. We form an AC

model by ignoring the DC parameters from Figure 2.4, and the result is shown in Figure 2.5, where 1/s represents the Laplace transform of integration. Let the open loop gain of the model in Figure 2.5 is G(s), then

G(s) = KdKo / s (2.11)

The transfer function is

do

V

−

V

θ

θ

θ

θ

Figure 2.4 The linear model with PD and VCO

− i

θ

θ

θ

θ

ω

|H(jω)| 1 |G(jω)|

ω

ω

Figure 2.6 The frequency response and bandwidth of linear PLL model

o d i

G

s

s

K

K

s

G

s

s

s

H

+

=

+

=

=

1

1

)

(

1

)

(

)

(

)

(

)

(

θ

θ

For describing the frequency response, we replace s by jω, and the response |H(jω)| is shown in Figure 2.6. When ω is low, |H(jω)| is about equal to unity. On the other hand, when ω is high, |H(jω)| approaches |G(jω)|. Notice that the meaning of ω here is not the same as ωi or ωo,

which represents the varying rate of frequency. Concerning frequency response, we can see that the bandwidth ω3dB occurs when |G(jω)| = 1. That is

ω3dB = KdKo (2.13)

2.1.4 Loop Filter Characteristic

Now suppose we want to reduce the bandwidth but keep PD and VCO unchanged, we can put a voltage attenuator between PD and VCO. The objective of voltage attenuator is to decrease the gain so as to reduce the bandwidth, but we intend to decrease the AC gain only and don’t limit the DC voltage. The solution is to use the RRC low pass filter which is also called the loop filter (LPF) as shown in Figure 2.7. This filter acts as an attenuator at high frequencies but with unity gain at DC. The transfer function of the LPF is

2 ) ( ω ω + + = s s K s F _h (2.14)

Figure 2.7 A RRC low pass filter where 2 1 2 R R R K_h + = C R R ) ( 1 2 1 1 + = ω (2.15) C R₂ 2 1 = ω

The frequency response of |F(jω)| is plotted in Figure 2.8. The gain |F(0)| = 1 at DC and |F(jω)| = Kh at high frequencies. After including F(s), the open loop gain of PLL is modified

as

G(s) = KdF(s)Ko / s (2.16)

The new frequency response of |H(jω)| is shown in Figure 2.9, and the 3dB bandwidth becomes ω3dB = KdKhKo = K (2.17) |F(jω)| 1

ω

ω

ω

Figure 2.9 The frequency response and bandwidth of complete linear PLL model

Finally, a complete linear model with the LPF is shown in Figure 2.10, and the transfer function is 2 1 2 2 o ) ( ) ( ) ( ) ( ω ω ω θ θ K K s K Ks s s s H i + + + + = = (2.18)

Because the denominator of this transfer function is a second-order polynomial in s, it is called a second-order PLL. The different loop filter affects the order of PLL, which may affect the different characteristic or stability of the system loop. Therefore, for simplifying analysis, the PLL design could follow the linear model usually.

do V −Vco − i θ

θ

θ

θ

Figure 2.10 The complete linear PLL model

2.2 Traditional PLL Circuit Design

circuit structure. As mentioned above, the APLL is constituted by analog components only, the DPLL combines analog circuits with digital, and the ADPLL has the all-digital implementation.

2.2.1 Analog PLL (APLL)

The analog PLL consists of the PD, the LPF, and the VCO as mentioned in Section 2.1. A four-quadrant multiplier is used as the PD for detecting frequency deviation at the earliest. Let two inputs of the multiplier be

vi = cos(ωit) (2.19)

vo = sin(ωit + θe) (2.20)

Suppose the gain of multiplier is Km, and the output of multiplier is given as

)) 2 sin( ) (sin( 2 e i e m o i d wt K v v v = =

θ

θ

Because of the LPF, the high frequency part is removed. Thus

vd = 0.5Kmsin(θe) (2.22)

The relationship between θe and vd is shown in Figure 2.11. Comparing with Figure 2.1, the

linear range of PD is very narrow unless the value of θe is small, and the effective detection

range is also [–π/2, π/2]. d V e θ dm V 2 / π 2 / π − π π −

1 2/ R R K_h= R1 C R2 -vd _v c + _

Figure 2.12 The PI filter circuit

For the LPF, instead of the RRC low pass filter, the proportional integrator filter (PI filter) is also a good choice as shown in Figure 2.12, which has the better loop bandwidth than the RRC. However, comparing with the DPLL and ADPLL, the lock time of APLL is rather slow relatively.

2.2.2 Digital PLL (DPLL)

As shown in Figure 2.13, the main difference between DPLL and APLL is that the DPLL uses the digital phase frequency detector (PFD) and the charge pump (CP) to replace the analog PD.

The DPLL usually uses the Exclusive-OR gate (XOR) or Flip-Flop as the PFD. Since the behavior of XOR mimics the multiplier, we can’t get too many advantages. Two PFDs constituted with D-Flip-Flops are depicted in Figure 2.14, where the inputs vi and vo are

square waves.

Figure 2.14 (a) The two-state PFD structure (b) the three-state PFD structure

The PFD of Figure 2.14a has two states, where vi and vo act as clock input of the two

D-Flip-Flops, respectively. In the beginning, assume Q1 and Q2 both are low, and vd is high.

When positive edge of vo is coming, Q2 becomes high and then makes vd low. When positive

edge of vi comes, Q1 becomes high and then make the vd high. In contrast to Figure 2.14a, the

circuit of Figure 2.14b replaces vd with two outputs vU and vD to has more states than the

former. The I/O relationships of them are shown in Figure 2.15 below. We find that the effective detection range of two-state PFD is ±π, and the three-state PFD is up to ±2π. It is more useful than the PD of APLL.

d V d θ π π − 0 d V d θ π 2 π 2 − 0 (a) (b)

Figure 2.16 The charge pump structure

Additionally, the charge pump can transfer the logic signal to be voltage. The structure of charge pump with three-state PFD is given in Figure 2.16. As shown, the capacitor Cp charges

when vU is high and vD is low, discharges when vU is low and vD is high, and keeps the status

unchanged when both vU and vD are low.

A disadvantage with DPLL is that the output voltage vp of CP may be unstable when the

capacitor Cp charges and discharges inconsistently or the charge currents I1 and I2don’t match

with each other. The self-generated noise is capable of destroying the VCO phase, so that additional components are necessary for eliminating the noise disturbance.

2.2.3 All-Digital PLL (ADPLL)

From the above discussion, we find that maintaining the stability of APLL or DPLL is usually complicated, but most analog components have low tolerance for noise. Therefore we may apply the algorithm of behavior description to replace the operation of circuit components. That is the ADPLL, whose function block diagram is shown as Figure 2.17.

The PFD, which is similar to the DPLL’s, is connected to the control unit. The control unit is a general block; any helpful control blocks about the system can be included inside this

Programmable Frequency Divider

PFD Control unit DCO

reference signal feedback

sognal

Figure 2.17 The function block diagram of ADPLL

unit, and it isn’t confined to only the loop filter. Usually we use the time-to-digital converter (TDC) and the digital recursive filter (or named digital LPF) as the core of control unit, because they can exactly replace the CP and LPF of DPLL, respectively. The TDC translates the PFD output into digital codes, and then the digital recursive filter decodes these codes and generates another digital code to adjust the DCO.

The DCO is the digital-controlled oscillator. Obviously, the difference between DCO and VCO is that the output of DCO is controlled by digital codes, but not voltage. The main advantage with DCO is that voltage is more sensitive than digital code, so that DCO can generate a comparably stable output frequency. But there is the resolution problem for DCO since the number of digital codes is limited. In other words, the VCO is able to generate more accurate output frequency than DCO.

2.3 An ADPLL Circuit Model

Here we will analyze the ADPLL in details [14], [20]. Figure 2.18 shows the block diagram of ADPLL [14]. The PFD produces series pulses Up and Down with lengths represent the phase differences, and the Update is used to clock the registers and reset the TDC between measurements. The TDC translates the lengths of Up and Down into digital

Figure 2.18 An ADPLL model

code C as mentioned above. Then the digital integrator determines the digital word W according to C. Finally, the DCO generates the output dco_clk which is compared with the reference ref_in in the PFD after frequency division by the divider.

2.3.1 Phase Frequency Detector (PFD)

The PFD also uses the three-state PFD but we make some improvements as illustrated in Figure 2.19. In the original PFD, if the ref_in leads the dco_in, the Down output still has short pulse. This is not desirable so that we add two inverters and two AND gates. In this way, the

Up output is high when ref_in leads the dco_in and the Down output is high when ref_in lags the dco_in, as shown in Figure 2.20.

ref_in dco_in Up Down up_temp down_temp short pulse

Figure 2.20 The timing diagram of new three-state PFD

The short Update output is necessary. Because the system is controlled in digital manner, the Update is a good trigger to be the time unit of system.

2.3.2 Time to Digital Converter (TDC)

The TDC could be complicated, but we can use the counters to simplify it, as shown in Figure 2.21. Intuitively, the longer Up/Down stands for the larger phase difference. We use

Figure 2.21 The TDC structure

high frequency signal hf_clk as the clock of counter; we can even combine both positive and negative edges to double the precision. The timing diagram is shown in Figure 2.22.

When the Up or Down output is high, the counters will start to work. Until the positive edge of Update is detected, the counters send results to the ALU and go to zeros afterwards. Then, the code C will represent the phase difference in this round.

2.3.3 Digital Integrator

The digital integrator, the recursive filter or the digital loop filter, which is essentially the same. In order to approximate the second-order loop filter as mentioned above, we let the transfer function of integrator be

2 1 5 . 0 5 . 0 1 1 ) ( _{− −} − − = z z z F (2.24)

For simplicity, we only use the number 1 or 0.5 as constant, which can be expressed correctly by limited bits. Converting to digital domain, we get

y[n] = x[n] + 0.5y[n-1] + 0.5y[n-2] (2.25) This is just the behavior of the integrator. The input x[n] and output y[n] are C and W, respectively; W[n] is the function of C[n], W[n-1], and W[n-2]. The structure is shown as Figure 2.23. The Update is the delay clock, and Up/Down is helpful to decide the sign of C.

Update D D 0.5 0.5 C[n] W[n] Up/Down

Figure 2.24 DCO constituted by parallel tri-state inverter

When Up is high, W increases with the positive C. Oppositely, W decreases with the negative

C when the signal Down is high. Additionally, W has the initial value; this value can cause the DCO to generate the initial frequency.

2.3.4 Digital-Controlled Oscillator (DCO)

A DCO is shown in Figure 2.24. It is an evolution from the ring oscillator, which consists of 126 tri-state inverters controlled by a 126-bit digital code D, and D is decoded from the 7-bit word W. When W = 0, all the inverters are off and the charge efficiency of the MOS should be lower. Otherwise, when W = 126 or 127, all the inverters are on and the DCO can generate higher frequency.

2.4 Design Challenges

From above descriptions, we have preliminary knowledge about the operation of ADPLL. However, for working with the wide capture range under noisy environment, the above system is not sufficient. There are some challenges to be overcome:

Challenge 1:

Although the effective detection range of three-state PFD is up to ±2π, it is still difficult to handle the capture range which has 1000 times between the highest frequency and the lowest frequency. Moreover, in order to reduce the lock time, it may be unrealistic to have a long observation time. How can the PFD detect correct phase difference from the ultra-wide frequency range?

Challenge 2:

Under noisy environment, the three-state PFD is easily affected by noise. As shown in Figure 2.25, a small pulse can cause series wrong judgment of the phase, let alone under serious noise environment. How can the PLL determine if the trigger is caused by noise or by signal?

Challenge 3:

Because the input code length of DCO is limited, the wider range causes the lower resolution. In our DCO, the lowest frequency and the highest frequency are respectively 1kHz and 1MkHz. Even if the codeword W is 10-bit, it only generates 1024 different frequencies. How can the DCO get fine resolution under limited bits?

Challenge 4:

As mentioned earlier, the LPF bandwidth is the key of system stability. With wide capture range, it is possible that the difference between reference frequency and center

frequency is quite large, and we can’t use a very narrow loop bandwidth to avoid the high frequency interference. How can the LPF get the balance between the efficiency in large frequency difference and the stability in small frequency difference?

Chapter 3

System Architecture

As mentioned above, we classify the process of our system into three states: the acquisition state, the tracking state and the phase-fixing state. In this chapter, we will describe the algorithm and the architecture about the proposed PLL system and present how to combine the three states against the difficulties encountered under serious noise environment.

3.1 Acquisition State

The acquisition state is the initial state in our PLL design, whose purpose is to find the possible region of reference frequency from 1kHz to 1MHz quickly. Because there is no prior information about this frequency, we have to get useful information from the PFD and handle the information adequately.

The traditional three-state PFD only provides the Up and Down outputs as shown in Section 2.3.1. It is not enough for the requirement of wide capture range. An example is given as Figure 3.1, where we only get the information that the difference between two frequencies is very large from the exaggerated length of Up/Down, but can’t distinguish the difference between these two cases. A PFD which can make an accurate judgment when there is a huge difference between the reference frequency and DCO frequency is necessary.

After some observation, we find it is possible to count the trigger times of positive edge continuously when the Up/Down is determined already. The concept is equivalent to use the reference frequency as the sampling frequency to sample the DCO signal. If one DCO period

freq_1 = 660kHz freq_2 = 15kHz Up Down freq_1 = 500kHz freq_2 = 15kHz Up Down

Figure 3.1 Two cases with large frequency difference

is sampled k times, the trigger times should be k-1, as shown in Figure 3.2. The trigger times can also represent the cycles which the leader exceeds. Although we can’t identify the precise reference frequency according to the trigger times, we know the ratio of the reference frequency with respect to DCO frequency approximately.

On the other hand, we divide the 1kHz-1MHz into multiple bands (Figure 3.3). Each band has its own center frequency, and the difference between adjacent center frequencies is double as frequency increases. Then, we use a Divider that can control the DCO to shift its center frequency from one band to the others. Combining above ideas, we can spend only several DCO signal periods to count the trigger times and then shift the DCO signal to the appropriate center frequency closest to the reference frequency.

1kHz 1MHz band 1 band 2 band n-1 band n

center frequency 1 center frequency 2 center frequency n-1 center frequency n Figure 3.3 The divided bands

Tn Tn+1 Tboundary n boundary f f 3 2 = n f n n

f

f

2

1

=

Figure 3.4: (a) The boundary in unit of period (b) The boundary in unit of frequency

The decision rule of trigger times is closely related to the approach of dividing bands. For simplify, we use the Divider to divide bands, which helps us to use a simple decision rule for selecting the right band according to the trigger times. As shown in Figure 3.4a, the most intuitive approach in dividing bands is to select the middle of two adjacent center frequencies as the boundary. But our design is based on digital circuits, therefore we replace the frequency with the period as time unit, given as

n n n n n boundary

T

T

T

T

T

T

2

3

2

2

2

=

+

=

+

=

where Tnand Tn+1 are any two adjacent center periods, and Tn+1 is twice of Tn. Then 1

3

4

3

2

=

=

f

f

f

As shown in Figure 3.4b, when the reference frequency is over 4/3 times or under 2/3 times than the current DCO center frequency, it jumps to other band.

For the decision rule of trigger times, we have to know the relationship between trigger times and reference frequency. Suppose the initial phase difference between the DCO frequency and the reference frequency is zero for simplifying the problem, and let the reference frequency be 1.6 times of the DCO frequency. This example is shown in Figure 3.5, where (a) shows the phase difference detected by PFD, and (b) shows them on the unit circle. We could find that the trigger happens when the phase difference is beyond a cycle. Therefore, we can use a simple equation to calculate the number of trigger times.

When the reference frequency is m times of the DCO frequency, the phase difference ψ will be

0 0 1

2

π

φ

(

1

)

2

π

φ

φ

=

−

×

+

=

m

−

+

f

f

f

where ψ0 is assumed to be zero. Then

π

φ

π

φ

π

φ

π

φ

π

φ

π

φ

2

)

1

(

2

)

1

(

2

)

1

(

3

2

)

1

(

2

)

1

(

2

2

)

1

(

−

×

=

+

−

=

−

×

=

+

−

=

−

×

=

+

−

=

n

m

m

m

m

m

m

M

Thus the total number of trigger times Ntri_total is



(

1

)



2



=

−











=

n

m

N

π

φ

But in our plan, the trigger times have to recount once again per cycle, and we turn the Ntri as

following:





(n

=

−

=

(

−

1

)

−

tri

N

N

n

m

N

N

Finally, we build a table with different m for observing the trend about trigger times, as shown in Table 3.1.

According to Table 3.1, we find that it is almost 3 rounds per cycle about the boundary trigger times because of our way of dividing bands. For example, at m=4/3 if we observe the sum of any three adjacent Ntri that is over 1 (0+0+1), the reference frequency is over 4/3 times

of the DCO frequency at least and then double the DCO frequency. Moreover, our purpose is to judge whether the reference frequency is over the boundary or not, therefore we just have to observe two rounds. We take the maximum sum of any two adjacent k points as a threshold and show it in Table 3.2. If the sum of two trigger times is over the threshold, the DCO frequency band will be changed immediately.

Table 3.1 The trigger times for several m

multiples trigger times k m=16/3 4 4 5 4 4 5 4 4 5 4 … m=4 3 3 3 3 3 3 3 3 3 3 … m=8/3 1 2 2 1 2 2 1 2 2 1 … m=2.5 1 2 1 2 1 2 1 2 1 2 … m=2 1 1 1 1 1 1 1 1 1 1 … m=1.6 0 1 0 1 1 0 1 0 1 1 … m=4/3 0 0 1 0 0 1 0 0 1 0 …

Table 3.2 The decision rule of band change

multiples thresholds change level m=32/3 20 *16

m=16/3 9 *8

m=8/3 4 *4

m=4/3 1 *2

We spend two DCO periods to determine where the reference frequency is located if it leads the DCO frequency. Otherwise, if the reference frequency lags t he DCO frequency, it needs two reference periods, too.

In addition to determining the band which the reference frequency is located, we hope the DCO frequency could be closer to the reference frequency in the acquisition state. Recall in Section 2.3.2, we use a high frequency signal to count the length of Up/Down output of PFD. But which frequency should we choose? According to Figure 3.1 or Figure 3.2, we find the maximum length of Up/Down is limited to a DCO signal period. It inspires us to use the harmonic frequency of DCO signal instead of a constant high frequency signal to count.

Figure 3.6 (a) Use quadruple DCO frequency to count the phase difference (b) Phase difference level

With the harmonic DCO frequency, we can transform the length into the phase ratio easily. When we select the quadruple DCO frequency to count the Up/Down, both positive and negative edges can be used. In this way, all the lengths are classified into eight levels and these levels are filled within 2π exactly as shown in Figure 3.6. The DCO will change its frequency according to different levels. A larger level makes a greater change. Therefore, the ratio between the Up/Down and the DCO period is more significant than the actual length itself.

Next, we observe the variation of levels. The levels should be converged when the DCO frequency is close to the reference frequency. Here we set a condition that if the same levels appear three times in a row, the acquisition state will be ended. As shown in Figure 3. 7, when the specified condition occurs, the phase difference ψn should be

2 1 2 2 2 − × + − − × = + × − = _n dco dco ref n dco dco ref n f f f f f f

φ

π

φ

π

φ

n

φ

φ

φ

Figure 3.7 The phase difference converges to the same level

and

π

π

φ

φ

There is about 6.25% difference between fref and fdco after the acquisition state. Naturally, the

6.25% is an approximation because the DCO frequency is varied each time; the actual frequency difference will be much less than 6.25%.

In summary, in the acquisition state we respectively use the reference frequency and the multiple DCO frequency to count the phase difference and then choose the appropriate band. Next, the system will get into the tracking state.

3.2 Tracking State

In contrast to the acquisition state, the frequency difference is small in the tracking state. Therefore, we have to make a more rigorous decision in the adjustment of DCO frequency. At first, we change the LPF which is used in the acquisition state. Because our architecture is

based on digital circuit, the replacement of circuits is fairly easy. In the acquisition state, the LPF is given as

]

2

[

5

.

0

]

1

[

5

.

0

]

[

]

[

n

=

x

n

+

y

n

−

+

y

n

−

y

where y[n] represents the current DCO frequency, and y[n-1] and y[n-2] respectively represent the previous two rounds. Also, x[n] means the current phase difference.

Because in the acquisition state our method is to sweep the band for observing the Up/Down levels, we average y[n-1] and y[n-2] for avoiding the DCO frequency sweeping too fast. But in the tracking state, the DCO frequency is near the reference frequency, thereby the difference between y[n-2] and y[n-1] is little. In this case we can adjust the DCO frequency just from y[n-1]. Moreover, in acquisition state the DCO frequency is changed only by the separate Up/Down levels, but it is unsuitable actually. The frequency difference must be represented with the difference of phase difference because the frequency is the time derivative of phase. An example is shown in Figure 3.8, when the Up level becomes smaller and smaller, that means the reference frequency is leading less and less. But the DCO signal still increases its code because the Up signal appears continuously. The DCO code has a direct impact on DCO frequency. When the phase difference becomes zero, the DCO frequency already exceeds the reference frequency a lot. Then the superfluous behavior will be repeated, that will cause the DCO frequency to oscillate endlessly. Therefore, we replace the single phase level with the phase level difference as the LPF input, and the LPF function would be

]

1

[

]

1

[

]

[

]

[

n

=

x

n

−

x

n

−

+

y

n

−

y

Furthermore, we increase the resolution of phase difference four times in the tracking state. A 16x DCO frequency replaces the quadruple DCO frequency as the high frequency of TDC. It means that 2π is divided into 32 levels now. In this way, the phase difference of PFD can be expressed accurately and the system could make more precise decision.

As in the acquisition state, we also set a condition to determine if the tracking state has been completed, and this condition must be stricter for ensuring the DCO frequency be the same as the reference frequency. In our DCO design, the minimum frequency difference between two adjacent DCO codes is about 0.332%, so that the DCO frequency is appropriate if the difference between the DCO frequency and reference frequency is less than 0.00332/2 = 0.166%. We set the phase levels to be the same N times in a row as shown in Figure 3.9, that is ) 1 ( 2 1

2

)

1

(

2

2

2

+

×

−

×

−

=

+

×

×

−

=

+

×

−

=

N

f

f

f

f

f

f

f

f

f

φ

π

φ

π

φ

π

φ

M

π

π

φ

φ

n

φ

φ

Figure 3.9 The phase levels converge to the same level N times

over 0.166%. Thus we set N=20 finally. If the condition is reached, the frequency is assumed to be locked.

However, according to Figure 3.9, we find that there is a constant phase difference ψn

although the frequency difference is zero. An example is shown in Figure 3.10. Because we use the level difference as the basis of adjusting frequency, the initial phase in the tracking state is ignored. Thus we next enter into the third state, the phase-fixing state, to resolve the constant phase.

3.3 Phase-Fixing State

A constant phase can be taken as a fixed time delay. The most intuitive approach to eliminate the time delay is to delay the DCO signal. But this is impractical, since the PLL is a

sensitive feedback system. If we delay the DCO signal directly, the PFD may misinterpret it as a low frequency signal. Then the system will break the steady state. Moreover, the damage of delaying signal is too strong for the waveform in spectrum. Sometimes we have to eliminate the phase repeatedly, but delaying signal for many times will cause the DCO signal with large phase errors.

Although we can not delay the DCO signal directly, we could make it indirectly. First, we change the high frequency of TDC for the 64x DCO frequencies, and there are 128 levels per cycle, which represents the phase resolution is about 3 degree for our system. But different from the tracking state, the 128 levels are just the reference in this state; they don’t affect the DCO output. The DCO is controlled only by the value of Up/Down, not the length. Therefore the LPF in the phase-fixing state is

1

]

1

[

]

[

n

=

y

n

−

±

y

The sign represents the Up/Down, respectively. The constant number 1 means that the DCO only makes the least adjustment according to the Up/Down signal. Moreover, we record the information of DCO frequency when the tracking state is ended. Because of the digital circuit, we can use registers to store the DCO code easily. In this way, we can reduce the DCO period to decrease the constant delay indirectly. When the DCO signal is out of control, the system can recover the DCO frequency from the stored DCO code.

Moreover, there is another reason for DCO code recovery. In our setting, the set of series levels is {30, 15, 7, 3, 1, 0}. When the phase difference is less than these levels, which means the two phases are very close and we have to handle the DCO more cautiously. As shown in Figure 3.11, the initial phase is 89, and the stored DCO code is 777. In this example, the reason of DCO code recovery in the first is the DCO code which will be over 50 than the stored code, and the others are the phase levels which are small enough. Finally the phase difference will be zero and the DCO signal maintains stable. The objective of PLL is

ref_freq doc_freq phase level Up Down dco_code backup_code

recover recover recover

recover recover recover

10 ≤ 1 ≤ ≤0 2 ≤ 5 ≤ 50 777± ≥

Figure 3.11 The process of fixing phase

completed.

Summary of Three States

Actually, the purpose of the three states is quite similar. The differences between them are only the resolution of phase and the LPF. In the acquisition state, the LPF gain is large to raise the bandwidth because we have to determine the approximated location of the reference frequency within the wide capture range. In the tracking state, we replace the phase difference with the difference of phase deviation; it can better express the difference between the reference frequency and DCO frequency. Finally in the phase-fixing state, we use the most prudent LPF and store the DCO frequency got from the tracking state.

The complete process is shown in Figure 3.12, where Figure 3.12b - 3.12d represent the phase difference, the DCO code and the DCO frequency, respectively. In the beginning, it spends some DCO periods to find the right band; the phenomenon appears in Figure 3.12d. Next, the DCO frequency starts to sweep the band until there is the same phase difference

1st jump to 128kHz 2nd jump to 256kHz Initial center frequency 64kHz miss miss into 2nd state into 3rd state recover 224kHz zero phase difference (b) (c) (d) PFD TDC LPF DCO dco code (c) dco frequency (d) phase difference level (b) reference frequency (a)

Figure 3.12 A lock process example

frequency first passes the reference frequency in this example. After entering into the tracking state, the scale of phase difference level is changed and the movement of DCO code becomes more sluggish. Then, in the phase-fixing state, we can adjust the DCO code indulgently because we store the right code already. Finally, the reference signal is locked.

3.4 The Noise Problem

Above discussion is made under the noiseless environment, where we only resolve the wide capture range problem. Next, we consider the reference signal which is sampled from the noisy environment.

3.4.1 The Noise Effect

Figure 3.13 The error phase and error trigger

down to one degree, there are at least 128 points which may be erroneous in a period. In our PFD, the error will lead to erroneous phase or trigger point. As shown in Figure 3.13, the error phase causes the phase difference unstable and we can handle it with LPF. But, the error trigger not only makes the irregular Up/Down output but also produces excess trigger times, which may result in incorrect band judging from the trigger times. Therefore, we would rather have more error phases than error triggers.

3.4.2 The Conversion of Noise

Before discussing how we handle the noise problem, we analyze these noises first. In our plan, the PLL have to work in the noisy environment whose signal to noise ratio is down to 0dB. Therefore, the following discussion will be focused on the worst case.

The signal could be classified into the analog and the digital. If the signal is digital, we get the binary 1 or -1. The noise, which is zero-mean Gaussian noise, will be added to every point of the digital signal, and it is assumed to be independent between any two points. Because the signal to noise ratio is 0dB, the noise power is equal to the signal power and the noise variance is 1. The probability of error is Q(1) = 15.9% and each point is the same as shown in Figure 3.14a. Otherwise, if the signal is analog, the noise will be added to the sinewave directly as shown in Figure 3.14b. The error probability of each point would be different. In the peak positions, the error probability is about Q( 2 ) = 3.97%, while in the zero-crossing

positions, the error probability will be near 50%.

Therefore, if there is a ‘change’ between successive sampling points, which means that the value varying from 1 to -1 or -1 to 1, it is about 15.9% caused by noise and 84.1% by data transition for digital signals. Thus, to determine whether the change is caused by noise, we can further observe the next point. If another change appears again, we are certain that the point is affected by noise and then repair it. Otherwise, it is considered as a data transition as shown in Figure 3.15.

The above idea is based on the necessity of phase resolution. Because we have 128 points in one signal period, it is impossible to have two consecutive changes theoretically. However, we also have to take the possibility of two consecutive errors into account, even if the probability is low (15.9%^2 = 2.53%). As there are 128 points in a period, it is about 128*2.53% = 9 error points which can’t be removed by the method.

Figure 3.14 The noise effect for different signals

change _change current point next point (a) (b) change

As a result, we have to further consider the multiple consecutive errors. Two approaches are proposed here. The first approach uses the technique of cascade. After one error point is repaired, we resample the signal once again every two points. As shown in Figure 3.16, two consecutive errors will become one error, and then we can use the method above to repair the single error. Similarly, we can increase the cascade state if there are more consecutive error points. The second approach is to observe the following two points instead of the next point. That means the points will be repaired if the changes appear twice as shown in Figure 3.17.

For the two approaches, we find the performance of the second approach is better than the first one as shown in Figure 3.18. The reason is because the first approach uses the cascade technique, so that this state could handle the error points which can’t be repaired by the previous state. But it can’t judge whether the decisions of previous state are correct or not, as illustrated in as Figure 3.19a. Hence on the case of multiple consecutive errors, the first

Figure 3.16 The cascade approach to repair consecutive points

change

repair repair

Figure 3.18 Comparison between two approaches of repairing two consecutive points

Figure 3.19 (a) Wrong repairment with correct points (b) phase resolution problem

approach is not as good as the second. Moreover, the first approach has to down sample the signal, thereby the resolution will be affected in data transition positions (Figure 3.19b). As a result, the second approach is taken.

Because our signal has wide frequency range, there are over 128 points in a period when the signal frequency is low. We can’t guarantee that more than two consecutive errors may occur. Thus, based on the second approach described above, we observe the following three points, even five points. Basically, observing more following points can correct more consecutive errors, but it also causes more wrong repairments if the data transition is coming

Figure 3.20 Wrong repairment with multiple points approach

as shown in Figure 3.20.

Figure 3.21 shows the performance of the noise removal. Except the error probability (Er), we can also calculate the positive trigger ratio between the original signal and the processed signal. Because our purpose is to reduce the trigger errors as much as possible, we can accept a larger trigger ratio even if the error probability is lower.

The two parameters between the number of observation points and the frequencies are shown in Figure 3.22. In high frequencies, the number of points are less in a period, thus fewer phase errors and lower error probability are obtained. But when the frequencies are low, the advantage of repairing more points appears. Besides, repairing more points lead to

1MHz 10kHz repair 2 points repair 5 points repair 3 points repair 2 points repair 5 points repair 3 points Er trigger ratio-1

Figure 3.22 The error probability and trigger ratio for repairing different points

excellent trigger ratio.

Nevertheless, this method still has the defects. From Figure 3.22, the trigger ratios of repairing five points are not enough when the frequencies are very low. But we can’t increase the observation points unlimitedly because it will bring wrong repairment in data transition positions. Furthermore, the discussions above all focus on the digital transmission. If the