行政院國家科學委員會專題研究計畫 期中進度報告
矽鍺量子點奈米級記憶元件及陣列之製作與研究(1/3)
計畫類別： 個別型計畫 計畫編號： NSC93-2215-E-002-015- 執行期間： 93 年 08 月 01 日至 94 年 07 月 31 日 執行單位： 國立臺灣大學電子工程學研究所 計畫主持人： 管傑雄 共同主持人： 蔡振水 報告類型： 精簡報告 處理方式： 本計畫可公開查詢中 華 民 國 94 年 5 月 30 日
行政院國家科學委員會專題研究計畫執行進度報告
矽鍺量子點奈米級記憶元件及陣列之製作與研究
Study and Fabrication of SiGe Quantum Dots Memory Device
and arrays
計畫編號：NSC 93-2215-E-002 -015-
執行期限：93/08/01 ~ 94/07/31
主持人： 管傑雄教授 台灣大學電機系
共同主持人： 蔡振水特聘研究員 中研院應用科學研究中心
一、 中文摘要 今日 MOSFET 已經佔有超過 88%的 IC 市場比例；原因是 MOSFET 能縮小到 比其它形式的元件更小的尺寸，使其成為 IC 的主要元件。當單電子的電晶體，其以 量子效應取代古典電荷的傳輸原理。在 此，量子效應的穿隧將單一電子的量化電 荷規則化。 目前記憶體元件之特性乃是利用將 電子儲存於浮動閘極中，藉由臨界電壓的 位移來判別記憶與否。由於微影、膠體化 學與磊晶成長的進步，本計畫擬採用半導 體或金屬材料來製作量子點，並藉由量子 點可儲存電子的特性來取代浮動閘極，達 到應用於記憶體元件的目標。 本計畫分三階段進行，第一階段主要 目摽為量子點製程，製作 MOS 結構以作 電容、電流等電性量測；第二階段為製程 記憶體元件，對其做電性及可靠度等相關 記憶元件特性的量測；第三階段為製作 EEPROM，並做電性及光電特性的量測。 關鍵詞：量子點、單電子記憶體、奈 米結構。 二、 本年度計畫緣由與目的Most of modern non-volatile memory devices are based upon the electron storage in the so-call “floating gate” underneath the MOS gate. The 1 or 0 bit can then be memorized and differentiated by telling the threshold voltage shift of this MOS transistor. The development of modern porous materials, polymer science and epitaxial technology has been rapidly progressing recently. The project is proposed to apply the nano-scale semiconductors in the floating gate memories.
including MOCVD and E-Bean Writer achieved SiGe QD. It will be applied in the planer-type MOS memory cells for this research.
First of all, simple metal-insulator- semiconductor (MIS) structures will be fabricated to measure and analyze their electrical characteristics using standard current-voltage and capacitance-voltage measurements. The study of their capabilities in charge trapping and long term storage will be followed. After optimization of the MIS structures, the quantum dot memory cell will be studied in terms of its program, erase and read characteristics. The reliability and compatibility with existing thin process of these memory cells will be further evaluated finally.
In the first year of this research, we focus on the fabrication of fundamental structure of memory devices, and its basic memory characterization. The key points of this structure are the growth of high quality tunneling oxide and the fabrication of high density and uniform quantum dots layer. Besides the SiGe semiconductor-material dots, we use gold dots to be compared. In order to make electrical test, we fabricate the MOS structure. We make typical C-V (capacitance- voltage) test and measure its C-V curve to confirm its memory characterization.
三、 執行進度
1. Ge nano-dots growth
We present an extensive study about the formation of SiGe dots on SiO2. The
formation of Ge dots in this work is grown in commercially CVD system, the Sirius 400 UHVCVD of Unaxis. The SiGe dot fabrication sequence is as follows: a 3-nm-thick tunneling oxide layer is grown on a (100)-oriented p-type Si substrate via rapid thermal oxidation (RTO). Before the RTO of SiO2, Si wafers were cleaned by
RCA process. The SiO2 on Si wafers sent to
the loading chamber which is pumped down to 10-6 torr were transferred in reactor of UHVCVD. Pure silane (SiH4) is used as Si
source precursor and germane (GeH4) as the
Ge source gas. The UHVCVD is hot-wall processing at 550oC growth temperature. A series of experiments were studied at deposition time of 30mins, 120mins, and 150mins. The evolution of the Ge dots has been observed by SEM (show as Fig.1.). We found that the density of Ge dots were larger as the deposition time was longer. By continually accumulating the Ge atoms, the dot size is larger as the time evolution. The size distribution was inhomogeneous, and was difficult to control. So the advanced research and study of Ge dots growing on SiO2 are required and continued.
2. Gold nano-dots MOS
Fig.2. shows our basic structure, including the P-type substrate, thermal oxide, nano-dots layer, control oxide, and contacts. In order to gate the tunneling characterization, we design two kinds of thickness, 3nm and 6nm. In the part the nano-dots layer, we fabricate different types of materials of dots. Besides the initial SiGe
nano-dots, we also use gold nano-dots to make comparisons. We believe that these two different types of material have different carrier transports mechanism, and we will make further study and research about it. On the nano-dots layer we design a control oxide layer about 40nm to prevent carrier tunneling to the gate. After the basic structure is accomplished, we make the contacts on the top and bottom to fabricate MOS structure. A typical high frequency C-V measurement is tested by HP4284A.
First, we grow the tunneling oxide layer. The silicon wafer is cleaned in standard RCA recipes, dipped in 10% hydrofluoric acid, rinsed in de-ionized water and dried, followed by a thermally grown 3/6nm-thick dry SiO2 layer as a
tunneling oxide on p-type (100) silicon substrate at 950oC.
In the part of fabrication of gold nano-dots layer, we apply chemical process. We use gold nano-particle solution which is synthesized by chemical process. First we use clean the organic contaminant with reactive ion etching (RIE) system. Then, chemical surfactant is coated on the tunneling oxide. After several minutes the surface of tunneling oxide will be stuck with negative charged organic molecules. Then we spray the gold nano-particle solution. After waiting about 1hours the gold particles adhered with positive charged molecules combine with the initial negative charged molecules, and they indirect attach on the surface of tunneling oxide. At last we use RIE system again to clean the residual
organic molecules and the nano-dots layer is accomplished.
We take SEM pictures of the gold nano-dots layer and measure their shape, dimensions, and density (show as Fig.3.). These gold nano-dots are almost round shape. Their diameter is about 20nm and has very small difference. The distribution of particle is random but the total number on a large enough area is uniform. The density of gold particles are about 1010 per centimeter square.
Finally the nano-dots layer capped with 44nm control oxide with plasma enhanced chemical vapor deposition (PECVD) system and 300nm Al gate deposition complete the gate stack formation of MIS capacitor. Last the samples are thermally annealed at 400oC in either pure N2 or forming gas (90%N2 +
10%H2) ambient.
The cross-sectional high resolution transmission electron microscope (HRTEM) of an oxide/Au nano-dots/oxide stacked structure is also show in Fig.4. It is clearly shown the Au nano-dots are embedded between tunnel oxide and control oxide, which are confirms the uniform size distribution of Au nano-dots of diameter nearly 18nm. Additionally we also fabricate a sample without gold particle to be a comparison.
3. 量測結果及討論
In the part of SiGe nano-dots devices, we still try to fabricate higher quality nano-dots layer. About these previous fabricated devices, their measurement data
are unstable and not complete. We still need to put more efforts on its fabrication.
In the part of gold nano-dots devices, Fig.5. shows the hysteresis curve of capacitance-voltage (C-V) measurement after a bias from -10V to +10V. All samples were held for 30 s at -10V before being swept to +10V and then held at this voltage for 30 s before returning to -10V. The holding time ensure that the structure are fully charged or discharged by the holding bias before commencement of the C-V sweep and any change in the sweep rate would not affect the flatband voltage shift, as evidenced by Yong Kim et al. The C-V hysteresis shows a significant threshold -voltage shift up to 1.7V, which is enough to be defined as 1 or 0 for the circuit design. The trapped charge density can be electrically calculated through the threshold-voltage shift by △ Vt = Qt ×
tcontrol /εox. Qt is the density of trapped
charge(C/cm2 in unit) in Au nano-dots. Setting tcontrol = 44nm, △ Vt = 1.7V in
sample A, and εox = 3.9 × 8.885 × 10-14
F/cm, the number of electrons trapped in the Au nano-dots was calculated to be 8.36 × 1011 cm-2. It is indicated the every Au nano-dots trapped almost close to 70 electrons, due to the Coulomb blockade effect.2 The sample B shown the △Vt =
2.48V with the thinner tunneling oxide owning close to 100 electrons to be calculated.
In this work, several oxide stacked structure embedded with Au nano-dots has been demonstrated for application in memory devices. The deeper potential well
of metal nano-dotls shows large charge storage and long retention time than Si nano-dots device has been reported. Our results also show the low operating voltage to achieve the memory window up to 1.7V(2.48V), which is enough to be applied in memory device.
四、 總結
We have successfully designed and fabricated MIS device with gold nano-dots layers. The SiGe nano-dots layer also gets preliminary achievement. Our devices with gold nano-dots layer shows high storage capacity and operation at low bias voltage. Our further work is to fabricate dot layer with higher density and focus on its electric characterization and reliability issue. 五、 圖表及註解
Fig.1.(a).
Fig.1.(c). Fig.1. SEM picture of SiGe nano-crystal layer grown with UHVCVD with different operation parameters and time. (a) is grown during 30 minutes; (b) is grown for 120 minutes; (c) is grown for 150 minutes.
Fig.2. Schematic cross section of MOS capacitor with Au nano-dots.
Fig.3. SEM picture of typical Au nano-dots deposited
on SiO2 with a density of 1.2 × 10 10
cm-2.The mean size is equal to 20nm.
Fig.4. Cross-sectional HRTEM of stack structure and showing single Au nano-dot of diameter nearly 18nm.
Fig.5. Typical high-frequency C-V characteristics of MOS capacitor incorporated Au nano-dots.
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