Impacts of a buffer layer and hydrogen-annealed wafers on the performance of strained-channel nMOSFETs with SiN-capping layer

Impacts of a buffer layer and hydrogen-annealed wafers on the performance

of strained-channel nMOSFETs with SiN-capping layer

Tzu-I Tsai

a

, Horng-Chih Lin

a,b

, Yao-Jen Lee

b,*

, King-Sheng Chen

b

, Jeff Wang

d

, Fu-Kuo Hsueh

b

,

Tien-Sheng Chao

c

_{, Tiao-Yuan Huang}

a

a

Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan b

National Nano Device Laboratories, Hsinchu, Taiwan c

Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan d

Department of Nanotechnology Engineering, University of Waterloo, Waterloo, Canada

a r t i c l e

i n f o

Article history: Received 15 May 2008 Accepted 7 June 2008 Available online 23 August 2008 Review of this manuscript was arranged by A. Iliadis, C. Richter, and A. Zaslavsky Keywords: Strained-Si CESL Si3N4capping Hydrogen-annealed wafer

a b s t r a c t

In this study, the effects of Si3N4layer capping and TEOS buffer layer inserted prior to the Si3N4deposition

on the NMOS device characteristics as well as correlated hot-electron degradations were investigated. The devices were built on two kinds of the substrates, namely, Cz and hydrogen-annealed (Hi) wafers. More importantly, we found that hydrogen species is the primary culprit for aggravated reliabilities in strained devices. By exerting the accelerated stress test, we could study the hot-electron degradation thoroughly in terms of threshold voltage shift (DVTH), transconductance degradation (DGm) and so on.

The TEOS buffer layer could effectively block the diffusion of hydrogen species from the Si3N4capping

layer into the channel and the Si/SiO2interface during the Si3N4deposition as well as subsequent thermal

cycles.

Ó 2008 Elsevier Ltd. All rights reserved.

1. Introduction

With CMOS scaling into the nanometer regime, strained chan-nel engineering has been adopted as one of the most effective rem-edies and thoroughly explored for the much needed performance enhancement such as boosting the drive current of the scaled de-vices[1–3]. With regard to carrier mobility enhancement, intro-ducing strain in the channel region can enhance the carrier mobility[4]. What the researchers could accomplish is by either applying highly bi-axial tensile strain to the channel region with a SiGe virtual substrate[1], or by uni-axially straining the channel with strain boosters[1–3]. Recent studies have shown that the uni-axial strained channel from a contact etch-stop silicon nitride layer increases the current drivability[5]. Such scheme is attractive and practical because it can be easily implemented using VLSI process-ing. The local strained channel (LSC) technique is proposed to pro-vide tensile strained channel in nMOSFETs[6].

As long as the knowledge base concerning the mobility enhancement of Si strained channel has been established, it is appropriate now for us to concentrate our attention to its relating

issue such as reliability. Among the most critical reliability issues, device degradation induced by hot-electrons is the most represen-tative one in deep sub-micro nMOSFETs[7]. The physical mecha-nisms and characteristics of hot-electrons degradation have been extensively examined[8]. Furthermore, by exerting the accelerated stress test, we could study the hot-electron degradation thor-oughly in terms of threshold voltage shift (DVTH), drain current

degradation (DIDS), subthreshold swing degradation (DS.S), and

transconductance degradation (DGm) and so on. According to the aforementioned contents, local tensile strain technology with the Si3N4capping layer has been viewed as one of the most effective

methods to boost the drive current in scaled nMOSFET devices, the device reliability associated with the strained device owing to the strain, and excess hydrogen and nitrogen incorporation from the deposited Si3N4layer is an imminent concern. In line with this,

the incorporation of a thin TEOS buffer layer to improve the reli-ability performance has been proposed[9].

In addition, hydrogen-annealed wafers (Hi-wafer) have been re-ported having reduced oxygen defects in Czochralski (CZ) wafers

[10–11], with improved micro roughness and less defect on the surface after high temperature hydrogen anneal. The following sec-tions describe in detail the behaviors of nMOSFETs device with lo-cal strained channel technique using SiN-capping layer on Hi- or Cz-wafers as well as the related reliability.

0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2008.06.007

*Corresponding author.

E-mail address:yjlee@ndl.org.tw(Yao-Jen Lee).

Contents lists available atScienceDirect

Solid-State Electronics

2. Device concept 2.1. Strained-Si technology

Strained-Si technology improves the drive current of CMOS through altering the energy band structures of the surface channel

[12–14]. There is a branch of strained-Si technology: bi-axial strain and uni-axial strain. The bi-axial tensile strained channel achieved by growing a Si channel layer on a relaxed SiGe substrate could im-prove the drive currents of both nMOSFETs and pMOSFETs when the incorporated Ge content is more than 20% of the relaxed SiGe substrate[15–16]. It is worthy to note that the thickness of the top strained-Si layer has to be thinner than a critical thickness that depends on the Ge content of the underlying relaxed SiGe sub-strate to avoid the generation of abundant amount of dislocations due to lattice mismatch[17]. Aplenty dislocations of the virtual SiGe substrate may become an obstacle to practical applications.

In contrast, the uni-axial strained channel technology has been proposed to avoid the shortcomings of bi-axial strained channel. Uni-axial strain can be set up by modifying contact-etch-stop-layer (CESL) deposition[18–19], silicidation[20], source/drain material

[21], shallow trench isolation (STI) [22], packing process [23], and so on. Moreover, uni-axial strain can be arbitrarily exerted in any direction correlative with the carrier transportation; hence the performance of both NMOS and PMOS devices can be enhanced by respectively applying the tensile and compressive strains. Mobility,

l

, for carriers in semiconductors is formulated as

l

¼q

s

m ð1Þ

where 1/

s

is the overall scattering rate and m*_{is the conductivity}

effective mass. From the above mobility formula, we could set about mobility enhancement of strained-Si devices by reducing either the conductivity effective mass or the scattering rate. The conduction band of unstrained bulk Si is consisted of six degenerate valleys (D6) with the same energy[24](as shown inFig. 1). Under the ef-fect of bi-axial tensile strain, the sixfold degenerate conduction band is split up into a fourfold (D4) in-plane and a twofold (D2) out-of-plane degenerate valleys in the energy band diagram[25]. The energy difference (DE) betweenD2 andD4 sub-bands

deter-mines the total population of electrons in each sub-band. As a re-sult, the larger DE, the more the percentage of total electron population would occupy theD2 valleys. Since theD2 valleys have a smaller effective mass as compared with that of theD4 valleys, the electron mobility enhancement could be accomplished as more electrons occupy theD2 valleys. In addition, suppression of inter-valley phonon scattering can effectively reduce the electron scatter-ing rate (1/

s

)[25–26], which in turn may also enhance the mobility. From the effort of Leitz et al. [27], we know that uni-axially and compressively strained pMOSFETs may have lighter in-plane effec-tive mass through full-band Monte Carlo simulation[24], thus hole mobility is enhanced. However, for the case of bi-axial tensile strain, the reduction of the inter-valley scattering is the only plausible ap-proach to the hole mobility enhancement by about 25–30% of ger-manium concentration necessary for introducing more than 1 G Pa stress[27].

2.2. Hi-wafer technology

A raw Czochralski-grown (CZ) silicon wafer includes supersatu-rated oxygen atoms and nuclei for oxygen precipitation, which are introduced during crystal growth. For ultra large scale integrated (ULSI) devices, CZ silicon wafers ought to be free of defects in the device active layer and adequate oxygen precipitates in the bulk region to enable intrinsic gettering for metallic contamination. However, inadequate oxygen contents would induce many mi-cro-defects during later heat treatments for ULSI fabrication. The micro-defects, which are induced near surface region, lead to var-ious harmful defects such as OISF (Oxidation induced Stacking Fault), pattern edge dislocations, gate oxide breakdown failures and so on. For the purpose of improving the surface quality and preventing the harmful defect generation, both oxygen and nuclei ought to be completely removed from the surface region. There is an approach to produce oxygen-less Si wafer by virtue of a high temperature anneal in hydrogen ambient so as to efficiently eject the oxygen atoms from the surface region[10–11]. The hydrogen anneal was carried out at 1200 °C for 1 h by using a hot wall type vertical furnace. Wafers which received such treatment are dubbed ‘‘Hi-wafer”. Fig. 2 shows the oxygen out diffusion profile after annealing in hydrogen or oxygen ambient. The oxygen contents

in the surface region of Hi-wafer are obviously smaller than that of a wafer annealed in oxygen ambient. Thus the generation of oxy-gen-induced defects near the surface region could be significantly reduced in Hi-wafers, making such wafers a good choice for improving the wafer yield.

3. Experimental results 3.1. Device fabrication

All device fabrications were carried out at National Nano Device Laboratories. nMOSFETs were fabricated on 6-in Hi- and Cz-wafers with resistivity of 15–25Xcm. The hydrogen anneal was carried out at 1200 °C for 1 h. The p-type well was formed first by BFþ 2

implantation at 70 keV and 1.2  1013cm2_{. Next, a standard local}

oxidation of silicon (LOCOS) process with channel stop implant (by BFþ

2 implantation at 120 keV and 4  10

13_cm2_{) was used for}

de-vice isolation. Threshold voltage adjustment and anti-punch through implantation steps were done by implanting 40 keV BFþ 2

and 35 keV B+_{, respectively. Gate dielectric thickness about}

2.5 nm was grown in an N2O ambient. Then, 200 nm un-doped

poly-Si was deposited. Shallow S/D extensions were formed by implanting As (10 keV, 1  1015_cm2_{). After a 200 nm TEOS spacer}

formation, S/D regions were formed by As+_{implantation at 30 keV}

and 5  1015_cm2_{. Then the substrate electrode patterning was}

performed through lithography and etching processes, followed

by the formation of the substrate contact regions by BFþ

2

implanta-tion at 40 keV and 5  1015_cm2_{. Rapid thermal anneal (RTA) was}

subsequently carried out in a nitrogen ambient at 1000 °C for 10 s to activate dopants in the gate, S/D, and substrate regions. A 300 nm LPCVD Si3N4was next deposited (denoted as SiN/Cz and

SiN/Hi), while some wafers were deliberately skipped of the Si3N4deposition step to serve as the controls (denoted as

Cz-con-trol and Hi). In addition, the effect of intrinsic stress inside the Si3N4layer with 300 nm thickness was remarkable[31]. For some

Si3N4-capped nMOSFETs on either Hi- or CZ-wafers, a thin

LPCVD-TEOS buffer layer (about 7 nm, denoted as SiN/buffer/Cz and SiN/ buffer/Hi) was capped prior to the Si3N4deposition, as shown in

Fig. 3. Finally, a four-level metallization was carried out in PVD sys-tem for contact.

3.2. Electrical characterization and related reliability

All measurements in the following section were evaluated by an HP4156A precision semiconductor parameter analyzer and an HP4284 LCR meter, respectively. Temperature-regulated hot chucks were used to set the measurement temperature at 25 °C.

Fig. 4shows the capacitance–voltage (C–V) characteristics of de-vices. InFig. 4, we could distinctly observe that the poly-depletion effect becomes obvious in the splits with Si3N4capping layer

depo-sitions, irrespective of the use of Cz or Hi-wafers.

This phenomenon is attributed to the additional thermal budget associated with the nitride deposition step by 780 °C LPCVD. It is known that the solid solubility of dopants is temperature-depen-dent and the thermal conditions mentioned above tend to lower the activated carrier concentration in the poly-Si gates [28]. In addition, the poly-silicon depletion can be avoided when PECVD is used for the nitride deposition owing to the short deposition time of PECVD for the activated carrier concentration in the poly-Si gates being less influenced.Fig. 5shows the drain current (ID)

and transconductance (Gm) versus VG for nMOSFETs with W/

L = 10

l

m/0.5

l

m from different splits. Higher subthreshold slope (S.S.) and leakage current, about 2 orders larger, are found for the splits with Si3N4capping layer due to contact etched damages. A

significant increase of Gm was found for the splits with Si3N4

cap-ping layer owing to the tensile stress in the channel, which in-creases the electron mobility in the channel.

Fig. 6shows the distribution of the threshold voltage (VTH), VTH

(L)–VTH(10

l

m), versus the gate length. Among the splits, the

con-trol splits depict a pronounced reverse-short-channel-effect (RSCE). This is probably due to boron segregation at the implant-damaged regions located near the edge of the channel. The phe-nomenon, however, is not observed in the Si3N4capping splits. It Fig. 2. Schematic diagram of the oxygen depth profile after hydrogen anneal at

1200 °C for 1 h[11].

is noted that RSCE would be suppressed by boron redistribution as the thermal budget increases and bandgap narrowing effect caused by channel stress[29].

Fig. 7shows the percentage increase of transconductance (Gm) for all splits as a function of channel length. The Gm is linearly re-lated to channel mobility. When the channel length is scaled to less

than 1

l

m, Gm increases sharply owing to the unique feature men-tioned above. Specifically, Gm increases by 20% for nMOSFETs with W/L = 10

l

m/0.5

l

m. In addition, the channel strain was scarcely influenced as the thickness of the TEOS buffer layer was lower than 20 nm[9].Fig. 8shows the percentage increase of the on-current with respect to the Cz-control (VG= 1.8 V, VD= 1.8 V) for all splits

as a function of channel length. The trend of on-current enhance-ment is the same as the Gm enhanceenhance-ment.

Fig. 9shows the distribution of the S.S. versus the gate length. For the splits of Cz-controls and Hi, S.S. is independent of gate length. Hi split depicts lower S.S. than Cz-controls because of the better surface quality after high temperature hydrogen anneal. However, the splits with Si3N4 capping layer depict higher S.S.,

especially for long channel devices. The root cause for such phe-nomenon is not clear yet at this stage. Increase in EOT due to poly-depletion effect may play a role. It is noted that the TEOS buf-fer layer could effectively block hydrogen molecules diffusion from Si3N4capping layer deposition. As a consequence, the S.S. increases

due to less effective interface passivation.

Fig. 10shows charge pumping current (Icp) versus base voltage.

The device size is W/L = 10

l

m/0.5

l

m for (a), W/L = 10

l

m/10

l

m for (b), the pulse amplitude is 1.5 V, and the square waveform is used for Icp extraction. The splits of SiN/Cz and SiN/Hi depict

slightly higher Icpcompared with the splits of Hi and Cz-control.

Gate Voltage(V)

-2 -1 0 2

Capacitance (

μ

F/cm

2

)

2.0e-1 4.0e-1 6.0e-1 8.0e-1 1.0e+0 1.2e+0 Hi Cz-control SiN/Hi SiN/Cz SiN/Buffer/Hi SiN/Buffer/Cz W/L= 50 m/50 m _20.7Å 22.21Å 1

Fig. 4. Capacitance–voltage(C–V) characteristics of nMOSFETs processed with TEOS buffer layer and Si3N4capping layer on both Cz and Hi-wafers. W/L = 50lm/50lm.

W/L=10μm/0.5 μm V_D=0.1V

Gate Voltage (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Drain Current (A)

10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4

Transconduce (mS)

0.0 0.1 0.2 0.3 0.4 0.5 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz With SiN layer

W/O SiN layer

Fig. 5. Drain current and Gm (measured at VD= 0.1 V) versus VGfor nMOSFETs with W/L = 10lm/0.5lm.

Gate Length (

μm)

1.0 10.0

Δ

V

TH

(mV)

-40.0 -20.0 0.0 20.0 40.0 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

Fig. 6. VTHdistribution, VTH(L)–VTH(10lm), versus gate length.

Gate Length (

μm)

1.0 10.0

Δ

Gm/Gm (%)

-5.0 0.0 5.0 10.0 15.0 20.0 25.0 Hi SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

Fig. 7. Percentage increase of Gm for all splits as a function of channel length.

Gate Length (

μm)

1.0 10.0

Δ

Ion

/Ion

(

%

)

-5.0 0.0 5.0 10.0 15.0 20.0 Hi SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz Ion@(VG=1.8V, VD=1.8V)

Fig. 8. Percentage increase of on-current for all splits as a function of channel length.

However, Icpincreases drastically for the splits of SiN/buffer/Cz.

These results indicate that the TEOS buffer layer can effectively block hydrogen diffusion into the channel region during the Si3N4deposition process. As a result, the hydrogen incorporation

in the gate oxide as well as at the Si/SiO2 interface can be

sup-pressed remarkably with the incorporation of TEOS buffer.

There-fore, the interface states from the Si3N4capping layer are not

re-paired due to the mechanism of TEOS blocking hydrogen diffusion. Therefore, the percentage increase of Gm for the SiN/buffer/Cz split is lower than that for the SiN/Cz split owing to the large amount of un-repaired interface traps, compared with the Cz-con-trols. In addition, it is noted that Icpof SiN/buffer/Hi split only

Gate Length(

μm)

1.0 10.0

S.S. (mV/dec.)

75.0 80.0 85.0 90.0 95.0 100.0 105.0 110.0 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

Fig. 9. Subthreshold slope versus gate length.

W/L=10μm/0.5μm Vamp.=1.5V Waveform:square

Base Voltage (V)

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4

Charge Pumping Current (pA)

0.0 200.0 400.0 600.0 800.0 1000.0 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz W/L=10μm/10μm Vamp.=1.5V Waveform:square

Gate Voltage (V)

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0

Charge Pumping Current (nA)

_0.0

2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

a

b

Fig. 10. Charge pumping current (Icp) versus base voltage. The device size is W/ L = 10lm/0.5lm for (a), W/L = 10lm/10lm for (b), the pulse amplitude is 1.5 V, and the square waveform is used for Icpextraction.

Effective Field (V/cm)

900.0x103 _1.0x106 _1.1x106 _1.2x106 _1.3x106 _1.4x106 100.0 150.0 200.0 250.0 300.0 Hi SiN/Buffer/Hi SiN/Hi

Effective Field (V/cm)

900.00x103 _1.00x106 _1.10x106 _1.20x106 _1.30x106 _1.40x106

E

ffe

c

ti

v

e

M

o

b

il

ity

(cm

2

/V

-s)

100.0 150.0 200.0 250.0 300.0 Cz-control SiN/Buffer/Cz SiN/Cz

a

b

Fig. 11. Comparisons of effective mobility for devices with W/L = 50lm/50lm. (a) Cz group; and (b) Hi group.

Off Current (A)

10-12 ₁₀-11 ₁₀-10 ₁₀-9

On Current (mA)

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

Fig. 12. On-current (VG= 1.8 V, VD= 1.8 V) versus off-current (VG= 0 V, VD=1.8 V) with W/L = 10lm/0.4lm.

slightly increases over the SiN/Hi split. Therefore, the effect of hydrogen diffusion or blocking is not a serious concern for the SiN/buffer/Hi split. Besides, the larger Icp of long length with

Si3N4capping layer than that of short length was a direct evidence

to explain the S.S. increases for long channel devices due to less hydrogen species diffusion at long channel devices.

Fig. 11 compares the effective mobility for devices with W/L = 50

l

m/50

l

m. For Cz group, as shown inFig. 7a, degraded behaviors are observed for the splits with Si3N4capping. However,

for Hi group, as shown inFig. 7b, it is very interesting to note that the buffer layer prevents the mobility degradation from the Si3N4

capping.

Fig. 12 shows the distribution of the on-current (VG= 1.8 V,

VD= 1.8 V) versus off-current (VG= 0 V, VD= 1.8 V) with

W/L = 10

l

m/0.4

l

m. Lower off-current is found for the splits on the Hi-wafers, owing to its better surface quality.

Fig. 13shows substrate current (Isub) versus gate voltage for all

splits (VDS= 3.75 V) for devices with W/L = 10

l

m/0.5

l

m. The

Si3N4-capped splits exhibit larger Isubthan the control splits for

both Cz and Hi-wafers owing to the enhancement of the ionization rate caused by the channel strain[30]. In addition, among the SiN-capped splits, the SiN/buffer/Hi split exhibits the largest Isubowing

to its largest transconductance.

Figs. 14 and 15show the threshold voltage shift (DVTH) and the

interface state density increase as a function of stress time for all splits after hot-electron (HC) stressing at VDS= 3.75 V and VGSat

the peak substrate current, and the device size is W/L = 10

l

m/ 0.5

l

m. The SiN-capping splits for both Cz and Hi-wafers exhibit

the worst HC degeneration, while the improvement of the HC deg-radation by using the TEOS buffer layers is obviously seen. How-ever, the threshold voltage shift of the SiN/Hi split is worse than that of the SiN/Cz split, similar to the case of the buffer-layer splits,

Gate Voltage(V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Substrate Current (

μ

A)

0 20 40 60 80 100 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz W/L=10 µm/0.5µm VDS=3.75V

Fig. 13. Substrate current versus gate voltage. The device size is W/L = 10lm/ 0.5lm.

Stress Time(sec)

0.0 1000.0 2000.0 3000.0 4000.0 5000.0

Δ

V

TH

(mV)

0.0 50.0 100.0 150.0 200.0 250.0 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

Fig. 14. DVTHafter hot-electron stressing performed at VDS= 3.75 V and VGSat the peak substrate current. The device size is W/L = 10lm/0.5lm.

Stress Time (sec)

0.0 1000.0 2000.0 3000.0 4000.0 5000.0

Δ

N

it

(10

10

/cm

2

)

0.0 5.0x100 10.0x100 15.0x100 20.0x100 25.0x100 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

Fig. 15. Interface trap density generation measured after hot-electron stressing performed at VDS= 3.75 V and VGSat the peak substrate current. The device size is W/L = 10lm/0.5lm.

Stress Time(sec)

0.0 1000.0 2000.0 3000.0 4000.0 5000.0

Δ

Gm (

μ

S)

-60.0 -40.0 -20.0 0.0 Hi Cz-control SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

Fig. 16. Transconductance degradation after hot-electron stressing performed at VDS= 3.75 V and VGSat the peak substrate current. The device size is W/L = 10lm/ 0.5lm.

Base Voltage (V)

-2.0 -1.5 -1.0 -0.5 0.0

Δ

Icp(Icp

stress

-Icp

fresh

) (pA

)

0 500 1000 1500 2000 2500 Hi Cz SiN/Buffer/Hi SiN/Buffer/Cz SiN/Hi SiN/Cz

Fig. 17. Increase in charge pumping current after hot-electron stressing performed at VDS= 3.75 V and VGS at the peak substrate current. The device size is W/L = 10lm/0.5lm.

owing to the fact that the fresh maximum Gm values of both the SiN/Hi split and the SiN/buffer/Hi split are larger than those of the SiN/Cz and SiN/buffer/Cz splits.

It is important to note that, although the Isubis high for the SiN/

buffer samples, significant improvement in HC resistance than that without the buffer is observed. Since the HC tends to break the Si– H bonds during the stressing, and much severe degradation will oc-cur with higher Si–H density. The use of TEOS buffer layer can effectively block the diffusion of hydrogen species into the channel region, therefore less HC degradation in terms of VTHshift and

interface-state generation is achieved.

Fig. 16shows the transconductance degradation as a function of stress time for all splits after receiving hot-electron (HC) stressing at VDS= 3.75 V and VGSat the peak substrate current. The device

size is W/L = 10

l

m/0.5

l

m. The SiN/Hi split shows the worst Gm degradation among all splits owing to the strain enhancement ef-fects and extra hydrogen incorporation mentioned above.

Fig. 17 shows the increase in charge pumping current after 5000 s of hot-carrier stress for devices with W/L = 10

l

m/0.5

l

m. The effect of TEOS buffer layer is observed in terms of lower 4Icp.

After stressing, the SiN/buffer/Hi split possesses higher 4Icpthan

the SiN/buffer/Cz split, although in principle the former split should have a better interface quality. Higher Isuband higher

pop-ulation of generated HC are postulated as the plausible origin for this observation.

4. Conclusions

We have performed a detailed investigation of the LSC channel technique induced by SiN-capping layer with or without buffer layer. Device characteristics including Gm, S.S., Icp, and reliability

were studied on devices fabricated with Hi and Cz starting wafers. The Gm and current drivability can indeed be enhanced by capping the Si3N4layer. We found that the splits with Hi-wafers depict

low-er S.S. than the splits with Cz-waflow-ers. Howevlow-er, with the incorpo-ration of TEOS buffer layer, Icpincreases and Gm is degraded for

SiN/buffer/Cz splits, contrary to the results of the SiN/buffer/Hi splits. The hot-electron degradation is adversely affected when the Si3N4 capping layer is deposited over the gate, regardless

of the types of wafers. When a TEOS buffer layer is inserted prior to the Si3N4deposition, although still worse than the control ones,

significant improvement in hot-carrier resistance over those with-out the buffer layer is achieved.

References

[1] Hoyt JL, Nayfeh HM, Eguchi S, Aberg I, Xia G, Drake T, et al. Strained silicon MOSFET technology. IEDM Tech Dig 2002:23–6.

[2] Ghani T, Armstrong M, Auth C, Bost M, Charvat P, Glass G, et al. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. IEDM Tech Dig 2003:978–80.

[3] Pidin S, Mori T, Inoue K, Fukuta S, Itoh N, Mutoh E, et al. A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films. IEDM Tech Dig 2004:213–6.

[4] Welser J, Hoyt JL, Gibbons JF. Electron mobility enhancement in strained-Si N-type metal-oxide-semiconductor field-effect transistors. IEEE Electron Dev Lett 1994;15:100–2.

[5] Chen Chien-Hao, Lee TL, Hou TH, Chen CL, Chen CC, Hsu JW, et al. Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application. VLSI Tech Dig 2004:56–7.

[6] Ota K, Sugihara K, Sayama H, Uchida T, Oda H, Eimori T, et al. Novel locally strained channel technique for high performance 55 nm CMOS. IEDM Tech Dig 2002:27–30.

[7] Momose HS, Nakamura S, Ohguro T, Yoshitomi T, Morifuji E, Morimoto T, et al. A study of hot-carrier degradation in N- and P-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime. IEDM Tech Dig 1997:453–6. [8] Heremans P, Bellens R, Groeseneken G, Maes H. Consistent model for the

hot-carrier degradation in N-channel and P-channel MOSFETs. IEEE Trans Electron Dev 1988(35):2194–209.

[9] Lu Ching-Sen, Lin Horng-Chih, Lee Yao-Jen, Huang Tiao-Yuan. Improved hot carrier reliability in strained-channel NMOSFETs with TEOS buffer layer. IRPS 2007:670.

[10] Izunome Koji, Shirai Hiroshi, Kashima Kazuhiko, Yoshikawa Jun, Hojo Akimichi. Oxygen precipitation in Czochralski-grown silicon wafers during hydrogen annealing. Appl Phys Lett 1996(68):49–50.

[11] Matsushita Y, Samata S, Miyashita M, Kubota H. Improvement of thin oxide quality by hydrogen annealed wafer. IEDM Tech Dig 1994:321–4.

[12] Takagi S, Mizuno T, Tezuka T, Sugiyama N, Numata T, Usuda K, et al. Channel structure design fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs. IEDM Tech Dig 2003:57–60.

[13] Thompson SE, Armstrong M, Auth C, Cea S, Chau R, Glass G, et al. A logic nanotechnology featuring strained-silicon. IEEE Trans Electron Dev 2004:191–3.

[14] Zhao W, He J, Belford RE, Wernersson L, Seabaugh A. Partially depleted SOI MOSFETs under uniaxial tensile strain. IEEE Trans Electron Dev 2004:317–23.

[15] Hoyt JL, Nayfeh HM, Eguchi S, Aberg I, Xia G, Drake T, et al. Strained silicon MOSFET technology. IEDM Tech Dig 2002:23–6.

[16] Lee BH, Mocuta A, Bedell S, Chen H, Sadana D, Rim K, et al. Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D. IEDM Tech Dig 2002:946–8.

[17] Mizuno T, Sugiyama N, Tezuka T, Numata T, Maeda T, Takagi S. Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility. IEDM Tech Dig 2002:31–4.

[18] Ito S, Namba H, Yamaguchi K, Hirata T, Ando K, Koyama S, et al. Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design. IEDM Tech Dig 2000:247–50.

[19] Shimizu A, Hachimine K, Ohki N, Ohta H, Koguchi M, Nonaka Y, et al. Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement. IEDM Tech Dig 2001:433–6.

[20] Steegen A, Stucchi M, Lauwers A, Maex K. Silicide induced pattern density and orientation dependent transconductance in MOS transistors. IEDM Tech Dig 1999:497–500.

[21] Ghani T, Armstrong M, Auth C, Bost M, Charvat P, Glass G, et al. A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. IEDM Tech Dig 2003:978–80.

[22] Scott G, Lutze J, Rubin M, Nouri F, Manley M. NMOS drive current reduction caused by transistor layout and trench isolation induced stress. IEDM Tech Dig 1999:827–30.

[23] Maikap S, Liao MH, Yuan F, Lee MH, Huang C, Chang ST, et al. Package-strain-enhanced device and circuit performance. IEDM Tech Dig 2004:233–6. [24] Lin HN, Lu CY, Lin HC, Huang TY. Material process and device characteristics

analyses of CMOS with local and global strained silicon channel (I). Nano Commun 2005(12):44–9.

[25] Welser J, Hoyt JL, Takagi S, Gibbons JF. Strain dependence of the performance enhancement in strained-Si N-MOSFETs. IEDM Tech Dig 1994:373–6. [26] Thompson SE, Sun G, Wu K, Kim J, Nishida T. Key differences for

process-induced uniaxial vs. substrate-process-induced biaxial stressed Si and Ge channel MOSFETs. IEDM Tech Dig 2004:221–4.

[27] Leitz CW, Currie MT, Lee ML, Cheng Z-Y, Antoniadis DA, Fitzgerald EA. Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal–oxide–semiconductor field-effect transistors. J Appl phys 2002(92):3745–51.

[28] Sze SM. Physics of semiconductor devices, 2nd ed.; 1985 [p. 69].

[29] Lu Chia-Yu, Lu Ching-Sen, Hsieh Yu-Lin, Lee Yao-Jen, Lin Horng-Chih, Huang Tiao-Yuan. Impacts of LP-SiN capping layer and lateral diffusion of interface trap on hot carrier stress of NMOSFETs. SSDM 2006:528.

[30] Sano N, Tomizawa M, Yoshii A. Temperature dependence of hot carrier effects in short-channel Si-MOSFETs. IEEE Trans Electron Dev 1995(42):2211–6. [31] Lu Chia-Yu, Lin Horng-Chih, Lee Yao-Jen, Shie Yu-Lin, Chao Chih-Cheng.

Impacts of LP-SiN capping layer on the device characteristics and hot carrier degradation of NMOSFETs. IEEE Trans Electron Dev Mater Reliab 2007;7:175–80.