Time-Multiplexing Current Balance Interleaved Current-Mode Boost DC-DC Converter for Alleviating the Effects of Right-half-plane Zero

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Time-Multiplexing Current Balance Interleaved

Current-Mode Boost DC-DC Converter for

Alleviating the Effects of Right-half-plane Zero

Yean-Kuo Luo, Yi-Ping Su, Yu-Ping Huang, Yu-Huei Lee, Student Member, IEEE,

Ke-Horng Chen, Senior Member, IEEE, and Wei-Chou Hsu, Member, IEEE

Abstract—In the present study, a time-multiplexing current

bal-ance (TMCB) current-mode boost converter is proposed to improve the transient performance. Generally, the crossover frequency of a conventional boost converter is limited to half or less than the right-half-plane (RHP) zero to ensure the system stability. The transient performance of a conventional boost converter is degraded due to its limited bandwidth. The proposed TMCB boost converter ex-tends its bandwidth and moves the RHP zero to a higher frequency to improve the transient performance using two inductors in one channel. Besides, the small signal model of dual phase system which considers cross-couple effect and offset correction is presented. The proposed converter requires an extra inductor and a slight increase in the size of the printed circuit board layout and die size. Using time multiplexing, two inductors were operated in an interleaved phase at a switching frequency of 5 MHz rather than a single induc-tor system operated at a switching of 10 MHz for the same ripple required. Experimental results show that the TMCB technique is effective in correcting the mismatch in the current of the inductors even if the difference between the inductors is large. Furthermore, the proposed converter can improve the settling time from 52 to 22 μs due to an extended bandwidth.

Index Terms—Boost converter, dc–dc power converter, dual

in-ductor single output boost converter, right-half-plane (RHP) zero, time-multiplexing current balance (TMCB).

I. INTRODUCTION

I

N recent years, various dc–dc converters, such as the buck, boost, and buck–boost converters, among others, have been used in power systems due to their high efficiency and ease of control. The boost converter, as shown in Fig. 1(a), is a commonly used converter used to convert a low input voltage to

Manuscript received November 29, 2011; revised January 16, 2012; accepted February 15, 2012. Date of current version May 15, 2012. This work was sup-ported by the National Science Council, Taiwan, under Grant NSC 100-2220-E-009-050 and Grant NSC 100-2220-E-009-055. Recommended for publication by Associate Editor Paolo Mattavelli.

Y.-K. Luo is with the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu 30041, Taiwan, and also with the Institute of Microelectronics, National Cheng Kung University, Tainan 70401, Taiwan (e-mail: yklou@aatech.com.tw).

Y.-P. Su, Y.-P. Huang, Y.-H. Lee, and K.-H. Chen are with the In-stitute of Electrical Control Engineering, National Chiao Tung Univer-sity, Hsinchu 30041, Taiwan (e-mail: k81369@yahoo.com.tw; kupmoon@ gmail.com; khchen@cn.nctu.edu.tw).

W.-C. Hsu is with the Institute of Microelectronics, National Cheng Kung University, Tainan 70401, Taiwan (e-mail: wchsu@eembox.ee.ncku.edu.tw).

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2188842

Fig. 1. (a) Conventional current-mode boost converter. (b) Proposed TMCB interleaved current-mode boost converter.

a higher output voltage. Especially for harvesting systems, such a low input voltage must be boosted to a higher voltage level for driving a complex next-stage.

In theory, the maximum bandwidth of a boost converter can be set to 1/10th or 1/15th of the switching frequency to obtain the best transient performance and stability [1]. However, when the output load, duty ratio, and inductor value are increased, the right-half-plane (RHP) zero moves toward low frequencies, and thus toward the crossover frequency ωT. The phase margin

(PM) and the system stability are greatly influenced by the low-frequency RHP zero given by

ωz (R H P)= D2R L , where D = 1− D, R = Vout Iload (1)

where Voutis the output voltage, Iloadis the output load current,

R is the output load resistance, and D is the duty cycle of the

pulsewidth modulation control.

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A number of studies have been made on eliminating or re-ducing the effects of the RHP zero [2]–[8]. Cho et al. [2] presented a method to eliminate the RHP zero by selecting the passive component value and satisfying the equation as follows:

RC · C > L

R· (1 − D) (2)

where RC is the equivalent series resistance (ESR) of the output

capacitance, C is the output capacitance, D is the duty cycle, L is the inductor, and R is the output load resistance.

The method was achieved using a large output capacitance with a very high ESR value.

Tristate and pseudo conduction current mode controls have been proposed to remove the RHP zero at the cost of an extra one power switch between the input and output nodes [3], [4]. A low switching frequency control [5] has been proposed to eliminate the RHP zero using a low switching frequency. The adaptive voltage position technique and modified hysteretic current con-trol have also been recommended to reduce the RHP zero effect and improve the transient response [6], [7].

The present study proposes an interleaved method with the time-multiplexing current balance (TMCB), as shown in Fig. 1(b), to move the RHP zero to higher frequencies compared with a conventional boost converter, as shown in Fig. 1(a). Al-though similar dual phase systems used voltage mode control have been proposed in [9], [10]. Those works focused on the high-power or high-current density application and the advan-tage of high speed is ignored. In addition, those models were presented based on the voltage mode control rather than the current mode control method. The value of the inductor can become half of that of the conventional design due to the in-terleaved operation of the preposed converter. Thus, the RHP zero can be moved to a higher frequency twice than that of the conventional design (see Fig. 2). Hence, the system bandwidth can be extended from ωT to ωT in order to achieve a fast

tran-sient response. The hardware overhead can be reduced using the proposed TMCB technique without sacrificing the performance of the current balance because the TMCB technique needs only one error amplifier similar to the conventional design. The out-put voltage ripple is guaranteed to be smaller than that of the conventional design if the current balance correctly works on the closed-loop.

Many works have presented the small-signal behavior of a switching converter [11]–[21]. Some studies and their related works have presented the voltage-mode interleaved buck con-verter or boost concon-verter [22]–[28]. In the current research, an analytic model of the current-mode interleaved boost converter with an average current balance is presented for system stability analysis.

The organization of this study is as follows. The interleaved operation with the TMCB technique is shown in Section II. The small-signal model and system stability analysis are pre-sented in Section III. The circuit implementation is described in Section IV. The experimental results are shown in Section V. Finally, a conclusion is drawn in Section VI.

Fig. 2. (a) Extended bandwidth of the proposed boost converter when the RHP zero is moved to higher frequencies. (b) Type II compensator.

Fig. 3. Determination of the duty cycle in the TMCB technique.

II. OPERATION OF THEINTERLEAVEDBOOSTCONVERTER

WITH THETMCB

The proposed interleaved boost converter needs two induc-tors L1 and L2 to move the RHP zero to higher frequencies. In addition, two Schottky diodes D1 and D2 are necessary for the simple implementation of asynchronous rectifiers. Phase I is the operation period of the master channel composed of L1,

D1, and a power MOSFET MN 1. Phase II is the operation

pe-riod of the slave channel composed of L2, D2, and a power MOSFET MN 2. It was difficult to ensure the perfect

match-ing between the two phases, and thus the current balance was worth. The TMCB technique was proposed to guarantee the cur-rent balance between the two phases. In the converter, a simple on-chip clock generator was built to provide a single clock with-out the synchronous issue between the two phases.

Similar to the conventional architecture, the duty cycle is determined using the comparison of the ramp signal VR am pand

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Fig. 4. If the driving current in phase I is larger than that in phase II, the TMCB technique adjusts the ramp slope of the phase II to increase the driving current in phase II when the operation is opposite in (a) and (b).

Fig. 5. Output ripple of the conventional boost converter: (a) when the duty cycle is less than 50%, (b) when the duty cycle is greater than 50%.

the error signal VEAO. The two phases share an error amplifier and a comparator. With a reduced hardware overhead, the dual-phase converter with a good current balance can achieve a fast transient response without being greatly affected by the RHP zero.

Fig. 6. Output ripple of the proposed boost converter: (a) when the duty cycle is less than 50%, (b) when the duty cycle is greater than 50%.

A. Compensation Design for Extending the Bandwidth

Fig. 2 shows the comparison of the bandwidth between the conventional and proposed converters. Usually, a Type II com-pensator is used to make the closed-loop transfer function sharp enough and ensure high low-frequency gain and adequate PM in a conventional current-mode boost converter. In the proposed converter, the compensation pole ωP 1 at the origin substitutes

the system pole, ωPS (i.e., 2/RCL) as the dominant pole. The

new compensator for the proposed interleaved design with the TMCB technique is designed to have a maximum ωT because the RHP zero ωR H PZ is located at high frequencies. Thus, a higher compensation pole and zero, ωZ 1and ωp2 , respectively, can be achieved because the interleaved method uses a small inductor.

B. Operation of the Proposed TMCB Technique for Current Balance

The transient response time can be improved by a higher crossover frequency. However, the current balance is another design issue that needs to be solved to ensure a fast transient response without having subharmonic oscillation or longer set-tling time problems. The subharmonic oscillation is due to the sampling effect if the unity gain frequency of the cur-rent balance loop approaches one-tenth of the switching fre-quency [18], [20], [21], [29]. Besides, the longer setting time problem is caused by low bandwidth or slow response current balance loop. The offset current between the two phases, still re-sults in the slave channel, affects the master channel even if the output voltage achieves its regulated value while the transient load is mainly supported by the master channel. The phenomena

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Fig. 7. Steady state analysis of the proposed converter in (a) state 1, (b) state 2 and state 4, and (c) state 3. (d) Duty ratio of the proposed converter.

Fig. 8. Simplified power stage model of the proposed converter when the duty cycles are equal for each channel.

Fig. 9. Equivalent power stage model of the proposed converter if the duty cycle is not equivalent in each channel.

are simulated and presented in Section III. In Fig. 3, the proposed TMCB technique uses a clock with the time-multiplexing idea to modulate the duty cycles of the two phases. This is based on the main concept that there are two interleaved ramps generated by the TMCB technique, as shown in Fig. 3.

The mismatches between the two phases can lead to an enormously unbalanced current distribution. Thus, the current balance circuit is demanded to compensate the mismatches for inductor current unbalancing [10]. The proposed TMCB technique was used to adjust the ramp slope for the current balance in dual-phase operation, as shown in Fig. 4.

As can be seen in Fig. 4(b), the current in phase I is larger than that in phase II. The decrease in ramp voltage can enlarge

Fig. 10. Block diagram for the proposed interleaved current mode boost converter.

the duty cycle and increase the current driving capability. On the contrary, the increase in ramp slope can lead to a smaller duty cycle and decrease the current driving capability. Therefore, the current balance can be achieved by comparing the voltage of the modified ramps with the same error signal.

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TABLE I

TRANSFERFUNCTIONS OF THEPROPOSEDCONVERTER

TABLE II

FEED-FORWARDGAIN ANDRELATIVEPARAMETERS OF THEPROPOSEDCONVERTER

C. Output Ripple Consideration

Low output ripple of dual-phase system is another advantage than single inductor system. Fig. 5 shows the output ripple of the conventional boost converter. The ripple voltage VR IPPLE con-tains the ripple from the ESR at the output capacitor VR IPPLE1 as well as the ripple VR IPPLE2 from the charging/discharging of the output capacitor. Fig. 5(a) and (b) shows the output ripple when the duty was less than 50% and greater than 50%, respec-tively. The output VR IPPLE contains the VR IPPLE1 regardless

of the duty. Fig. 6 shows the output ripple of the proposed con-verter. The diode current (ID 1+ID 2) was continuous when the

duty was less than 50%, as shown in Fig. 6(a). Due to the contin-uous diode current, the output ripple can be reduced to VR IPPLE2 during the charge/discharge phase compared with the conven-tional boost converter. Although the diode current (ID 1+ID 2)

was not continuous when the duty was greater than 50%, the output ripple of the proposed converter was still smaller than that of the conventional converter because the average inductor

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Fig. 11. Relationship between iL 1, iL 2, and VE A Oof the proposed converter.

current, as shown in Fig. 6(b), was half of that of the conventional converter. In addition, the discharge period TD ISC H A RG E, of the output capacitance was shorter than that shown in Fig. 5(b).

III. SMALLSIGNALMODEL

A. Simple Power Stage Model

From Fig. 1(a), the operation of the proposed converter can be classified into four states, as shown in Fig. 7. In state 1, as shown in Fig. 7 (a), the power switch MN 1 is ON with the increasing

inductor current IL 1. On the other hand, the power switch MN 2

is OFF when the inductor current IL 2ramps down to charge the

output capacitor CL.

In state 2, as shown in Fig. 7(b), MN 1and MN 2are OFF and

the inductor currents IL 1 and IL 2 ramp down to charge CL. In

state 3, as shown in Fig. 7(c), MN 1is OFF and inductor current

IL 1 ramps down to charge CL. MN 2 is ON, IL 2 is increased.

The status of state 4 is similar to that of state 2.

From the four states mentioned earlier, the state space equa-tion can be separately established as

˙x(t) = Anx(t) + Bnu(t) (3)

where x(t) is the state vector and expressed as

[ iL 1 iL 2 Vout], u(t) is the input vector defined as

Vin(t), and n is the state.

The on-resistance r1and r2of power switches MN 1and MN 2

are assumed to be identical to ra, which is the ESR of the output

capacitor, and on-resistance of diodes D1and D2are neglected in this case.

The node equation in state 1 can be expressed in the matrix form as follows: ⎡ ⎢ ⎣ ˙iL 1 ˙iL 2 ˙ Vout ⎤ ⎥ ⎦ = ⎡ ⎢ ⎣ −r1 L1 0 0 0 0 L1 2 0 1 CL 1 R CL ⎤ ⎥ ⎦ ⎡ ⎢ ⎣ iL 1 iL 2 Vout ⎤ ⎥ ⎦ +  1 L1 1 L2 0 [Vin]

The matrixes in states 2–4 can also be expressed in similar forms as follows: A2 = A4 = ⎡ ⎢ ⎣ 0 0 L1 1 0 0 L1 2 1 CL 1 CL 1 R CL ⎤ ⎥ ⎦ , A3 = ⎡ ⎢ ⎣ 0 0 1 L1 0 −r2 L2 0 1 CL 0 1 R CL ⎤ ⎥ ⎦ , and B1 = B2 = B3 = B4 =  1 L1 1 L2 0 .

For simplification, it was assumed that the duty ratios D1and

D3 in Fig. 7(d) have the same values in steady state. Hence, (4)–(6) can be derived as follows:

D1 = D3 = D (4) where D= (1− D) = (D2+ D3+ D4) = Vout Vin (5) and D1+ D2+ D3+ D4 = 1. (6)

According to the state-space averaged theory and ignoring the second-order nonlinear term, a linearized ac model can be ob-tained as follows:

ˆ

x(t) = Aˆx(t) + B ˆu(t) +{(Ad)X + (Bd)U} ˆd(t) (7)

where A is equal to(D1· A1+ D2· A2+ D3· A3+ D4· A4),

Ad is equal to (A1+ A3− A2− A4), B is equal to

(D1· B1+ D2· B2+ D3· B3+ D4· B4), and Bd is equal to

(B1+ B3− B2− B4).

The matrixes are expressed as follows:

A = ⎡ ⎢ ⎢ ⎣ 0 0 0 0 (D2+ D3+ D4) CL (D1+ D2+ D4) CL , −(D2+ D3+ D4) L1 −(D1+ D2+ D4) L2 −(D1+ D2+ D3+ D4) RCL ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ B =  1 L1 1 L2 0 , Ad = ⎡ ⎢ ⎢ ⎢ ⎢ ⎣ 0 0 1 L1 0 0 1 L2 1 CL 1 CL 0 ⎤ ⎥ ⎥ ⎥ ⎥ ⎦, and Bd = 0.

In the scalar form, the vectors in (7) can be expressed as follows:

L1 dˆiL 1(t) dt = ˆVin(t)− D Vˆ out(t) + (Vout) ˆd(t) (8) L2 dˆiL 2(t) dt = ˆVin(t)− D Vˆout(t) + (Vout) ˆd(t) (9)

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Fig. 12. (a) Bode plot of the master channel. (b) Bode plot of the slave channel. (c) Bode plots of the conventional and the proposed converter. CL d ˆVout(t) dt = D ˆi L 1(t) + ˆiL 2(t) −Vˆout(t) R − (IL 1+ IL 2) ˆd(t). (10)

Consequently, the equivalent circuit model can be constructed, as shown in Fig. 8. Vin+ ˆvin is the input voltage with the

per-turbation, L1 and L2are the inductor values, Vout+ ˆvoutis the output voltage with the perturbation, IL 1 and IL 2 are the dc

inductor currents, D is the duty cycle in steady state, R is the equivalent loading resistance, and CLis the output capacitance.

Using the simplified power stage model, the RHP zero can be derived as (11), and the effective inductor value is reduced to half of the original value. The effective inductor value is

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Fig. 13. Simulation waveforms of the single channel converter and the proposed interleaved converter. TABLE III

DESIGNPARAMETERS ANDSIMULATIONCONDITIONS

different from the result, which is equal to one, obtained by Xu

et al. [10]. In addition, the RHP zero in the interleaved converter

is half of that in the conventional single inductor boost converter

ωZ (R H P) = D2R L1//L2

. (11)

B. Power Stage Model With Unequal Duty Cycle

If the duty cycles are not equal in each channel, the equiv-alent power stage model is modified, as shown in Fig. 9. The parameter definitions ˆd1and ˆd2 are the perturbations for each channel, ZL is the impedance seen at the output node, and the

rest parameters are defined as previously discussed.

According to the equivalent power stage model, the individual duty-to-output transfer function Gvd and the duty-to-inductor-current transfer function Gid can be derived. Furthermore, the cross-couple term of the duty-to-other-inductor-current transfer function G(1)idx implies how the duty of the master channel d1 affects the slave channel inductor current iL 2. On the other hand,

the cross-couple term of the duty-to-other-inductor-current G(2)idx implies how the duty of the slave channel d2 affects the master channel inductor current iL 1. With a carefully designed current

balance mechanism, the average of each channel was mostly

kept similar to each other, and the bandwidth of the TMCB was wide enough without affecting the transient response.

The duty-to-output transfer function of the master channel

G(1)vd can be obtained when the independent voltage Vinand d2 are assumed to be shorted to the ground and zero, respectively. Similarly, the duty-to-output transfer function of the slave chan-nel G(2)vd can be derived. In addition, using the KCL theorem, the net current at the output node is zero. The cross-couple term of duty-to-other-inductor-current transfer functions, G(1)idx and

G(2)idx, can be obtained. Table I shows the summary of the power stage model transfer function of the proposed converter.

C. Controller Model and Transfer Function of the Proposed Converter

Fig. 10 shows the block diagram of the proposed interleaved current model boost converter. The block diagram is composed of three parts, including the converter power stage, and the con-troller models of master and slave channels. The power stage transfer functions are shown in Table I. In addition, the con-troller block diagrams can be determined using the relationship of the control signal VEAO and inductor currents IL 1 and IL 2.

Two separate controller models are necessary to model the dif-ferent values of duty cycle or the inductor of each channel. Moreover, the TMCB mechanism is derived and included in the slave channel controller model. As can be seen in Fig. 10,

R(1), R(2), and R(2)

b are the current-to-voltage ratios; ˆVC is the

small-signal part of the VEAO. A(2)b (s) is the transfer function

of the current balance mechanism, including the error ampli-fier and the compensator. Fg(1), Fg(2), Fv(1), and Fv(2) are the

feed-forward term from the input or the output voltage to the duty cycle; and Fm(1) and Fm(2) are the modulation gains of the

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Fig. 14. (a) Simulation waveforms of the TMCB mechanism with a low-gain Ab( 2 )(s). (b) Simulation waveforms with a suitable design of the TMCB. (c) Simulation waveforms of the TMCB with an ultrahigh bandwidth.

shows the summary of the feed-forward gain of the proposed converter.

Fig. 11 shows the relationship between iL 1, iL 2, and VEAOof the proposed converter. Due to the current balance mechanism, the average inductor current of iL 1and iL 2can be forced to have

similar values with a pseudo average current modification term

Ibal. According to the relationship shown in Fig. 11, Ibal can

be expressed by M1A and M1B shown in Table II. In addition,

Fg(2), Fv(2), and Fm(2)) can be obtained after the process of

per-turbation and linearization. The modulation gain Fm(2) and the

feed-forward gains Fg(2)and Fv(2)are different from those in the

master channel due to the TMCB mechanism. The difference came from the modulation gain has the M1Aand the M2Ain the denominator.

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Fig. 15. Bode plot of current balance loop in closed form.

Fig. 16. Schematic diagram of the TMCB circuit.

Fig. 17. Schematic diagrams of the internal oscillator and ramp generator.

As can be seen in Fig. 10, the control-to-output voltage in the closed-loop transfer function of the master channel TC L M can

be derived as (12) to determine the stability of the master chan-nel, as shown (12), at the bottom of this page. The closed-loop

Fig. 18. Chip micrograph of the proposed converter.

transfer function of the slave channel TC L S can also be derived

as (13), shown at the bottom of the next page. The transfer func-tion TC L S is used to verify the stability of the slave channel

with the TMCB mechanism. The closed-loop transfer function of the proposed converter TC L T is the summation of (12) and

(13). Besides, the closed-loop transfer function of the current balance loop iL 2/iL 1is expressed in (14), and (15) expresses the

sampling effect at high frequency. Fig. 12(a) and (b) shows the Bode plots of the master and slave channels, respectively, using MATLAB. The simulation conditions and design parameters are summarized in Table III. Fig. 12(c) shows the Bode plots of the proposed converter and conventional single channel converter at the same loading of 400 mA. The proposed converter has a higher bandwidth compared with the conventional converter because the proposed converter has a higher loop gain derived

TC LM = Fm(1)· R(1) G(1)id Fm(1)/G(1)vd −G(2)idx· Fm(1)/G(2)vd − F(1) v Fm(1)+ (1/G(1)vd) . (12)

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Fig. 19. Switching waveform of the TMCB boost converter with (a) a loading of 150 mA and (b) a loading of 300 mA.

from the summation of the master and slave channels

Ibalance = ˆi2 ˆi1 = Aa(s) F (2) m G(2)id He(s) + (G(1)idx/G(1)id ) Aa(s) Fm(2)G(2)id He(s) + Fm(2)G(2)id + 1 (14) He(s) = 1 1 + (2s/TS) + (s22TS2) . (15)

Fig. 13 shows the simulation waveforms of the conventional converter and the proposed interleaved converter when the load current was increased from 300 to 600 mA. The output voltage of the proposed converter has better transient response than that of the single channel converter. The simulation results demonstrate the correction of the earlier analytic small-signal analysis.

The design of the TMCB is an important factor in the perfor-mance of the transient response. As mentioned earlier, a con-verter with a low bandwidth design in the TMCB leads to a slow transient response. Consequently, a converter with an ultrahigh bandwidth results in a subharmonic oscillation. Fig. 14 shows

the simulation results of the transient response under the influ-ence of the TMCB at the same load current condition of 300 mA and an inductor value of 0.47 μH. Fig. 14(a) shows a poor de-sign example of TMCB wherein the current is unbalanced with a low gain A(2)b . On the other hand, Fig. 14(b) shows a converter with a suitable bandwidth design. However, Fig. 14(c) shows a converter with an ultrahigh bandwidth wherein a subharmonic oscillation occurs. The subharmonic oscillation is due to a too high bandwidth of current balance loop. The sampling effect should be considered together when the bandwidth approaches one-tenth of the switching frequency. Fig. 15 is the Bode plot of current balance loop in closed-loop form. It shows that the sampling effect appears when the bandwidth is extended to an enough high frequency as the gm increases.

IV. CIRCUITIMPLEMENTATION

Fig. 16 shows the schematic diagram of the TMCB circuit. The current sensor estimates the current of each channel to

TC L S= 1 (1/Fm( 2 )G ( 2 ) v d) + R ( 2 ) a (G ( 1 ) id x/G ( 1 ) v d) + R ( 2 ) a (G ( 2 ) id x/G ( 2 ) v d) (G( 1 )id /G( 1 )v d) + (G( 2 )id x/G( 2 )v d)− (G( 1 )id x/G( 1 )v d) + (G( 2 )id /G( 2 )v d) R( 2 )b Ab(s)− F ( 2 ) v (13)

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Fig. 20. (a) Measurement results of the load transient response in the conventional boost converter. (b) Measurement results of the load transient response in the proposed TMCB boost converter.

Fig. 21. Current balance turn-on waveform of the proposed converter.

obtain Is 1 and Is 2 for indicating the inductor current level in

phase I and phase II, respectively. The switching operation causes the fluctuation on the values of Is 1 and Is 2. Thus, the

sample and hold circuit were adopted to obtain the average val-ues of VSH 1and VSH 2to represent Is 1and Is 2, respectively. To

obtain a better current balance operation, summation and di-vider circuits were used to generate the average channel current

VAVG through VSH 1and VSH 2.

The current adjustment circuit is composed of two operational transconductance amplifiers, OTA1 and OTA2, to amplify the difference between VAVG and VSH 1 (or VSH 2) to produce the current balance signal IC B 1 (or IC B 2). Each signal is injected

into the ramp generator to modify VSen2 of phase II for the current balance. As mentioned in the TMCB technique, the ramp voltage was adjusted using the time-multiplexing method. The outer voltage and inner current loops simultaneously exist in the closed loop. To ensure loop stability, the outer voltage loop must dominate the whole system in the multiphase operation wherein the voltage loop gain is higher than the current balance loop gain.

The embodied ramp generator circuit produces a voltage

VSen2 from the charging and discharging the capacitor CR to

determine the duty cycle. The charging and discharging cur-rents are I1 and I2, respectively. Therefore, the current balance signals, IC B 1 and IC B 2, can be injected into the CR for the

ramps in phase II. The higher value of IC B 2 contributes to a higher ramp voltage leading to a reduced value duty cycle and a lower IC B 2results in a large duty cycle. The time-multiplexing control with modulated ramp amplitude can be easily achieved using a multiplexer. Unlike in the conventional interleaved ar-chitecture, all phases in the proposed converter share the same clock based on the time-multiplexing scheme. It can also elimi-nate the inevitable mismatch between multiple controllers using a single controller, and thus improving the accuracy of current sharing.

Ideally, the bandwidths of both loops must be as large as possible to accelerate the transient response. However, enlarging

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TABLE IV

SPECIFICATIONS OF THEPROPOSEDBOOSTCONVERTER

TABLE V

COMPARISONBETWEEN THEPROPOSED AND THECONVENTIONALTOPOLOGIES

the bandwidth of the current balance loop leads to a subharmonic oscillation because the bandwidth of the current balance loop (or sample and hold) is too closed to one-tenth of the switching frequency, and the inductor current ripple cannot be ignored. This phenomenon makes VSen2unstable with a constant value. On the other hand, a small bandwidth of the current balance loop leads to a longer transient time because VSen2cannot reach its stable value, and the loading is immediately supplied by the master channel. Although the master channel has supplied the loading and balanced, it is still affected by slave channel while the current balance loop is unbalanced.

Fig. 17 shows the schematic diagram of the internal oscillator and the frequency divider and the waveforms. The internal os-cillator is composed of constant current source P47, comparator

X3, and capacitance C7. The sawtooth is generated by

charg-ing/discharging C7 when the sawtooth voltage is less than the

VH or greater than the VL, respectively. A D flip-flop, which

is a simple frequency divider, was used to generate two inter-leaved clocks, the CLKM asterand the CLKSlave. The waveforms of each signal are shown in Fig. 17.

V. EXPERIMENTALRESULTS

The proposed TMCB current-mode boost converter was fab-ricated in a 0.3-μm 5-V/18-V CMOS 2P3M process. The input voltage was about 3.1–3.3 V and the output voltage was 4.5 V. The chip area was 1350× 1380 μm2. The internal clock gener-ator was 10 MHz and each interleaved channel was operated at 5 MHz. The inductor value was 0.47 μH, and the output capaci-tance was 20 μF with an ESR of 10 mΩ. Fig. 18 shows the chip micrograph of the proposed TMCB boost converter. The power MOSFETs, MN1and MN2, are located at the left-top corner for easy wire bonding.

Fig. 19 shows the measurement results of the proposed TMCB boost converter. The load currents were 150 and 300 mA as

shown in Fig. 19(a) and (b), respectively. The accurately inter-leaved operation demonstrates that each channel can operate at a switching frequency of 5 MHz.

Fig. 20(a) shows the measurement results of the load transient response in a conventional boost converter if the load current is changed from 400 to 600 mA, or vice versa. The input and the output voltages were 3.3 and 4.5 V, respectively. The light-to-heavy and heavy-to-light settling times were 52 and 54 μs, respectively. On the other hand, as shown in Fig. 20(b), the light-to-heavy and heavy-to-light settling times improved to about 22 and 25 μs, respectively, due to the large bandwidth and dual-phase operation. The output voltage ripple was effectively reduced to about half of that of conventional design because the proposed TMCB technique ensured a good current balance between the two phases.

To show the effective current balance contributed by the TMCB technique, the two inductors, L1 and L2, were set to 0.47 and 1.2 μH, respectively. The mismatch between the two inductors was about 153%. The TMCB technique was switched ON to start the current balance between the two phases, as shown in Fig. 21. Finally, the two phases can drive the same current to the output even there was a large mismatch between the two inductors. Table IV shows the specifications of the pro-posed converter, and Table V shows the comparison between the proposed and the conventional boost converters. The proposed boost converter has a better transient response than the conven-tional converter due to a higher frequency RHP zero. Moreover, the compensator can be modified to have a larger bandwidth.

VI. CONCLUSION

In the current study, the proposed TMCB boost converter has been shown to be capable of providing a topology that reduces the output ripple and the effects of the RHP zero. A small and effective inductor value can move the RHP zero to

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higher frequencies, thus allowing the bandwidth to be extended to a higher value. In addition, the proposed TMCB technique is demonstrated and the current mode ac model with the couple effect is presented. The test chip uses the 0.3-μm 5-V/18-V CMOS technology. Experimental results demonstrate that the proposed converter can improve the transient response from 22 to 52 μs.

ACKNOWLEDGMENT

The authors would like to thank the Advanced Analog Tech-nology, Inc. and Chunghwa Picture Tubes, Ltd., for their help.

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Yean-Kuo Luo was born in Tainan, Taiwan. He

re-ceived the B.S. and M.S. degrees from the Institute of Microelectronics, National Cheng-Kung University, Tainan, in 2001 and 2003, respectively, where he is currently working toward the Ph.D. degree.

He is a Faculty Member in the Mixed Signal and Power Management IC Laboratory, Institute of Elec-trical Control Engineering, National Chiao Tung Uni-versity, Hsinchu, Taiwan.

Yi-Ping Su was born in Taipei, Taiwan. She received

the B.S. degree from the Department of Electrical En-gineering, National Sun Yat-Sen University, Kaohsi-ung, Taiwan, in 2009. She is currently working toward the Ph.D. degree at the Institute of Electrical Engi-neering, National Chiao Tung University, Hsinchu, Taiwan.

She is a Faculty Member in the Mixed Signal and Power Management IC Laboratory, Institute of Elec-trical Engineering, National Chiao Tung University. Her current research interests include the power man-agement integrated circuits design, battery charging integrated circuits design, and analog integrated circuits design.

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Yu-Ping Huang was born in Taipei, Taiwan. She

re-ceived the B.S. degree from the Department of Elec-trical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2009, where she is currently working toward the M.S. degree at the In-stitute of Electrical Control Engineering.

She is a member of the Mixed Signal and Power Management IC Laboratory, National Chiao Tung University. Her research interests include the design of power management circuit, battery charging ICs, and the analog integrated circuit designs.

Yu-Huei Lee (S’09) was born in Taipei, Taiwan. He

received the B.S. and M.S. degrees from the Depart-ment of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2007 and 2009, respectively, where he is currently working to-ward the Ph.D. degree at the Institute of Electrical Control Engineering.

He is a Faculty Member in the Mixed-Signal and Power Management IC Laboratory, Institute of Electrical Control Engineering, National Chiao Tung University. His current research interests include the power management integrated circuit design, LED driver IC design, and analog integrated circuits.

Ke-Horng Chen (M’04–SM’09) received the B.S.,

M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.

From 1996 to 1998, he was a Part-Time IC De-signer at Philips, Taipei. From 1998 to 2000, he was an Application Engineer at Avanti, Ltd., Tai-wan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was involved in designing power management ICs. He is currently a Professor with the Department of Electrical Engineering, Na-tional Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 100 papers published in journals and conferences, and holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display TV, RGB color sequential backlight designs for optically compensated bend panels, and low-voltage circuit designs.

Dr. Chen has served as an Associate Editor of the IEEE TRANSACTIONS ONPOWERELECTRONICSand the IEEE TRANSACTIONSONCIRCUITSAND SYSTEMS—PART II:EXPRESS BRIEFS. He is with the IEEE Circuits and Sys-tems (CAS) VLSI SysSys-tems and Applications Technical Committee, and the IEEE CAS Power and Energy Circuits and Systems Technical Committee.

Wei-Chou Hsu (M’87) was born in Taichung,

Tai-wan, on May 28, 1957. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Na-tional Cheng Kung University (NCKU), Tainan, Tai-wan, in 1979, 1981, and 1984, respectively.

In 1979, he passed the National Higher Civil Ser-vice Examination and received the Technical Expert License of the Republic of China in electrical engi-neering. In 1983, he was with Four Dimensions Com-pany, CA, as an Engineer. From 1982 to 1985, he was an Instructor with the Department of Electrical Engi-neering, NCKU, where he has been an Associate Professor since 1985. From 1991 to 1992, he was a Postdoctoral Researcher with the Department of Electri-cal Engineering, University of Florida, Gainesville. Since 1993, he has been a Professor with the Department of Electrical Engineering, NCKU. During 2000– 2005, he was the Associate Chair with the Department of Electrical Engineering, NCKU, and the Chair of the Institute of Microelectronics, NCKU. During 2005– 2008, he was the Chair of the Department of Electrical Engineering, NCKU. Since 2008, he has been the Chair of the Advanced Optoelectronic Technology Center, NCKU. His research interests include metal–organic chemical vapor deposition and molecular-beam-epitaxy-grown pseudomorphic heterostructure field-effect transistors (FETs), d-doped FETs, high-power FETs, heterojunc-tion bipolar transistors, organic light-emitting diodes, and organic photovoltaic devices.

數據

Fig. 1. (a) Conventional current-mode boost converter. (b) Proposed TMCB interleaved current-mode boost converter.
Fig. 1. (a) Conventional current-mode boost converter. (b) Proposed TMCB interleaved current-mode boost converter. p.1
Fig. 3. Determination of the duty cycle in the TMCB technique.
Fig. 3. Determination of the duty cycle in the TMCB technique. p.2
Fig. 2. (a) Extended bandwidth of the proposed boost converter when the RHP zero is moved to higher frequencies
Fig. 2. (a) Extended bandwidth of the proposed boost converter when the RHP zero is moved to higher frequencies p.2
Fig. 5. Output ripple of the conventional boost converter: (a) when the duty cycle is less than 50%, (b) when the duty cycle is greater than 50%.
Fig. 5. Output ripple of the conventional boost converter: (a) when the duty cycle is less than 50%, (b) when the duty cycle is greater than 50%. p.3
Fig. 6. Output ripple of the proposed boost converter: (a) when the duty cycle is less than 50%, (b) when the duty cycle is greater than 50%.
Fig. 6. Output ripple of the proposed boost converter: (a) when the duty cycle is less than 50%, (b) when the duty cycle is greater than 50%. p.3
Fig. 4. If the driving current in phase I is larger than that in phase II, the TMCB technique adjusts the ramp slope of the phase II to increase the driving current in phase II when the operation is opposite in (a) and (b).
Fig. 4. If the driving current in phase I is larger than that in phase II, the TMCB technique adjusts the ramp slope of the phase II to increase the driving current in phase II when the operation is opposite in (a) and (b). p.3
Fig. 10. Block diagram for the proposed interleaved current mode boost converter.
Fig. 10. Block diagram for the proposed interleaved current mode boost converter. p.4
Fig. 9. Equivalent power stage model of the proposed converter if the duty cycle is not equivalent in each channel.
Fig. 9. Equivalent power stage model of the proposed converter if the duty cycle is not equivalent in each channel. p.4
Fig. 8. Simplified power stage model of the proposed converter when the duty cycles are equal for each channel.
Fig. 8. Simplified power stage model of the proposed converter when the duty cycles are equal for each channel. p.4
Fig. 7. Steady state analysis of the proposed converter in (a) state 1, (b) state 2 and state 4, and (c) state 3
Fig. 7. Steady state analysis of the proposed converter in (a) state 1, (b) state 2 and state 4, and (c) state 3 p.4
TABLE II

TABLE II

p.5
Fig. 11. Relationship between i L 1 , i L 2 , and V E A O of the proposed converter.
Fig. 11. Relationship between i L 1 , i L 2 , and V E A O of the proposed converter. p.6
Fig. 13. Simulation waveforms of the single channel converter and the proposed interleaved converter
Fig. 13. Simulation waveforms of the single channel converter and the proposed interleaved converter p.8
Fig. 10 shows the block diagram of the proposed interleaved current model boost converter
Fig. 10 shows the block diagram of the proposed interleaved current model boost converter p.8
Fig. 14. (a) Simulation waveforms of the TMCB mechanism with a low-gain A b ( 2 ) (s)
Fig. 14. (a) Simulation waveforms of the TMCB mechanism with a low-gain A b ( 2 ) (s) p.9
Fig. 17. Schematic diagrams of the internal oscillator and ramp generator.
Fig. 17. Schematic diagrams of the internal oscillator and ramp generator. p.10
Fig. 16. Schematic diagram of the TMCB circuit.
Fig. 16. Schematic diagram of the TMCB circuit. p.10
Fig. 15. Bode plot of current balance loop in closed form.
Fig. 15. Bode plot of current balance loop in closed form. p.10
Fig. 19. Switching waveform of the TMCB boost converter with (a) a loading of 150 mA and (b) a loading of 300 mA.
Fig. 19. Switching waveform of the TMCB boost converter with (a) a loading of 150 mA and (b) a loading of 300 mA. p.11
Fig. 13 shows the simulation waveforms of the conventional converter and the proposed interleaved converter when the load current was increased from 300 to 600 mA
Fig. 13 shows the simulation waveforms of the conventional converter and the proposed interleaved converter when the load current was increased from 300 to 600 mA p.11
Fig. 21. Current balance turn-on waveform of the proposed converter.
Fig. 21. Current balance turn-on waveform of the proposed converter. p.12
Fig. 20. (a) Measurement results of the load transient response in the conventional boost converter
Fig. 20. (a) Measurement results of the load transient response in the conventional boost converter p.12
TABLE IV

TABLE IV

p.13

參考文獻