A low-power design for Reed-Solomon decoders

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World Scientiﬁc Publishing Company

A LOW-POWER DESIGN FOR REED SOLOMON DECODERS

HSIE-CHIA CHANG and CHEN-YI LEE

Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, 300, Republic of China

Received 15 April 2002 Accepted 15 July 2002

In this paper, a low-power design for the Reed–Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modiﬁed Berlekamp–Massey algorithm in the key equa-tion solver and a terminated mechanism in the Chien search circuit. The test chip for (255, 239) and (208, 192) RS decoders are implemented by 0.25 µm CMOS 1P5M and 0.35 µm CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average. Keywords: Low-power design; Reed–Soloman codes; two-stage syndrome calculator; Berlekamp–Massey algorithm; Euclidean algorithm.

1. Introduction

Among the most well-known error-correcting codes, the Reed–Solomon (RS) codes are undoubtedly the most widely used block codes in communications and storage systems to enhance the immunity to burst errors. An (N, K) RS cod e contains N coded symbols with K message symbols in each codeword, and is capable of correcting up to t =(N − K)/2 symbol errors, where each symbol belongs to the ﬁnite ﬁeld.1_{Due to the increasing demand for high capacity communication systems} and portable wireless applications, low-power implementations of RS decoders are desirable to meet higher data rates for system-level integration.

The most popular RS decoder architecture can be summarized into four steps: (1) calculating the syndromes from the received codeword, (2) computing the error locator polynomial andthe error evaluator polynomial, (3) ﬁnding the error loca-tions, and(4) computing error values. The secondstep in the four-step procedure involves solving the key equation,2_{which is}

Ω(x) = S(x)σ(x) mod x2t, (1)

where S(x) represents the syndrome polynomial, σ(x) is the error locator polyno-mial, andΩ(x) is the error evaluator polynomial. As a consequence, existing RS de-coders usually contain a syndrome calculator, a key equation solver, a Chien search,

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Data Error Value Evaluator

Chien Search Key Equation Solver Syndrome Calculator σσσσ(x) Ω Ω Ω Ω(x) Received Data Memory

R(x)

Fig. 1. Reed–Solomon decoding ﬂowchart.

andan error value evaluator, which are illustratedin Fig. 1. The syndrome calcula-tor generates a set of syndromes from the received codeword polynomial R(x). From the syndromes, the key equation solver produces the error locator polynomial σ(x) andthe error evaluator polynomial Ω(x), which can be usedby the Chien search andthe error value evaluator to determine the error locations anderror values, respectively. The receiveddata memory is usedto store the receivedsymbols. In accordance with the error value and its location, the output of the ﬁnite-ﬁeld adder shown in Fig. 1 is the corresponding corrected symbol.

While implementedfor portable storage systems or optical communications with higher data rates, all existing RS decoders cause relatively large power consump-tion, leading to difficulty in system-level integration. As a result, we propose a low-power design for RS decoders using a novel two-stage syndrome calculator, which is addressed in Sec. 2, to detect whether the received codeword carrying errors. If there is no error occurring, the power consumption can be reduced sig-nificantly by terminating the follow-up decoding procedure. Section 3 illustrates a modified Berlekamp–Massey algorithm to reduce many unnecessary calculation counts andSec. 4 describes the Chien search with the terminatedmechanism and an area-efficient architecture for the error value evaluator. The (255, 239) as well as (208, 192) RS decoder are implemented as the design examples and simulation results are shown in Sec. 5. Finally, the conclusion is given in Sec. 6.

2. The Novel Syndrome Calculator

By deﬁnition, the syndrome polynomial S(x) is denoted as S1+S2x+· · ·+S2tx2t−1, where Si= R(αi) with the receivedpolynomial R(x) = R0+R1x+· · ·+RN₋₁xN−1 in (N, K) RS codes. If the received codeword contains no errors, it can be shown that all syndromes, S1 through S2t, will all equal zeros. From the relations between syndromes and the coeﬃcients of the error locator polynomial σ(x) given by3_:

      S1 S2 · · · Sν S2 S3 · · · Sν+1 .. . ... Sν Sν+1 · · · S2ν₋₁             σν σν₋₁ .. . σ1      =       −Sν+1 −Sν+2 .. . −S2ν      ,

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R(x)=

R₀, R₁, . . . , R_N-1 S_i

xαi

(a)

Received Data Memory

S_9 S_10 S_16 ... R(x) m m m S_1 S_2 S_8 ... 8 _{R_enb} (b)

Fig. 2. (a) Syndrome calculator cell S i. (b) Proposed two-staged structure of the syndrome calculator over GF (2m_{) for t = 8.}

Sν+1, Sν+2, . . . , and S2ν will be all zeros if both ν≤ t and S1= S2=· · · = Sν= 0, where ν represents the number of actual errors and t is the number of correctable errors. Therefore, the ﬁrst half of the syndromes can be seen as an error detector. Once there are t continuous syndromes equaling zeros, all 2t syndromes will equal zeros. Then the follow-up decoding procedure can be terminated and all error values are set to zeros directly whether no-error (ν = 0) codeword or out-of-correction codeword (ν > t) received. The novel syndromes calculating procedure can be shown as follows:

Let continue = FALSE ; For (i = 1 to t) { Calculate Si; If (Si= 0) continue = TRUE ; } IF (continue = TRUE) { For(i = t + 1 to 2t) Calculate Si; } Else Finish;

The syndrome calculator cell S i is shown in Fig. 2(a), where the partial syn-drome is multiplied with αi _{andaccumulatedwith the receivedsymbol at each} cycle. After all receivedsymbols from RN−1 to R0are processed, the accumulated result is the ith syndrome, Si. In Fig. 2(b), the proposedtwo-stagedstructure of the syndrome calculator is illustrated for t = 8. After N cycles, the syndromes S1 through S8 are obtainedandthen the signal R enb is usedto control the access of the data memory. The syndrome calculator cells S 9 through S 16 will remain idle except the controlling signal R enb goes to high.

Moreover, the look-forwardarchitecture4_{can be usedto improve the throughput} rate. For example, the process of calculating the ith syndrome in (255, 239) RS codes

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S

_i xα3i xα2i xαi xα4i

R

₂

, . . . , R

₂₅₀

, R

₂₅₄

R

₃

, . . . , R

₂₅₁

, 0

R

₁

, . . . , R

₂₄₉

, R

₂₅₃

R

₀

, . . . , R

₂₄₈

, R

₂₅₂

Fig. 3. Syndrome calculator cell of S i using the look-forward architecture. Note that R255= 0

in the (255, 239) RS code. can be derived as Si= 63 j=0 (R4j+ R4j+1x + R4j+2x2+ R4j+3x3)x4j x=αi . (2)

The syndrome calculator cell S i using the look-forwardarchitecture to process four symbols per cycle is illustratedin Fig. 3. At each cycle, the partial syndrome is multipliedwith α4i_{, accumulatedwith the receivedsymbols andtheir multiplying} results of αi to α3i in parallel. After all the receivedsymbols are processed, the accumulatedresult is Si. Thus, our proposedtwo-stage syndrome calculator can be also appliedto applications of higher data rate.

Note that the finite-fieldmultipliers (FFMs) implementedin the syndrome cal-culator are all constant–variable FFMs, which have one input as a constant and the other input as a variable, indicating that the circuit complexity and power con-sumption are much lower than that of variable–variable FFMs, whose inputs are both variables. Since the transmission data in realistic systems are almost correct (i.e., S1 = S2 =· · · = St= 0), our proposal reduces by almost half the syndrome computations, leading to a good effect on the power consumption of the entire RS decoder.

3. The Key Equation Solver

The techniques frequently usedto solve the key equation include the Berlekamp– Massey (BM) algorithm2,5 _{andthe Euclid}_{ean algorithm.}6 _{The BM algorithm is} generally considered to be the one with the least hardware complexity for solving the key equation. Another advantage is that the constant term of σ(x) and Ω(x) always equals 1 and S1, suggesting an efficient decoding procedure to eliminate redundant computations in the BM algorithm. However, the BM algorithm is an iterative procedure and after calculating the first iteration in advance, the modified BM algorithm with some differences in initial conditions can be shown as follows:

Initialcondition: δ = ∆(0)_{= S}

1, D(0)(x) = 1 , σ(0)_{(x) = 1 + S}

1x , τ(0)(x) = Ω(0)(x) = γ(0)(x) = 1 ,

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For (i = 1 to 2t− 1) ∆(i)_{(x) = S} i+1+ Siσ (i₋₁₎ 1 +· · · + Si_−t+1σ (i₋₁₎ t , (3) σ(i)_{(x) = σ}(i−1)_{(x) +} ∆ (i) δ xτ (i−1)_{(x) ,} ₍₄₎ Ω(i)_{(x) = Ω}(i−1)_{(x) +}∆ (i) δ xγ (i−1)_{(x) ,} ₍₅₎ If (∆(i)_{= 0 or 2D}(i₋₁₎_{≥ i + 1)} D(i)= D(i−1), τ(i)(x) = xτ(i−1)(x) , γ(i)(x) = xγ(i−1)(x) , Else D(i)_{= i + 1}_{− D}(i−1)_, _{δ = ∆}(i)_, τ(i)_{(x) = σ}(i−1)_{(x) ,} _γ(i)_{(x) = γ}(i−1)_{(x) ,}

where σ(i)_{(x) is the ith error locator polynomial, Ω}(i)_{(x) is the ith error evaluator} polynomial, and σj(i)’s are the coeﬃcients of σ

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(x); ∆(i)is the ith discrepancy and δ is the previous discrepancy; D(i)is an auxiliary degree variable in the ith iteration, and τ(i−1)_{(x) and γ}(i−1)_{(x) are auxiliary polynomials for calculating σ}(i)_{(x) and} Ω(i)(x), respectively. Note that the ith error locator polynomial σ(i)(x) calculated by Eq. (4) will be equal to the previous polynomial σ(i−1)_{(x) if ∆}(i) _{= 0. After 2t−1} iterations, σ(2t₋₁₎_{(x) and Ω}(2t₋₁₎_{(x) are equivalent to the error locator polynomial} σ(x) andthe error locator polynomial Ω(x), respectively.

The conventional way to compute the error evaluator polynomial Ω(x), shown as above, is to do it in parallel with the computation of σ(x). From the key equation andNewton’s identity, the computation of Ω(x) can be shown as follows:

Ω(x) = S(x)σ(x) mod x2t = Ω0+ Ω1x +· · · + Ω(t₋₁₎xt−1, (6) ⇒ Ω0= S1, Ω1= S2+ S1σ1, .. . Ωt−1= St+ St−1σ1+· · · + S1σt−1,

where Ωj’s are the coeﬃcients of the error evaluator polynomial Ω(x). Note that the proposed direct computation of Ω(x) after σ(x) is computedrequires fewer multiplications and additions than the original BM algorithm. Table 1 compares the average calculation counts between the original Euclidean and BM algorithm with the modiﬁed BM algorithm after many random test patterns are simulated.

In addition, the computation of the ith coefficient Ωiis similar to that of the ith discrepancy ∆(i)_{. Therefore, the same hardware used to compute ∆}(i) _{can be} recon-figured to compute the coefficient Ωi. Depending on the implementation, there are

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Table 1. Comparison of calculation counts in diﬀerent architectures.

Type Euclidean6 BM2,5 Modiﬁed BM

Division 8.92 4.44 4.44 Addition 156.07 113.43 94.55 Multiplication 155.15 121.30 94.54 Mod m

...

σσσσ1 S_i+1 2m-1 Bit-wise Mul Mod m σσσσ2 2m-1 Bit-wise Mul S_i S_i-1 S_i-t+1 Mod m σσσσt 2m-1 Bit-wise Mul m ∆∆∆∆(i) _or m ΩΩΩΩ i (a) Mod m ∆∆∆∆(i) _or m 2m-1 σσσσ1 2m-1 Bit-wise Mul σσσσ2 2m-1 Bit-wise Mul S_i S_i-1 S_i-t+1 σσσσt 2m-1 Bit-wise Mul

...

S_i+1 Ω ΩΩ Ωi (b)

Fig. 4. (a) Original approach for calculating ∆(i)_{or Ω}

i. (b) Separated approach for calculating

∆(i)_{or Ω} i.

two different approaches illustrated in Fig. 4 to compute ∆(i) or Ωi over GF (2m).7 From the finite-fieldarithmetic, the multiplication of two operands can be split into a bit-wise multiplying operation anda modular operation. In Fig. 4(a), the origi-nal approach indicates that each multiplier requires both the bit-wise multiplying operation andthe modular operation. However, the separated approach, shown as Fig. 4(b), reduces t− 1 modular operations and only requires an extra m − 1 XOR gates of t-input. Simulation results show the separatedapproach can achieve ap-proximately both a 30% reduction of power consumption and a 15% reduction of circuit complexity as comparedwith the original approach for calculating ∆(i) _or Ωi within (t, m) = (8, 8).

4. Chien Search and the Error Value Evaluator

In the (N, K) RS decoding algorithm, the Chien search is used to check whether the error locator polynomial σ(x) equals zero or not while x = α−n, n = 0, 1, . . . , N−1. If σ(α−n) = 0, it means there is an error at Rn. In Ref. 8, McEliece proposedthree conditions to determine whether the received codeword can be corrected or not.

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xα-i MU X

σ

i (a)

σσσσ

ood

(x)

C1 C3 C7 C5

σ

1

σ

3

σ

7

σ

5

σ

0 C2 C4 C8 C6

σ

2

σ

4

σ

8

σ

6 8 (b)

Fig. 5. (a) Chien search cell Ci. (b) Chien search structure for t = 8.

The corresponding hardware is to compare the degree of σ(x) with the number of roots foundby the Chien search. While the out-of-correction receivedcodeword is detected, we stop the follow-up decoding procedure of error value evaluation. Figure 5(a) shows the circuit of the Chien search cell Ci andthe structure of the Chien search with t cells is illustratedin Fig. 5(b).

At the ηth cycle after initialization, the finite-field adder (FFA) in the right handside of Fig. 5(b) calculates the value of σ(α−η) andthe NOR gate is used to check whether the final sum equals zero or not. Note that σodd(x) = σ1x + σ3x3+· · · + σtoddx

todd _{is preparedto calculate the error value. For t = 8, t}

odd= 7

represents the largest odd number less than or equal to t. However, Fig. 5 checks one root at one cycle, whereas Fig. 6 illustrates another structure of the Chien search to check eight roots at each cycle for applications of higher data rate. Note that all input ports to the shadowed cells in Fig. 6 are identical. In the jth iteration after initialization, the outputs of the FFA in shadowed cells are σ(α−8j), σ(α−8j−1)_{, . . . , σ}(α−8j−7)_{, respectively.}

For calculating the error value, the Forney algorithm proposedin Ref. 9 is utilizedandcan be expressedas: el= Ω(χl−1) σ(χ−1l ) = Ω(χ −1 l )· χ−1l σodd(χ−1l ) , (7)

where χ−1_l indicates the root of σ(x), for l = 1, . . . , t. Figure 7 shows an area-efficient architecture for the error value evaluator, which requires only one variable–variable FFM. Note that the Buffer-1 and Buffer-2 store all the roots χ−1_l foundby the Chien search andthe corresponding values of σodd(χ−1l ) respectively. The Ω(x)-buffer is composedof one “0 ” andthe coefficients of the error evaluator polynomial Ω(x), Ω0 through Ων₋₁, where ν represents the number of the actual errors. At the first ν cycles after initialization, the output of the multiplexer in Fig. 7 is χ−1l ,

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xα-64 xα-16 xα-8 .... MU X σ₈ MU X σ₂ σ0= 8'b 01 MU X σ₁

σ( α

-8j

₎

xα-7

σ( α

-8j-7

₎

.... . . . . xα-1

σ( α

-8j-1

₎

.... . . . . xα-2 xα-8 xα-14 xα-56

Fig. 6. Chien search structure to check eight roots per cycle for t = 8.

error value Buffer-1 Buffer-2 σσσσodd(χχχχl -1₎ χχχχl-1 M U X Ω(x)-buffer GF(2m₎ invertor 0,ΩΩΩΩ₀,ΩΩΩΩ₁, . . . ,ΩΩΩΩ_νννν-1

Fig. 7. The error value evaluator structure.

andthe detailedcomputation of (Ω(x)· x)|x=χ−1_l can be shown as

(Ω0+· · · + (Ων−2+ Ων−1χ−1l )χ−1l · · ·)χ−1l = Ω0χ−1l + Ω1(χ−1l ) 2 +· · · + Ων−1(χ−1l ) ν ≡ Ω(χ−1 l )· χ−1l .

At the (ν + 1)th cycle, the output of the Ω(x)-buﬀer is 0 andthe output of the multiplexer in Fig. 7 shouldbe alteredto 1/[σodd(χ−1l )], then the output of the FFM, which will be latchedby the register shown in the right handside of Fig. 7, is the error value corresponding to the root χ−1l .

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Syndrome Calculator

64 0

S1~S8

S9~S16

128 192

σσσσ

(x)

Ω

(x) 160 Key Equation Solver Chien Search Error Value Evaluator

Fig. 8. Pipelining diagram of our proposed (255, 239) RS decoder with t = 8.

5. Chip Implementation and Simulation Results

Here we propose two design examples to verify our low-power architecture. One is the (255, 239) RS decoder, which is recommended in ITU-T G.975 to resist burst errors for optical ﬁber submarine cable systems on the STM-16 basis. Note that the STM-16 format has a data rate of 2.5 Gbps. For meeting a higher data rate with a lower clock rate, the look-forwardarchitecture is utilizedin our (255, 239) RS decoder to process four bytes at each cycle. Figure 8 shows the pipelining diagram with the latency of 192 cycles. In the ﬁrst pipelining stage, the front half syndromes S1 through S8 are calculatedandusedto detect whether the received codeword carrying errors. The received codeword without errors indicates that the calculations of the later half syndrome, S9through S16, are needless in the second stage. However, the Chien search takes only half of the thirdstage, checking eight roots at each cycle. The error value is evaluatedandsimultaneously addedwith the corresponding received symbol for correcting errors in the fourth stage.

After being implementedby the Verilog andSynopsys design tool with the Artisan 0.25 µm CMOS 1P5M standard cells, the (255, 239) RS decoder contains four 2K bit embedded single-port synchronous memory and has gate counts of 32.9 K. The total size is 2.23 mm×2.23 mm with the RS core of 2.01 mm×1.01 mm. The layout view andchip summary are shown in Fig. 9. While simulatedat 1.8 V of the supply voltage by EPIC PowerMill, our proposed RS decoder can work successfully with the 2.5 Gbps data rate and consumes 14.8 mW core power and 53.7 mW memory power under the bit-error rate (BER) of 10−4, indicating an approximately 20% error probability of the received codewords. For the BER less than 10−5, only the syndrome calculator operates to detect errors and the other three parts — key equation solver, Chien search, anderror value evaluator — almost remain idle.

The other design example is the (208, 192) RS decoders utilized for DVD ap-plications. Since the data rate of 1× DVD is below 4 MBps, the overall decoding speedcan be maintainedby the two-stag approach of calculating syndromes, each

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Chip Summary

Power dissipation (83.68MHz, 1.8Volt)

(255,239) Reed-Solomon

Decoder

2k-bit MEM#3 2k-bit MEM#4 2k-bit MEM#1 2k-bit

MEM#2 _{Chip Size}

RS Core Size 2.23mm x 2.23mm 2.01mm x 1.01mm Gate Counts Embedded Memory 32.9 K 8K-bit SRAM Technology .25µµµµm 1P5M CMOS 48.2 mW RS core Memory 53.7 mW 70.2 mW 72.9 mW 13.5 mW 14.8 mW 22.5 mW 27.9 mW BER < 10-5 BER = 10-4 BER = 10-3 BER > 10-2

Fig. 9. Layout view of the (255, 239) RS decoder chip.

Syndrome Calculator

208 0

S1~S8

S9~S16

516 724

Key Equation Solver

Chien Search Error Value Evaluator 548 σσσσ(x) 652 Ω Ω Ω Ω(x)

Fig. 10. The pipelining diagram of our proposed (208, 192) RS decoder with t = 8.

taking 208 cycles to ﬁnish. Figure 10 illustrates the pipelining diagram with the latency of 724 cycles. From our proposal, the Chien search takes only half of the thirdstage, checking two roots at each cycle andtherefore, 104 cycles are required totally. The error value is evaluatedafter the Chien search and72 cycles are needed in the worst case of eight errors occurring.

We implement the (208, 192) RS decoder by the 0.35 µm CMOS SPQM stand ard cell library. The RS decoder has the core size of 1.05 mm× 1.07 mm andthe gate counts of 16.3 K, including 3.2 K for the syndrome calculator, 8.0 K for the key equation solver, and5.1 K for Chien search andthe error value evaluator. Figure 11 shows the layout view andchip summary.

While simulatedat the supply voltage of 3.3 V by EPIC PowerMill, our proposed RS decoder can work successfully with the clock rate of 100 MHz. Table 2 shows the circuit complexity andsimulation results of power consumption between the

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Power dissipation

54.9 mW BER < 10-5

Key Equation

Solver

Syndrome Calculator Chien Search Error Value Evaluator

Chip Summary

RS Core Size Gate Counts Technology 1.05mm x 1.07mm 16.3 K .35µµµµm 1P4M CMOS BER = 10-4 BER = 10-3 BER > 10-2 60.2 mW 109.4 mW 135.6 mW Fig. 11. Layout view of the (208, 192) RS decoder chip. Note that the power dissipation is simulated at the clock rate of 100 MHz and the supply voltage of 3.3 V.

Table 2. Comparison of hardware complexity (gates) and power consumption (mW) with the pre-vious architecture.

Previous10 _Proposed

Gates (K) 8 errors 0 error Gates (K) 8 errors 0 error

Syndrome Calculator 3.1 88.1 87.9 3.2 83.1 54.9

Key Equation Solver 2.9 120.2 115.5 8.0 81.5 0

Chien Search 2.8 56.7 53.2 2.8 46.6 0

Error Value Evaluator 1.8 37.9 7.1 2.3 19.8 0

Total 10.6 302.9 263.7 16.3 231.0 54.9

previous architecture10 andour proposal in this paper. Although the architecture proposed in Ref. 10 has less complexity, the proposed RS decoder consumes only 60% of the power dissipation of Ref. 10 and approximately no power consumption in the key equation solver, Chien search, anderror value evaluator when no-error codewords are received. Note that the two diﬀerent results in each architecture correspondto two extreme cases of the receivedcodewords carrying eight errors andwithout errors. In realistic communication systems, the probability of no error is much larger than that of error. Our proposedtwo-stage syndrome calculator of reducing half syndrome calculations, and of terminated mechanisms in other parts can lead to a very power eﬃcient solution for the RS decoder.

6. Conclusion

In this paper, the design and implementation of a low-power RS decoder is presented. The proposed architecture features the novel two-stage syndrome

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calculator, the key equation solver using the modiﬁedBM algorithm, andthe Chien search with the terminatedmechanism. The test chip of the (255, 239) RS decoder andthe (208, 192) RS decoder are implemented to verify our proposal. Since there are almost correct codewords in realistic communication systems, our derived struc-ture can lead to a very power eﬃcient solution for the RS decoder.

Acknowledgment

The work was supportedby the National Science Council of Taiwan, R.O.C., under Grant NSC 90-2218-E-009-035.

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