Kuo-Liang Yeh, Member, IEEE, and Jyh-Chyurn Guo, Senior Member, IEEE
Abstract—The impact of layout-dependent parasitic
capaci-tances on extraction of inversion carrier density Qinvand effective mobility μeff has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the ex-trinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e.,
Cof and Cf (poly-end), respectively. Both categories of parasitic capacitance lead to overestimated Qinvand underestimated μeff. The increase in effective channel width Weff due to ΔW from shallow trench isolation (STI) top-corner rounding may compen-sate μeffdegradation due to STI stress. The tradeoff between μeff and Weffdetermines the impact of width scaling on IDSand Gm. A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of μeff in multifinger MOSFETs with various layouts and narrow widths down to 0.125 μm.
Index Terms—Effective mobility, effective width, fringing
capacitance, open deembedding, parasitic capacitances. I. INTRODUCTION
T
HE LAYOUT-dependent stress effect has been known as a critical factor responsible for the variation of channel carrier mobility. Most of previous works limited the observa-tion through dc characterizaobserva-tion and assumed the variaobserva-tions of channel current IDS and transconductance Gm simply fromthat of effective mobility μeff. This assumption may become
invalid for nanoscale MOSFETs, in which the variation of effective channel width Weff emerges as a more important
variable [1]. To investigate the stress effect on μeff, an accurate
and reliable method for μeff extraction becomes a
prerequi-site, but this has been increasingly challenging in nanoscale MOSFETs. The split C–V method has been frequently used for the determination of inversion carrier density Qinv, which
is one of basic parameters for μeffextraction [2], [3]. However,
Manuscript received March 8, 2011; revised April 27, 2011 and May 17, 2011; accepted May 20, 2011. Date of publication July 25, 2011; date of current version August 24, 2011. This work was supported in part by the National Science Council under Grant NSC 98-2221-E009-166-MY3. The review of this paper was arranged by Editor Y.-H. Shih.
K.-L. Yeh is with the Institute of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with Silicon Motion Technol-ogy Corporation, Hsinchu 300, Taiwan.
J.-C. Guo is with the Institute of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: jcguo@mail.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2011.2158105
the conventional split C–V method is not valid for miniaturized devices because the measured gate capacitance cannot represent the intrinsic channel capacitance. Recently, several improved techniques have been proposed, trying to extend the split C–V method to scaled CMOS devices [4]–[7]. Unfortunately, the proposed methods leave a number of critical problems without a concrete solution. First, the conventional C–V measurement cannot be applied to nanoscale MOSFETs with ultrathin gate oxide due to gate leakage current and abnormal C–V falloff un-der the strong inversion condition. Second, an appropriate open deembedding method for removing parasitic capacitances from the pads, interconnection lines, and lossy substrate [8], [9] is not available for the published methods relying on the conventional
C–V measurement. The mentioned parasitic capacitances do
not make any contribution to IDSbut lead to an overestimation
of Qinvand then an underestimation of μeff. Moreover, the
ex-isting methods are limited to single gate-finger devices and not applicable to multifinger MOSFETs, which have been widely used in RF and analog circuits. A more critical problem is that the gate sidewall and gate finger-end fringing capacitances were not considered in the existing methods. Most of the early works are limited to long-channel devices in which the gate sidewall fringing capacitance is negligibly small compared with the intrinsic channel capacitance. Recent works, even with an improvement for short-channel devices, have been limited to single-finger and wide-channel-width MOSFETs in which the gate finger-end fringing capacitance is insignificant [6]. In our recent work, the 3-D parasitic gate capacitances have been accurately calculated by a 3-D integral model and Raphael simulation. Our research foresees an important impact that the parasitic gate capacitances are not scalable with gate length Lg
scaling and may dominate that from the intrinsic channel region in nanoscale MOSFETs [10]. However, the previous models [10]–[14] limit the focus on the gate sidewall capacitance and leave the finger-end fringing capacitance an open question. This topic deserves more research effort to explore the layout-dependent mechanisms and the methodology for precise extrac-tion of intrinsic gate capacitance density Cox(inv). The last point
of special concern is that the shallow trench isolation (STI) profile and top-corner rounding (TCR) effects on Weff were
not considered in previous works [4]–[7]. The approximation of Weff by the total width on layout, i.e., Wtot, becomes invalid
for multifinger and narrow-width MOSFETs [1].
In this paper, a new method based on high-frequency S-parameter measurement, an improved open deembedding
Fig. 1. Schematic of multifinger MOSFETs with three different layouts. (a) Standard multifinger device: WF× NF= 2 μm× 16 (W2N16).
(b) Narrow-OD devices: WF× NF= 1 μm× 32 (W1N32) and WF× NF = 0.5 μm× 16 (W05N64). (c) Multi-OD devices: WOD× NOD=
2 μm× 1 (OD1), WOD× NOD= 0.25 μm× 8 (OD8), and WOD× NOD= 0.125 μm× 16 (OD16).
process, and Raphael simulation has been developed to pre-cisely extract and eliminate all of the parasitic capacitances outside the intrinsic channel. In addition, STI TCR-induced ΔW can be determined, giving Weffwith high precision, which
is critical for multifinger devices with extremely narrow width. Accordingly, effective mobility μeff can be extracted with
im-proved accuracy, which is attributed to the ensured accuracy of basic device parameters such as Cox(inv), Qinv, Lg, and Weff.
II. DEVICEFABRICATION ANDCHARACTERIZATION
In our recent work, multifinger MOSFETs have been fabri-cated in a 90-nm logic CMOS process [1]. Target gate length Lg
is 80 nm, and total gate width Wtot= WF × NFis specified at
32 μm. Two kinds of layouts derived from the standard multi-finger MOSFET, namely, narrow-OD and multi-OD, were im-plemented for this study. Note that OD means oxide diffusion, which is equivalent to the active area, generally denoted by AA. Fig. 1(a)–(c) displays the device layouts for standard, narrow-OD, and multi-narrow-OD, respectively. The narrow-OD devices illus-trated in Fig. 1(b) were designed with simultaneously varied
NF and WF under fixed total width, i.e., Wtot= 32 μm, and
WF× NF = 2 μm× 16, 1 μm × 32, and 0.5 μm × 64, which
were denoted by W2N16, W1N32, and W05N64, respectively. The multi-OD devices shown in Fig. 1(c) represent multiple OD fingers with simultaneously varied OD finger width WOD
and OD finger number NODunder a specified finger width, i.e.,
WF = WOD× NOD. In this paper, the multi-OD devices were
implemented with NF = 16 and WOD× NOD= 2 μm× 1,
0.25 μm× 8, and 0.125 μm × 16, corresponding to WF =
2 μm, namely, OD1, OD8, and OD16, respectively.
S-parameters were measured by an Agilent E8364B network analyzer for high-frequency characterization up to 40 GHz. Two-step deembedding, i.e., open and short deembedding, was performed via dummy open and dummy short test structures. Open deembedding was carried out on the measured two-port S-parameters to remove the parasitic capacitances from the pads, interconnection lines, and lossy substrate. Moreover, short deembedding was done to eliminate the parasitic resistances and inductances originated from the metal intercon-nection [8]. Two kinds of dummy open test structures, namely, open-M3 and open-M1, were designed, as shown in Fig. 2(a) and (b), respectively. Note that the dummy open-M1 created in this paper incorporates metal-3/metal-2/metal-1 (M3–M2–M1) stacked layers, as shown in Fig. 2(b), to remove all of the
Fig. 2. Dummy open test structures. (a) Open-M3 for open deembedding to M3. (b) Open-M1 for open deembedding to M1.
parasitic capacitances from the stacked metals from top to bot-tom, i.e., M1. On the other hand, open-M3, which is known as the conventional and most frequently used open deembedding method, cannot remove the parasitic capacitances from the met-als below M3, which are not scalable with device scaling and indeed impose a significant influence on miniaturized devices in high-frequency performance. In this paper, 3-D interconnect simulator Raphael was utilized to simulate the 3-D parasitic capacitances from the metals and gate-related fringing capacitances.
III. INTRINSICGATECAPACITANCEEXTRACTION
A. Open Deembedding for Intrinsic Gate Capacitance Extraction
The S-parameters measured from the devices, the dummy open-M3, and the dummy open-M1, which were denoted by DUT, OM3, and OM1, were converted to Y-parameters, as shown in (1.1)–(1.3) for open deembedding. Following the process given by (1)–(3), open-M3 and open-M1 deembedding were simultaneously performed on the same device to investi-gate the differences in the extracted investi-gate capacitances and the final impact on μeff. Thus
[S]DUT⇒ [Y ]DUT⇒ Cgg(DUT)=
ImYDUT 11
ω (1.1)
[S]OM3⇒ [Y ]OM3⇒ Cgg(OM3)=
ImYOM3 11
ω (1.2)
[S]OM1⇒ [Y ]OM1⇒ Cgg(OM1)=
ImYOM1 11
ω (1.3)
Cgg(DUT,OM3)= Cgg(DUT)− Cgg(OM3)
(2)
Cgg(DUT,OM1)= Cgg(DUT)− Cgg(OM1)
(3)
Cgg(OM1)= Cgg(OM3)+ CM 123 (4)
where
Cg,DUT gate capacitance measured from DUT
with pads;
Cgg(OM3) parasitic capacitance measured from
open-M3;
Cgg(OM1) parasitic capacitance measured from
open-M1;
Fig. 3. Gate capacitances Cgg(DUT,OM3)and Cgg(DUT,OM1)extracted from open-M3 and open-M1 deembedding on multifinger NMOS (W2N16, W1N32,
and W05N64) with fixed WF× NF. (a) Cgg(DUT,OM3)versus NF. (b) Cgg(DUT,OM1)versus NF.
Cgg(DUT,OM3) gate capacitance after open-M3
deembedding;
Cgg(DUT,OM1) gate capacitance after open-M1
deembedding.
It was expected that the multifinger MOSFETs with fixed
Wtot= WF× NFshould have a constant intrinsic gate
capaci-tance, which is independent of the variation of NFand WF. To
verify this point, Cgg(DUT,OM3) and Cgg(DUT,OM1) extracted
by using open-M3 and open-M1 deembedding are presented versus NF, as shown in Fig. 3(a) and (b), respectively. Both
Cgg(DUT,OM3)and Cgg(DUT,OM1)indicate a linear function of
NF, and Cgg(DUT,OM1) versus NF presents a much smaller
slope than that of Cgg(DUT,OM3). The experimental results are
out of conventional expectation, and the nonzero slope, i.e., the variation w.r.t. NF, reveals parasitic capacitances outside
the intrinsic channel, which can be significantly reduced using open-M1 deembedding but cannot be eliminated to zero. The linear increase in Cgg(DUT,OM1) with NF, under fixed Wtot,
suggests the existence of some other components of parasitic capacitance, which are generated from certain sources other than the pads, interconnection lines, and substrate and cannot be removed, even using open-M1 deembedding, i.e., the most effective open deembedding method.
B. Gate Fringing Capacitance Simulation and Analysis
To explore the mechanism responsible for this new obser-vation, a rigorous analysis was performed by using Raphael simulation, and the results suggest that the parasitic capaci-tances lumped into Cgg(DUT) can be classified into two
cate-gories: one is contributed from the pads, interconnection lines, and substrate, and the other is fringing capacitances from the gate sidewall and finger ends, which are denoted by Cof and
Cf (poly-end), respectively. The former is a kind of extrinsic
parasitic capacitances and can be eliminated through a dedi-cated open deembedding method, such as open-M1. However, the latter is actually a kind of intrinsic parasitic capacitance arising from the gate fingers and the surrounding conductors, such as the source/drain (S/D) diffusion regions and the contact plugs, and cannot be removed using any existing deembedding methods. To solve this problem, 3-D capacitance simulation was performed using Raphael to calculate Cofand Cf (poly-end).
Fig. 4(a) and (b) illustrates the 3-D MOSFET structure for Raphael simulation. This 3-D structure incorporates four
Fig. 4. Schematic of the 3-D MOSFET structure for Raphael simulation. (a) The 3-D structure incorporates four conducting regions, namely, a polygate, a channel, an S/D diffusion region, and contact plugs to the S/D. (b) Cross-sectional view of the multifinger MOSFET.
conducting regions, namely, a polygate, a channel region, an S/D diffusion region, and contact plugs to the S/D region. As an individual electrode is specified for each conducting region as defined, the three components of coupling capacitances from the gate to other three regions can be calculated. Among the three components, the gate-to-channel region is the intrinsic gate capacitance responsible for Qinv, and the other two
com-ponents, i.e., gate to S/D diffusion and gate to contact, which are denoted by Cg,Diff and Cg,CT, respectively, constitute the
gate sidewall fringing capacitance, given by Cof = Cg,Diff+
Cg,CT. Fig. 5 presents Cg,Diff, Cg,CT, and Cof calculated for
MOSFETs with various Lg. Note that all of the components
of the sidewall fringing capacitance indicate very weak depen-dence on Lg(80–160 nm), and Cofis 0.28 fF/μm,
correspond-ing to 90-nm CMOS design rule and technology parameters. The results suggest that the gate sidewall fringing capacitance is not scalable with Lg scaling, and its weighting factor will
rapidly increase with device scaling.
In addition to gate sidewall fringing capacitances Cof, gate
finger-end fringing capacitance Cf (poly-end) is another key
element of the intrinsic parasitic capacitances, which always exists in MOSFETs but cannot be removed by the existing open deembedding methods. Again, Raphael simulation was employed to calculate Cf (poly-end), which emerges as a critical
component for accurate extraction of truly intrinsic gate capac-itance and STI TCR-induced ΔW . Both Cof and Cf (poly-end)
are not scalable with device scaling and may dominate the intrinsic gate capacitance of miniaturized MOSFETs. As a result, Cof and Cf (poly-end) appear as critical parameters to
Fig. 5. Gate sidewall fringing capacitances simulated by Raphael for MOSFETs with various Lg, Cg,Diff, Cg,CT, and Cof= Cg,Diff+ Cg,CT
versus Lg.
Fig. 6. (a) Schematic of the multifinger MOSFET layout. (b) Three compo-nents of fringing capacitances associated with each gate finger: Cf (poly-end)
is the finger-end fringing capacitance, and Cg,Diff and Cg,CTare the gate
sidewall fringing capacitances.
be known for precise determination of Qinvand then accurate
extraction of μeff in multifinger MOSFETs with narrow width.
Fig. 6 illustrates the planar view of a multifinger MOSFET in which three components of fringing capacitances, such as
Cf (poly-end), Cg,Diff, and Cg,CT, are depicted. This graphical
analysis explains that Cf (poly-end) is proportional to NF but
is independent of WF. On the other hand, sidewall fringing
capacitances, such as Cg,Diff and Cg,CT are determined by
both WF and NF and in a linear function proportional to
Wtot= WF× NF. Note that Cf (poly-end)can be decomposed
into the fringing capacitances from the polygate finger ends on STI to the S/D diffusion region and that to the contacts on the S/D region. For narrow-OD devices [see Fig. 1(b)] with simultaneously varied WF and NF under a specified Wtot=
WF× NF, Cf (poly-end)will increase with increasing NF, and
its weighting factor dramatically increases in MOSFETs with very large NF and extremely narrow WF. According to 90-nm
CMOS design rule and technology parameters, Cf (poly-end) is
calculated to be 0.064 fF/finger by Raphael simulation. Based on an extensive simulation and analysis on the aforementioned parasitic capacitances from pads, metals, lossy substrate, and gate-related fringing effects, the intrinsic gate
capacitance extraction flow and analysis can be derived as follows:
Cgg(DUT,OM1)= Cgg,int× NF(WF+ ΔW ) + Cgg,ext
×Wtot+ Cf (poly-end)× NF (5)
where Cgg,int and Cgg,extare the intrinsic and extrinsic
com-ponents of the gate capacitance density per unit width, respec-tively, which are defined as
Cgg,int= Cox(inv)Lg (6.1)
Cox(inv)= εoxε0/Tox(inv) (6.2)
Cgg,ext= Cof= Cg,CT+ Cg,Diff (7)
Wtot= WF × NF (8)
Tox(inv) electrical thickness of the oxide under strong
inversion;
Cox(inv) intrinsic gate capacitance density of the inversion
channel;
ΔW increase in effective width from STI TCR. According to (6)–(8), (5) can be rewritten as two parts, one of which is proportional to NF and the other is independent of
NF, i.e.,
Cgg(DUT,OM1)= NF
(ΔW · Lg)Cox(inv)+ Cf (poly-end)
+ Cox(inv)Lg+ Cof
Wtot (9)
then Cgg(DUT,OM1)of the multifinger MOSFETs with various
NF but fixed Wtot= WF× NF can be expressed as a linear
function of NFwith the slope and intercept defined as α and β,
respectively, given by
Cgg(DUT,OM1)= αNF+ β (10)
where
α = (ΔW · Lg)Cox(inv)+ Cf (poly-end) (11)
β =Cox(inv)Lg+ Cof
Wtot
= (Cgg,int+ Cof)Wtot. (12)
Note that the first term of intercept β in (12), i.e., Cgg,intWtot,
is the intrinsic gate capacitance, which contributes the inversion carriers QinvWtotthat are responsible for channel current IDS.
The intrinsic gate capacitance density Cgg,int= Cox(inv)Lg
defined by (6.1) can be extracted from intercept β given by (13) converted from (12), with Cofdetermined by Raphael
simula-tion. In another approach, Cof can be extracted from β given
by (14.1), under varying Lgand specified Cox(inv) (Tox(inv)).
The Cof determined by two independent approaches, one from
simulation and the other from measurement, should be self-consistent to validate the accuracy. In addition, Lg can be
extracted from (14.2) as a function of Cofand Cox(inv). Finally,
ΔW can be extracted from slope α given by (15) derived from (11), in which Lg and Cox(inv) have been extracted, and
Cf (poly-end) is provided by Raphael simulation. The accurate
precise calculation of inversion carrier density Qinv and
accu-rate extraction of effective mobility μeffin the intrinsic channel
region. The aforementioned flow is described as follows:
Cox(inv)Lg= β Wtot − Cof (13) Cof= β Wtot − Cox(inv) Lg (14.1) Lg= β WtotCox(inv) − Cof Cox(inv) (14.2) ΔW =α− Cf (poly-end) Cox(inv)Lg . (15)
Following the extraction flow, open-M1 deembedding, and Raphael simulation can facilitate thorough and precise extraction of the 3-D parasitic capacitances and accurate determination of the intrinsic gate capacitance. Taking the developed characterization and analysis process, the funda-mental device parameters such as Cox(inv), Lg, ΔW , Cof,
and Cf (poly-end) can be determined with proven accuracy for
nanoscale MOSFETs. Table I summarizes the key parameters extracted from narrow-OD NMOS. Note that the slope α of 0.0988 fF/finger is contributed from two portions given by (11), one from STI TCR-induced ΔW , i.e., Cox(inv)LgΔW =
0.0348 fF/finger, and the other from the finger-end fringing capacitance, i.e., Cf (poly-end)= 0.064 fF/finger. The former
resulted from ΔW = 37.9 nm occupies around 35% of α, and the latter contributes the remaining 65%. Both terms cannot be eliminated using any deembedding methods. The analysis proves the results shown in Fig. 3 and explains why it is impos-sible to achieve zero slope in Cgg(DUT,OM1)versus NF under
fixed Wtot= WF× NF, even through open-M1 deembedding.
As for multi-OD NMOS, the extracted ΔW is 42.9 nm. It is larger than that of narrow-OD NMOS due to the sharper trench profile associated with the denser OD/STI layout.
IV. EFFECTIVEMOBILITYEXTRACTION ANDANALYSIS
A. Effective Mobilityμeff Extraction Method
In the following, effective mobility μeffcan be extracted from
linear I–V characteristics according to (16)–(22), in which
inv ox(inv)
(VGS− VT − λVDS) in the linear region. Herein, Cox(inv)is the
intrinsic gate capacitance density per unit area of the inversion channel, given by Cgg,int/Lg, and Cgg,int is the intrinsic gate
capacitance density determined by (22) [or (13)], in which intercept β has been extracted from the linear function of
Cgg(DUT,OM1)versus NF under fixed Wtot= WF × NF [see
Fig. 3(b)], and Cof is the gate sidewall fringing capacitance
calculated by Raphael simulation (see Fig. 5).
IDS= WeffQinvμeff
VDS0 Leff (16) μeff = IDS VDS0 1 Weff LeffQinv (17) VDS0= VDS− IDS(RD+ RS) (18) Weff = NF(WF + ΔW ) (19) Qinv= Cox(inv)(VGS− VT − λVDS) (20) Cox(inv)= Cgg,int Lg (21) Cgg,int= β NF × WF − Cof (22) λ≤1
2 for short-channel MOSFETs in the linear region.
Note that the differences between the new and conventional methods appear in Cox(inv) and Weff, and there is nearly no
difference in (VGT− λVDS). The influence from λ variation
on Qinv and the extracted μeff is negligible in the strong
inversion region due to VGT λVDS. However, the influence
may become significant in the weak inversion region when VGT
approaches λVDS.
B. Effective MobilityμeffExtraction and Analysis for
Narrow-OD NMOS
Fig. 7 presents the linear IDS and Gm measured from
narrow-OD NMOS under varying VGT (VGT= VGS− VT).
The results indicate that the narrower width (WF = WODfor
narrow-OD devices) leads to IDS and Gm degradation. As
shown in Fig. 8(a), VT versus WOD for narrow-OD NMOS
presents an obvious inverse narrow-width effect (INWE), which is generally originated from the STI process [16]. Fig. 8(b) reveals a monotonic decrease in maximum Gm (Gm,max)
with WOD scaling. As compared with the standard reference
(W2N16), Gm,max degradation is around 2% for W1N32, and
it is significantly increased to as large as 8% for W05N64, with four times narrower width than W2N16. The monotonic
Fig. 7. (a) Drain current IDSversus VGT. (b) Transconductance Gmversus VGTin the linear region (VDS= 50 mV), as measured from narrow-OD NMOS
(W1N32 and W05N64) and standard multifinger NMOS (W2N16). All of the devices have the same total width, i.e., WF× NF = 32 μm.
Fig. 8. (a) Linear VTversus WOD. (b) Gm,maxversus WODfor narrow-OD NMOS (W1N32 and W05N64) and standard multifinger NMOS (W2N16), under
the biases of VDS= 50 mV and VBS= 0 V.
Fig. 9. Effective mobility μeff versus VGT for narrow-OD NMOS. (a) Conventional method with approximation: Qinv= Cgg(DUT,OM3)/Lg× VGT,
ΔW = 0, and Weff = WF× NF. (b) New method with open-M1 deembedding and extraction of Cof and Cf (poly-end) for Cgg,intand ΔW for Weff: Qinv= Cgg,int/Lg× VGTand Weff = NF(WF+ ΔW ).
degradation of Gmwith WODscaling suggests that the increase
in STI transverse stress σ⊥along the direction of width, which is generally compressive, may be the dominant factor responsi-ble for μeff degradation and the resulted Gmdegradation.
To verify the layout dependence of μeff, the conventional
and new methods were applied to each specified device for a comparison. Note that the new method has been described by (16)–(22), in which Qinv is determined by (Cgg,int/Lg)×
(VGT− λVDS), and Cgg,intis calculated by (22), with intercept
β extracted from Cgg(DUT,OM1)versus NF and Cof extracted
from Raphael simulation. As for the conventional method,
Qinvis approximated by (Cgg(DUT,OM3)/Lg× (VGT− λVDS)
without consideration of Cof and Cf (poly-end, and Weff is
assumed equal to Wtot= WF× NF, without ΔW . The
dif-ference between Cgg(DUT,OM1) and Cgg(DUT,OM3) can be
referred to in Fig. 3(a) and (b), in which Cgg(DUT,OM3)appears
much larger than Cgg(DUT,OM1)and leads to an overestimation
of Qinv. As shown in Fig. 9(a) and (b), the μeff extracted by
the conventional and new methods indicates the same trend of μeff variation with decreasing WF, i.e., the narrower WF
leading to the smaller μeff. However, the degradation of μeff in
W1N32 and W05N64 compared with W2N16 is much larger for those extracted by the conventional method than those determined by the new method. The results suggest that the
μeff extracted by the conventional method is underestimated
due to an overestimation of Qinv from invalid approximation
of Cox(inv) by Cgg(DUT,OM3)/Lg. This deviation increases
with width scaling and becomes significant for WF = WOD=
1 μm and below. Using the new method, μeff degradation is
as small as 1.3%–2.3% for W1N32 and increases to 5.5%–8% for W05N64 compared with W2N16. However, the conven-tional method leads to an overestimation of μeff degradation to
14.6%–15.9% for W1N64 and even much worse to 42.5%–45% for W05N64.
Fig. 10. (a) Drain current IDSversus VGT. (b) Transconductance Gmversus VGTin the linear region (VDS= 50 mV), as measured from multi-OD NMOS
OD8 (NOD= 8, WOD= 0.25 μm) and OD16 (NOD= 16, WOD= 0.125 μm) and standard reference OD1 (NOD= 1, WOD= 2 μm). OD1 = W2N16.
All of the devices have the same finger number, i.e., NF = 16.
Fig. 11. (a) Linear VTversus WOD. (b) Gm,maxversus WODfor multi-OD NMOS OD8 and OD16 and standard multifinger NMOS OD1(W2N16), under
the biases of VDS= 50 mV and VBS= 0 V.
Fig. 12. Effective mobility μeffversus VGTfor multi-OD NMOS. (a) Conventional method with approximation: Qinv= Cgg(DUT,OM3)/Lg× VGT, ΔW =
0, and Weff = NF× NODWOD. (b) New method with open-M1 deembedding and extraction of Cof and Cf (poly-end) for Cgg,int and ΔW for Weff: Qinv= Cgg,int/Lg× VGTand Weff= NF× NOD(WOD+ ΔW ).
C. Effective Mobilityμeff Extraction and Analysis for
Multi-OD NMOS
Fig. 10 presents IDS and Gm versus VGT (VDS=
0.05 V) measured from multi-OD NMOS, such as OD8 (NOD = 8, WOD= 0.25 μm) and OD16 (NOD= 16, WOD=
0.125 μm), and the standard reference, such as OD1 (NOD=
1, WOD= 2 μm). The results indicate degradation of both IDS
and Gm in OD8 compared with OD1, but further scaling of
WODto 0.125 μm in OD16 leads to an increase in IDSand Gm
compared with OD8, and the degradation compared with OD1 is reduced. As for VT versus WOD of the multi-OD NMOS
shown in Fig. 11(a), it presents an obvious INWE, which is similar to narrow-OD NMOS [see Fig. 8(a)] and will actually appear in a universal curve when plotted together with those of narrow-OD NMOS [1]. However, Gm,max versus WODshown
in Fig. 11(b) reveals a nonmonotonic variation of Gm,maxwith
WOD scaling. Gm,max degradation is around 21.7% for OD8
compared with OD1, but further scaling of WOD to 0.125 μm
for OD16 results in Gm,maxincrease of around 9.7% compared
with OD8. This layout dependence of IDSand Gmappears
un-usual and cannot be explained by STI compressive stress alone. To explore the mechanism responsible for the unusual results measured from multi-OD NMOS with extremely narrow WOD,
μeff was extracted from multi-OD NMOS to verify the layout
dependence and identify the impact on IDSand Gmfrom μeff
or other parameters. As shown in Fig. 12(a) and (b), the μeff
extracted by the conventional and new methods for multi-OD NMOS (OD8 and OD16) and the standard reference (OD1 = W2N16) indicate the same trend of μeff variation with
decreas-ing WOD, i.e., the smaller μeff associated with the narrower
WOD. However, the degradation of μeff in OD8 and OD16
compared with OD1 is larger for those extracted by the conven-tional method than those determined by the new method. Again, the results suggest that the μeff extracted by the conventional
Fig. 13. Effective mobility μeffversus VGTfor multi-OD NMOS Qinv= Cgg,int/Lg× VGTin the new method. (a) μeff(ΔW = 0): ΔW is removed, and Weff= NF× NODWOD. (b) Δμeff = μeff(ΔW = 0)− μeff(ΔW ), μeff(ΔW ): Weff= NF× NOD(WOD+ ΔW ).
Fig. 14. Effective mobility μeff extracted by the new method. (a) μeff versus VGT. (b) μeff versus WODfor narrow-OD NMOS (W2N16, W1N32, and
W05N64) and multi-OD NMOS (OD1, OD8, and OD16).
originated from invalid use of Cox(inv) by Cgg(DUT,OM3)/Lg.
This deviation increases with width scaling and becomes signif-icant for WOD= 0.25 μm and below. Using the new method,
μeff degradation is around 28%–33.6% for OD8 and increased
to 36.5%–39.6% for OD16 compared with OD1. However, the conventional method leads to an overestimation of μeff
degradation to 43.6%–44.3% for OD8 and 52.5%–56.2% for OD16. Note that the μeff extracted by the new method indicates
a monotonic decrease with WOD scaling, which suggests that
μeff is not the factor causing the nonmonotonic variations of
IDSand Gmunder decreasing WOD(see Fig. 10). The increase
in Weff from ΔW is considered as the primary parameter
responsible for the increase in IDS and Gm for OD16 with
extremely narrow WODto 0.125 μm.
Under the condition that ΔW is removed from Weff given
by (19), the μeff extracted from multi-OD NMOS shown in
Fig. 13(a) just reproduces a nonmonotonic variation w.r.t. WOD
scaling, which is the same trend as that of IDSand Gm. The
impact of ΔW on the extracted μeff can be verified by the
difference between those with and without taking ΔW into
Weff, i.e., Δμeff = μeff(ΔW = 0)− μeff(ΔW ), as shown in
Fig. 13(b). The positive Δμeff suggests that μeff(ΔW = 0) is
overestimated by neglecting ΔW . Note that Δμeff is less than
4 cm2/V· s for OD1 (W
OD= 2 μm), then increases to around
22 cm2/V· s for OD8 with W
OD= 0.25 μm, and further
increases to more than 40 cm2/V· s for OD16 with W OD=
0.125 μm. The above analysis explains how the increase in Weff
from ΔW can dominate the impact of μeffdegradation and lead
to the increase in IDSand Gmin multifinger MOSFETs with
extremely narrow width.
D. Layout Dependence ofμeffin Multifinger MOSFETs
The effective mobility μeff extracted by the new method
for both narrow- and multi-OD devices are presented to-gether in Fig. 14(a) to verify the layout dependence of μeff
in multifinger MOSFETs. The comparison indicates that μeff
degradation compared with the standard reference (W2N16) is not serious for narrow-OD NMOS (W1N32 and W05N64), with channel-width scaling limited to WF = WOD= 0.5 μm,
but becomes significantly worse for multi-OD NMOS, such as OD8 and OD16, with more aggressively scaled width to
WOD= 0.25−0.125 μm. The results suggest that μeff is a
universal function of channel width WOD, no matter whether
in the same or different layouts such as narrow- or multi-OD. Fig. 14(b) presents μeff versus WOD(VGT= 0.38 V) based
on the data from narrow- and multi-OD NMOS and indicate a monotonic degradation of μeff with decreasing WOD. The
degradation is not significant in the region of WOD 0.5 μm,
but a sharp degradation happens in the transition region from
WOD= 0.5 μm to 0.25 μm. The significant degradation of
μeff when scaling WOD from 0.5 to 0.25 μm suggests that the
penetration of STI stress from the STI edge into the channel center gradually covers the whole active channel region. With regard to the gradual level off of μeff degradation in the region
below 0.25 μm, it indicates that STI stress has covered the whole active channel for WOD≤ 0.25 μm, and the influence
from further WOD scaling becomes very minor. The results
provide a helpful guideline for multifinger MOSFET layout optimization with a tradeoff among μeff, Rg, and parasitic
lines, and lossy substrate. However, a 3-D interconnect simu-lation is required to extract the intrinsic parasitic capacitances such as gate sidewall and finger-end fringing capacitances, i.e., Cof and Cf (poly-end), respectively. The Cgg(DUT,OM1)
achieved by open-M1 deembedding indicate a linear function of NF in which intercept β is contributed from two terms:
one is intrinsic gate capacitance Cgg,intWtot, and the other
is CofWtot. The former is responsible for the inversion
car-riers and channel current IDS and can be extracted from β
with known CofWtot. The slope α of the linear function can
be decomposed into two terms: one is the gate capacitance contributed from ΔW , which is given by Cox(inv)ΔWLg, and
the other is Cf (poly-end). Again, the former is an additional
component of the intrinsic gate capacitance with contribution to the inversion carriers and may compensate the μeff degradation
effect on IDS and Gm, resulting to a nonmonotonic variation
of IDS and Gm with WOD scaling, in extremely narrow
de-vices. The μeff extracted by this new method for narrow- and
multi-OD devices indicates a universal function of WOD and
a monotonic degradation of μeff with decreasing WOD. The
degradation is not significant in the region of WOD 0.5 μm,
but a sharp degradation appears in the transition region from
WOD= 0.5 μm to 0.25 μm. The results provide a useful
guideline for multifinger MOSFET layout optimization with a tradeoff among μeff, Gm, Rg, and parasitic capacitances, which
is important for RF and analog circuit design. ACKNOWLEDGMENT
The authors would like to thank the National Nano Device Laboratories for RF measurement and the Chip Implementation Center for device fabrication.
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Kuo-Liang Yeh (M’09) received the B.S.E.E.
de-gree from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1995 and the M.S.E.E. degree from National Taiwan University, Taipei, Taiwan, in 1997. He is currently working toward the Ph.D. degree in electronics engineering at NCTU.
In 1999, he joined Taiwan Semiconductor Man-ufactory Company, Inc., Hsinchu, where he worked on process integration and yield improvement. From 2004 to 2007, he was a Senior Engineer with MediaTek Inc., Hsinchu. He is currently a Senior Manager with Silicon Motion Technology Corporation, Hsinchu. He has authored more than ten technical publications in international journals and conference proceedings. His research interests include the characterization and parameter extraction of CMOS devices for modeling and circuit simulation, as well as the protection of intellectual property rights.
Jyh-Chyurn Guo (M’06–SM’07) received the
B.S.E.E. and M.S.E.E. degrees from National Tsing Hua University, Hsinchu, Taiwan, in 1982 and 1984, respectively, and the Ph.D. degree in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, in 1994.
For more than 19 years, she was with the semicon-ductor industry, where her major focus was on device design and VLSI technology development. In 1984, she joined ERSO/ITRI, where she was engaged in semiconductor integrated circuit technologies with a broad scope that covers high voltage, high power, submicrometer project, high-speed SRAM technologies, etc. From 1994 to 1998, she was with Macronix International Corporation, Hsinchu, where she engaged in high-density and low-power Flash memory technology development. In 1998, she joined Vanguard International Semiconductor Corporation, where she assumed re-sponsibility of Device Department Manager for advanced DRAM device tech-nology development. In 2000, she joined Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, where she served as a Program Manager in charge of 100-nm logic CMOS FEOL, high-performance analog (HPA), and RF CMOS technology development. In 2003, she joined as an Associate Professor with the Department of Electronics Engineering, NCTU, where she has been a Full Professor since 2008. She has authored or coauthored more than 60 technical papers. She is the holder of 19 U.S. patents in her professional field. Her current research interests cover RF/MS CMOS device design and modeling for low power and low noise, nanoscale CMOS noise modeling and strain engineering effects, broadband and scalable inductors modeling, novel nonvolatile memory technologies, and device integration technologies for SoC.
