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Impact of Uniaxial Strain on Low-Frequency Noise in Nanoscale PMOSFETs

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672 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 6, JUNE 2009

Impact of Uniaxial Strain on Low-Frequency

Noise in Nanoscale PMOSFETs

Jack J.-Y. Kuo, Student Member, IEEE, William P.-N. Chen, and Pin Su, Member, IEEE

Abstract—This letter investigates the low-frequency noise

char-acteristics and reports a new mechanism for uniaxial strained PMOSFETs. Through a comparison of the input-referred noise and the trap density of the gate dielectric/semiconductor inter-face between co-processed strained and unstrained devices, it is found that the tunneling attenuation length for channel carriers penetrating into the gate dielectric is reduced by uniaxial strain. The reduced tunneling attenuation length may result in smaller input-referred noise, which represents an intrinsic advantage of low-frequency noise performance stemming from process-induced strain.

Index Terms—Interface state, low-frequency noise,

process-induced strain, trap density, tunneling attenuation length, uniaxial strained PMOSFET.

I. INTRODUCTION

L

OW-FREQUENCY noise is becoming a concern for con-tinuously down-scaled CMOS devices because increased low-frequency noise in these nanoscale transistors may limit the functionality of analog, mixed-signal, and RF circuits. As strained silicon is widely used in state-of-the-art CMOS technologies to enable the mobility scaling [1], [2], the low-frequency noise performance for strained devices is particularly important. Several studies regarding this topic have been carried out in the past [4], [5]. For example, Giusi et al. [3] have reported that the low-frequency noise of strained PMOSFETs with HfO2 gate dielectric could be degraded due to worse gate dielectric quality when processing the SiGe source/drain. The work of Simoen et al. [4] and Ueno et al. [5] revealed that the low-frequency noise performance of strained devices with SiON gate dielectric may be preserved. While the low-frequency noise performance is determined by the device fabri-cation processes [3]–[6], whether there exists any other intrinsic stress effect on low-frequency noise is still not clear and merits further investigation. In this letter, through an in-depth com-parison between co-processed strained and unstrained devices regarding the low-frequency noise characteristics, we report a new mechanism for uniaxial strained PMOSFETs.

Manuscript received March 11, 2009. First published May 12, 2009; current version published May 27, 2009. This work was supported in part by the National Science Council of Taiwan under Contract NSC97-2221-E-009-162 and in part by the Ministry of Education in Taiwan under the ATU Program. The review of this letter was arranged by Editor S. Kawamura.

The authors are with the Department of Electronics Engineering, Na-tional Chiao Tung University, Hsinchu 30050, Taiwan (e-mail: jack.ee93g@ nctu.edu.tw; williamchen.ee93g@nctu.edu.tw; pinsu@faculty.nctu.edu.tw).

Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2009.2020069

Fig. 1. Drain current noise spectral density SIdfor devices with Lgate=

65 nm at|Vd| = 0.05 V and |Vgst| = 0.2 V showing typical 1/frnoise type

with r close to one.

II. DEVICES

Co-processed uniaxial strained and unstrained PMOSFETs are investigated in this letter [7], [8]. Strained and unstrained devices with channel direction110 and poly/SiO2gate stack were fabricated on (100) silicon substrate. The strained de-vice features compressive uniaxial Contact Etch Stop Layer (CESL) and SiGe source/drain. For the transistors with gate length Lgate= 65 nm, the saturation drain current (Idsat) of the strained device is improved by more than 100% as com-pared with its control counterpart. The low-frequency noise measurements were carried out using the BTA9812 [3], [9] measurement system.

III. RESULTS ANDDISCUSSION

The drain current noise spectral densities (SId) for strained and unstrained devices biased at gate overdrive|Vgst| = 0.2 V are shown in Fig. 1. The spectra show typical 1/frnoise type with the frequency index γ close to one. Fig. 2 shows the normalized noise spectral density, SId/I2

d, as well as (gm/Id)2 versus drain current Id for strained and unstrained devices at frequency f = 10 Hz. It can be seen that the SId/I2

d shows a fairly good proportionality with (gm/Id)2, indicating a carrier-number-fluctuation origin [10], [11].

Fig. 3 shows the input-referred voltage spectral density (SVg= SId/gm2) as a function of Vgsttaken from the average of ten devices. It can be seen that the SVg for strained and 0741-3106/$25.00 © 2009 IEEE

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KUO et al.: IMPACT OF UNIAXIAL STRAIN ON LOW-FREQUENCY NOISE 673

Fig. 2. Normalized current noise spectral density SId/I2

d and (gm/Id)2

versus Idfor devices with Lgate= 65 nm and|Vd| = 0.05 V.

Fig. 3. Input-referred noise spectral density SVgversus|Vgst| for devices

with Lgate= 65 nm at f = 10 Hz and|Vd| = 0.05 V.

unstrained devices are nearly the same. The SVg stems from oxide traps and can be expressed as [12]

SVg=

kT q2

f W LgateCOX2

λ× Nt (1)

where λ, Nt, kT , W , and COX are the tunneling attenuation length for channel carriers penetrating into the gate dielectric, the occupied trap density, the thermal energy, the gate width, and the gate capacitance per unit area, respectively. The nearly identical SVg implies that the λ× Ntproducts of the strained and unstrained devices are almost the same.

To further analyze the impact of uniaxial strain, we have measured the Ntby the incremental frequency charge pump-ing method [13] under the followpump-ing conditions: source/drain reverse voltage Vrev=−0.1 V, amplitude of gate pulse Va = 1.2 V, frequencies of gate pulse are 20 and 25 MHz, duty cycle = 50%, rise time of gate pulse trise= 2 ns, and fall time of gate pulse tfall= 2 ns. According to the incremen-tal frequency charge pumping method [13], the difference of

Fig. 4. Measurement results of charge pumping for strained and unstrained devices with Lgate= 65 nm. Ntis proportional to the maximum of ICP.

Fig. 5. Igversus|Vg| showing smaller gate tunneling current for the strained

device.

charge pumping current (ICP) between 20 and 25 MHz can be regarded as the ICP at 5 MHz. The ICP at 5 MHz versus base level of gate pulses (VBase) is shown in Fig. 4. Since the

Ntis proportional to the maximum of ICP, it can be seen that the occupied trap density Ntof the strained device is 9% larger than its control counterpart. More importantly, the increased Nt means that the tunneling attenuation length (λ) of the strained device is reduced.

The reduced λ in the strained device can be attributed to the increased out-of-plane effective mass (m∗z) and tunneling barrier height (ϕB). Thompson et al. [14] have reported that when the uniaxially compressive strain is applied, the valence bands split, and more holes populate in the top band. Moreover, the m∗z and ϕB of the top band are larger for the strained device as compared with that of the unstrained ones. The strain-increased m∗z and ϕB are also responsible for the smaller gate tunneling current (Ig) in the strained device, as shown in Fig. 5, which is consistent with the results in [15]–[17].

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674 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 6, JUNE 2009

Since λ is related to m∗zand ϕBby [12]

λ =2/2m

zϕB (2)

with being the reduced Planck’s constant, the strain-increased

m∗zand ϕBresult in a smaller λ in the strained device. In other words, while the gate dielectric quality may be degraded by the strain process, the tunneling attenuation length of carriers can actually be reduced by strain. It indicates that the carrier-number-fluctuation origin of low-frequency noise can be im-proved intrinsically for nanoscale strained PFETs.

IV. CONCLUSION

We have investigated the low-frequency noise characteristics of uniaxial strained PMOSFETs. Based on the extracted Nt, it is found that the tunneling attenuation length λ is reduced in the strained device. The reduced λ can be attributed to the increased out-of-plane effective mass m∗zand tunneling barrier height ϕB by uniaxially compressive strain. This reduced λ may result in smaller SVg, which represents an intrinsic advantage of low-frequency noise performance stemming from process-induced strain.

REFERENCES

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[3] G. Giusi, E. Simoen, G. Eneman, P. Verheyen, F. Crupi, K. De Meyer, C. Claeys, and C. Ciofi, “Low-frequency (1/f ) noise behavior of locally stressed HfO2/TiN gate-stack pMOSFETs,” IEEE Electron Device Lett.,

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[4] E. Simoen, P. Verheyen, A. Shickova, R. Loo, and C. Claeys, “On the low-frequency noise of pMOSFETs with embedded SiGe source/drain and fully silicided metal gate,” IEEE Electron Device Lett., vol. 28, no. 11, pp. 987–989, Nov. 2007.

[5] T. Ueno, H. Rhee, H. Lee, M. Kim, H. Cho, H. Baik, Y. Jung, H. Park, C. Lee, G.-J. Bae, and N.-I. Lee, “Improved 1/f noise characteristics in locally strained Si CMOS using hydrogen-controlled stress liners and embedded SiGe,” in VLSI Symp. Tech. Dig., 2006, pp. 104–105. [6] Y. P. Wang, S. L. Wu, and S. J. Chang, “Low-frequency noise

characteris-tics in strained Si nMOSFETs,” IEEE Electron Device Lett., vol. 28, no. 1, pp. 36–38, Jan. 2007.

[7] J. J.-Y. Kuo, W. Chen, and P. Su, “A comprehensive investigation of analog performance for uniaxial strained PMOSFETs,” IEEE Trans. Electron

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[8] P. Su and J. J.-Y. Kuo, “On the enhanced impact ionization in uniaxial strained PMOSFETs,” IEEE Electron Device Lett., vol. 28, no. 7, pp. 649– 651, Jul. 2007.

[9] F. Crupi, P. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, and C. Claeys, “Impact of interfacial layer on low-frequency noise (1/f ) behavior of MOSFET with advanced gate stacks,” IEEE Electron Device

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[10] L. K. J. Vandamme and F. N. Hooge, “What do we certainly know about 1/f noise MOSTs,” IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3070–3085, Nov. 2008.

[11] G. Ghibaudo and T. Bouchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectron. Reliab., vol. 42, no. 4/5, pp. 573–582, Apr./May 2002.

[12] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flicker noise in metal–oxide–semiconductor field-effect transistors,” IEEE

Trans. Electron Devices, vol. 37, no. 3, pp. 654–664, Mar. 1990.

[13] S. S. Chung, S.-J. Chen, C.-K. Yang, S.-M. Cheng, S.-H. Lin, Y.-C. Sheng, H.-S. Lin, K.-T. Hung, D.-Y. Wu, T.-R. Yew, S.-C. Chien, F.-T. Liou, and F. Wen, “A novel and direct determination of the interface traps in sub-100-nm CMOS devices with direct tunneling regime (12∼ 16 Å) gate oxide,” in VLSI Symp. Tech. Dig., 2002, pp. 74–75.

[14] S. E. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig., 2004, pp. 221–227. [15] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson,

“Strain-induced changes in the gate tunneling currents in p-channel metal–oxide–semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 88, no. 5, p. 052 108, Jan. 2006.

[16] W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, “Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 410–412, Jun. 2005.

[17] X. Yang, T. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs,” in Proc. IEEE EDSR, 2007, pp. 149–152.

數據

Fig. 1. Drain current noise spectral density S Id for devices with L gate =
Fig. 3. Input-referred noise spectral density S Vg versus |Vgst| for devices

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