極寬捕獲範圍的一位元取樣數位鎖相迴路

極寬捕獲範圍的一位元取樣數位鎖相迴路

研究生：李信德

指導教授：高銘盛 教授

國立交通大學

電信工程學系碩士班

摘 要

One Bit Quantized Digital Phase-Locked Loop with Ultra-Wide

Capture Range

Student: Hsin-Te Lee

Advisor: Prof. Ming-Seng Kao

Department of Communication Engineering

National Chiao Tung University

Abstract

In this thesis, we propose the idea of one bit quantized digital phase-locked loop (PLL) with ultra-wide capture range. To achieve the goal, we devise two steps: 1. Information collection: we estimate the phase difference many times and average the results to obtain an accurate phase estimation. Combining the accurate estimation and the feature of digital PLL, we transfer the output frequency of numerically-controlled oscillator (NCO) to around the input signal frequency. 2. Fine frequency adjustment: based on the concept of phase locking, we slightly adjust the NCO output frequency until the system is locked.

In addition, we separate the capture range into lower frequency, middle frequency and higher frequency ranges. Depending on the frequency range, we change some key factors in order to achieve phase locking over a wide frequency range. As a result, we can realize a digital PLL with ultra-wide capture range. From the simulation results, we can lock input frequency whose range is from 50 Hz to 10K Hz in noiseless environment, with an initial NCO natural frequency of 10K Hz. The system achieves almost 99.5% capture range of the natural frequency.

Acknowledgements

I would like to show my deepest appreciation to my advisor, Dr. Ming-Seng Kao, for his

enthusiastic guidance and patience. It is absolutely lucky to be his student and his positive

attitude affects me a lot. Besides, I would like to thanks all the members in our laboratory for

their support, especially Wan-Hsin Hsieh. He gives me a lot of directions of the work during

the two years. Last but not the least; I have to thanks my family, my grandparents, parents and

sisters. All of their love and support are the strongest energy for me. Without their

Content

List of figure

v

Chapter 1.

Introduction

... 1

Chapter 2.

One Bit Quantized Digital PLL System Overview

... 4

2.1. Operating principles of PLL ... 4

2.2. One bit quantized digital PLL ... 7

2.2.1. The PD of one bit quantized digital PLL ... 9

2.2.2. Digital loop filter ... 12

2.3. Summary ... 14

Chapter 3.

One Bit Quantized Digital PLL in Noiseless Environment

... 15

3.1. Frequency detection ... 15

3.2. Analysis of one bit digital quantized PLL with ultra-wide capture range ... 22

3.3. The tracking procedure ... 25

3.4. Simulation Results ... 34

3.5. Summary ... 43

Chapter 4.

Noise effect

... 44

4.1. Overview ... 44

4.2. Noise effect ... 48

4.3. Summary ... 53

Chapter 5.

Conclusions

... 55

List of figure

Fig. 2.1 PLL block diagram. ... 5

Fig. 2.2 Transfer function of the PD. ... 6

Fig. 2.3 Transfer function of the VCO. ... 7

Fig. 2.4 The block diagram of one bit quantized digital PLL. ... 8

Fig. 2.5 One bit quantized DPD. ... 9

Fig. 2.6 The phase discriminator of one bit quantized software-defined receiver ... 11

Fig. 2.7 Configuration of Ω_o( )m = Ω_i( )m + Ω_o(m− . ... 12 1) Fig. 2.8 Configuration of Ωi( )m =φ( )m −φ(m− . ... 13 1) Fig. 2.9 One bit quantized digital PLL. ... 13

Fig. 3.1 One bit quantized digital PLL in details. ... 16

Fig. 3.2 Graphical illustration of CaseⅠ. ... 18

Fig. 3.3 Graphical illustration of CaseⅡ. ... 18

Fig. 3.4 Graphical conception of CaseⅢ. ... 19

Fig. 3.5 The phase variation with time, where the angle of is the phase of input signal, the angle of is the phase of NCO output signal. ... 20

Fig. 3.6 The phase variation with time, where the angle of is the phase of input signal , the angle of is the phase of NCO output signal. ... 20

Fig. 3.7 The phase variation with time, where the angle of is the phase of input signal, the angle of is the phase of NCO output signal. ... 21

Fig. 3.8 The expected capture range of the thesis. ... 22

Fig. 3.9 General range of middle input frequency. ... 25

Fig. 3.10 The block diagram when m=1~200. ... 26

Fig. 3.13 General range of middle input frequency. ... 28

Fig. 3.14 Expected outcome of one bit digital quantized PLL with lower input frequency. ... 29

Fig. 3.15 General range of higher input frequency. ... 29

Fig. 3.16 Phase diagram of φ( )m −φ(m−1). ... 30

Fig. 3.17 The block diagram when m=201~300. ... 32

Fig. 3.18 Expected outcome of one bit quantized digital PLL with higher input frequency. ... 33

Fig. 3.19 Flowchart of distinguishing input frequency ... 34

Fig. 3.20 The locking process of f 7800 Hz._c ... 35

Fig. 3.21 The locking process of f 5000 Hz._c ... 36

Fig. 3.22 The locking process of f 3300 Hz._c ... 36

Fig. 3.23 The locking process of f 770 Hz._c ... 37

Fig. 3.24 The locking process of f 250 Hz._c ... 38

Fig. 3.25 The locking process of f 180 Hz._c ... 38

Fig. 3.26 The locking process of f 100 Hz._c ... 39

Fig. 3.27 The locking process of f 50 Hz._c ... 39

Fig. 3.28 The locking process of f 9999 Hz._c ... 40

Fig. 3.29 The locking process of f 9000 Hz._c ... 41

Fig. 3.30 The locking process of f 8500 Hz._c ... 41

Fig. 3.31 The locking process of f 8200 Hz._c ... 42

Fig. 3.32 Locked situation in noiseless environment. ... 43

Fig. 4.1 Simulation results with SNR=20 dB. ... 45

Fig. 4.2 Simulation results with SNR=10 dB. ... 46

Fig. 4.3 Simulation results with SNR=0 dB. ... 46

Fig. 4.5 Simulation results with SNR=-20 dB. ... 47

Fig. 4.6 The unlocked process of f = 50 Hz with SNR=10 dB._c ... 48

Fig. 4.7 The unlocked process of f = 8072 Hz with SNR=10 dB._c ... 49

Fig. 4.8 The unlocked process of f = 2000 Hz with SNR=0 dB._c ... 50

Fig. 4.9 The unlocked process of f = 7500 Hz with SNR=0 dB._c ... 51

Fig. 4.11 The unlocked process of f = 8222 Hz with SNR=0 dB._c ... 52

Chapter 1.

Introduction

A. PLL overview

PLL is a technique that has a great contribution to the technology advancement

in communications and motor servo control systems in the past 40 years. The

introduction of PLL is beneficial to coherent communication systems, too. In the late

1970’s, PLL did not be widely used because of the difficulty in circuit realization.

With the rapid development of integrated circuits (ICs), the applications of PLL were

widespread in modern communication systems. Since then, the PLL has made much

progress and turned its use in high-precision apparatus into consumer electronics. It

makes modern electronic systems be able to improve performance and reliability,

especially in common electronic applications used daily [1].

A PLL contains three basic functional blocks: 1. Phase detector (PD), 2. Loop

filter (LF), 3. Voltage-controlled oscillator (VCO). The first PLL ICs appeared around

1965 and were purely analog devices. In the analog PLL, an analog multiplier was

used as the PD, the LF was built from a passive or active RC filter, and the VCO was

used to generate the output signal of the PLL. This type of PLL is referred to as the

“linear PLL” (LPLL) today. In the following years, the PLL shifted slowly but

steadily into digital domain. The very first digital PLL (DPLL), which appeared

digital circuit, but the remaining blocks were still analog. A few years later, the

“all-digital” PLL (ADPLL) was invented. The ADPLL was exclusively built from

digital function blocks and hence didn’t contain any passive components like resistors

and capacitors.

In this thesis, we focus on the capture range of PLL. Definition of capture range

is given below.

Capture range: Consider a PLL that is not in lock, then the input signal

frequency slowly approaches the free running frequency of the VCO, the maximum

frequency range in which the PLL finally becomes in lock is called the capture range

[3].

Normally, no matter what kind of PLL it would be, the capture range is usually

narrow, even though we implement circuit by high-order PLLs [4]. For some special

design of ADPLL, they propose Locking Status Indicator (LSI) in a new structure.

When the PLL becomes out of lock, the PLL increases the loop bandwidth and

achieve fast locking. Hence, they can also achieve wider capture range [5].

B. Our work

In this thesis, we propose a new method of ADPLL which is called “one bit

quantized digital PLL”. The concept of one bit quantized digital PLL is originated

from typical arctangent phase discriminator (APD) of GPS [6]. We utilize the idea and

extend the system to achieve an ultra-wide capture range. In addition, we do not have

to change our loop bandwidth and do not have any indicator of the input frequency. In

other words, we simplify the architecture of ADPLL and reach the goal of ultra-wide

C. Thesis organization

The thesis is organized as below. In Chapter 2, we will introduce the operating

principles of PLL, from LPLL to ADPLL. Then, the concept of one bit quantized

digital PLL will be described. Next, in Chapter 3, we analyze the affect of every

parameter in one bit quantized digital PLL and devise the method to achieve

ultra-wide capture range. Then, we study the system performance under noisy

environment in Chapter 4. Finally, we summarize the important ideas of our design

Chapter 2.

One Bit Quantized Digital PLL System

Overview

As we know that the multi-bit analog-to-digital-conversion (ADC) is utilized in

most applications. For example, all digital phase-locked loop is one of the

applications. In order to reduce the complexity of the quantization design, the one-bit

ADC has been investigated. In this chapter, we would like to firstly introduce the

general concept of PLL and one-bit ADC. Then, we combine PLL with one-bit ADC

and bring the idea - one bit quantized digital phase-locked loop.

2.1. Operating principles of PLL

A PLL is a circuit that makes a particular oscillator to track another one. To be

more specific, a PLL is a circuit synchronizing an output signal (generated by an

oscillator) with an input or reference signal in frequency as well as in phase. In the

synchronized—often called locked—state, the phase error between the output signal

and the input signal remains constant or zero.

If a phase error builds up, a control mechanism acts on the oscillator in such a

way that the phase error is again reduced to a minimum. In such a control system, the

phase of the output signal is actually locked to the phase of the input signal. This is

The basic operating principle of PLL is explained by the example of the linear

PLL. Its block diagram is shown in Fig. 2.1. The PLL contains three basic functional

blocks: 1. Phase detector. 2. Loop filter. 3. Voltage-controlled oscillator.

Phase Detector

(PD)

Loop Filter

Voltage-Controlled

Oscillator (VCO)

( )

s t

( )

y t

( )

u t

( )

u t

Fig. 2.1 PLL block diagram.

The signals within the PLL circuit are defined as follows:

 The input (or reference) signal s t( ) with angular frequency ω . _c  The output signal y t( ) of the VCO with angular frequency ω . o

 The output signal ( )u t of the phase detector (_d u is the average value of _d ( )

d

u t ).

 The output signal u t_f( ) of the loop filter.

 The phase error θ , defined as the phase difference between signals _e s t( )and

( ) y t

 The natural frequency of VCO (ω ). _n

Phase detector

with the phase of s t( ) and develops an output signal u t that is approximately d( ) proportional to the phase error θ_e( )t , given as

( ) ( )

d d e

u t =K ⋅θ t , (2.1) whereK (volts/rad) is the gain of the PD. Fig. 2.2 is a graphical representation of _d Eq.(2.1).

e

θ

d

u

Fig. 2.2 Transfer function of the PD.

Loop filter

The output signal u t of the PD contains a dc component and an ac _d( ) component. The phase error is contained in the dc component, while the ac

component is undesired. Therefore, the loop filter is used to eliminate ac component.

Besides, another purpose of the loop filter is to attenuate signals at the reference

f

u

ω

ω

Fig. 2.3 Transfer function of the VCO.

Voltage-controlled oscillator

A typical characteristic of a voltage-controlled oscillator is shown in Fig. 2.3.

Here, the VCO oscillates at an frequencyω , which is determined by the input signal _o ( )

f

u t . The frequency ω is given by o

( ) ( )

o t n K u to f

ω =ω + , (2.2) where K is the VCO gain in _o rad s⋅ −1⋅V−1. Actually, the curve of Fig. 2.3 may be nonlinear, but it usually simplifies the PLL design if the slope is the same everywhere.

2.2.

One bit quantized digital PLL

From analog to digital:

An all digital phase-locked loop (ADPLL) works similar to the analog PLL, but

it is implemented completely by digital circuits. ADPLL is easier to implement and

design, and is less sensitive to voltage variation than analog PLL; however it typically

suffers from the higher phase noise due to quantization error. Normally, a higher

number of quantization bits leads to the lower quantization error. Therefore, most of

the ADPLL system nowadays is quantized by multi-bit ADC to reduce quantization

hardware design or software design. For reducing the complexity of multi-bit

quantization, we introduce the idea of “one bit quantized digital PLL”.

Structure of one bit quantized PLL:

A general operation block diagram of one bit quantized PLL is shown in Fig. 2.4.

As we see, the structure is similar to analog PLL. An obvious difference between one

bit quantized digital PLL and analog PLL is that the signals are always

one-bit-quantized before they are processed.

Comparing with analog PLL, the PD of one bit quantized PLL can not just be a

mixer because the output of one bit quantization is merely +1 and -1. If we

implement the PD of one bit quantized PLL by a mixer, the possible results— +1 or

-1 —can not express the phase difference between input signal and output signal

correctly. Therefore, we have to establish a new PD for one bit quantized system.

The following is the introduction of the new PD.

Phase Detector

(PD)

Loop Filter

(LF)

Numerically-Controlled

Oscillator (NCO)

input signal ( ) (

s t

s kT

)

φ

Fig. 2.4 The block diagram of one bit quantized digital PLL, where φ( )m is the estimated phase difference between (s kT and s) y kT , while ( s) Ωo( )m is the input

2.2.1. The PD of one bit quantized digital PLL

NCO

Phase

Estimation

( )

s t

sgn[ (

s kT

)]

a

b

π

φ

∑

∑

Fig. 2.5 One bit quantized DPD.

In order to design an ADPLL, we utilize the digital phase discriminator (DPD)

instead of APD for the one bit quantized digital PLL. Before analyzing the system in

Fig. 2.5, we would like to explain its operation principle. First, for phase estimation, it

is usual to calculate the phase difference between the input signal and the output

signal via the inphase branch (I ) and the quadrature branch (Q). However, the most special setting for one bit quantized DPD is to accumulate one-bit samplesa and k b . k

As mentioned previously, we can not use only one bit to distinguish the phase

between the input signal and the output signal. For gaining more information from

one bit quantization, we accumulate a and _k b N times to obtain I and Q. _k Therefore, I and Q will have enough information for accurate phase estimation.

Consider an input signal s t( ) given as ( ) cos(2 c )

s t = π f t+θ , (2.3) where f is the carrier frequency, _c θ is an unknown initial phase. Besides, we assume that f is equal to o f , where c f is the output frequency of NCO. In Fig. o

sgn[ ( )] sgn[cos(2 )] sgn[cos(2 ) cos(2 )] sgn[cos cos ], k s c s c s c s k a s kT f kT f kT f kT π π θ π θ ϕ = ⋅ = + ⋅ = + (2.4)

where sgn[ ]x is the polarity function, i.e., sgn[ ] 1x = if x>0, sgn[ ]x = −1 if x<0 and sgn[ ]x =0 if x=0; ϕ_k =4π f kT_{c s}+θ mod 2π, k=0,1…N-1 and N is the total number of samples within T. In Eq. (2.4), a can be referred to the polarity of a k

discrete sinusoid plus a DC bias specified by cosθ . It can be proved ϕ ’s are _k

uniformly distributed over [0, 2 ]π . Define the ratio of negative samples to the total

number of samples within T, given by

,

i

N N

η ₌ − _(2.5)

where N₋ is the number of samples with ak = − . 1

From Fig. 2.6, when 0< ≤θ π , a_k = − only if1 ϕ is within the _k interval[π θ π θ− , + ]. Sinceϕ ’s are uniformly distributed over k [0, 2 ]π , if N is large

enough, the parameter η is approximated by _i 2 . 2 θ θ η π π ≈ = i (2.6)

In contrast, when − ≤ ≤π θ 0,ak = − only if1 ϕ is within the intervalk [π θ π θ+ , − ].

In this case, 2 . 2 θ θ η π π − − ≈ = i (2.7)

From Eq. (2.6) and Eq. (2.7), θ can be derived from η with polarity ambiguity. i

The ambiguity can be resolved with the Q-channel signal. In the similar process, we

obtain

sgn[ sin sin ],

k k

b = − θ+ ϕ (2.8) where ϕk =4π f kTc s+θ mod 2π and k=0,1…N-1.

I

Q

π θ

−

π θ

+

ϕ

Fig. 2.6 The phase discriminator of one bit quantized software-defined receiver

Define ' , q N N η ₌ − _(2.9)

where N'₋is the number of samples with bk = − . We obtain 1 1 2 q θ η π ≈ + if 2 2 π _θ π − ≤ < ; (2.10) 3 2 q θ η π ≈ − if 3 2 2 π _θ π ≤ < . (2.11) From Eq. (2.10) and Eq. (2.11), we have

1 2 q η > if 0< ≤θ π ; (2.12) 1 2 q η ≤ if − < ≤π θ 0. (2.13)

As a result, the polarity of θ can be acquired directly from η . From Eqs. _q (2.6)-(2.7) and Eqs. (2.12)-(2.13), the phase θ can be obtained by

1

sgn( )

2

q i

θ = η − ⋅η π . (2.14) In addition, from the implementation point of view, the two negative sample counters

can be obtained from summation output I and Q in Fig. 2.5, that is,

2 i N I N η = − , 2 q N Q N η = − . (2.15) Thus, the estimated phase can be derived by

sgn( ) [1 ] 2

π θ = − Q ⋅ − I

N , θ∈ −[ π π, ] (2.16) which makes the proposed approach easily fit in the traditional structure.

Furthermore, even though the initial frequency of input signal and NCO output

signal are different, we still can distinguish the phase difference which is caused by

the different frequency of them. We can apply this characteristic to the one bit

quantized PLL.

When f is not equal to _o f , the estimated phase can be given by _c

2 ( ) [ ] sgn( ) [1 ] 2 2 c o s f f NT I Q N π π φ = − +θ = − ⋅ − , φ∈ −[ π π, ] (2.17) where 2 ( ) 2 c o s f f NT π −

is the average phase difference caused by the frequency

difference between input signal and NCO.

2.2.2. Digital loop filter

In analog PLL, we implement loop filter by low-passed filter in most cases.

Normally, we use an integrator to implement a low-passed filter. For a digital PLL,

since all data are discrete, we replace the integrator with an accumulator [8]. As

shown in Fig. 2.7, the relationship between input and output is written as

( ) ( ) ( 1)

o m i m o m

Ω = Ω + Ω − , (2.18) where Ωi( )m is the input of the accumulator at time m, Ωo( )m is the output and

( 1)

o m

Ω − is the output of the accumulator at time m-1.

1

z

( )

m

Ω

(

1)

m

Ω

−

( )

m

Ω

1

z

( )

m

φ

(

m

1)

φ

−

( )

m

Ω

As will be clear later, the purpose of the accumulator is to attenuate signals that

emanated from the phase estimator, and adjust the input of NCO in finer resolution.

Moreover, we add a function block between the DPD and the loop filter, as shown in

Fig. 2.8.

The polarity of Ω_i( )m is determined by the relative magnitude of φ( )m and

(m 1)

φ − . In other words, the polarity of Ωi( )m provides an information for the NCO to adjust its frequency at time m. The further details will be presented on sec.

3.1.

Finally, we combine above blocks and construct the one bit quantized PLL, as

shown in Fig. 2.9,

One bit quantized

DPD

NCO

( )

s t

φ

( )

m

( )

m

Ω

( )

m

Ω

( )

m

(

m

1)

φ

−

φ

−

( )

(

1)

Ω

m

+ Ω

m

−

( )

y t

2.3. Summary

In this chapter, we introduce a general block diagram of PLL and explain the

function of each block. Besides, we know that ADPLL is easier to design than the

analog PLL. For reducing the complexity of ADPLL, we employ one bit quantization.

Then, we discuss the one bit quantization in PLL and explain one bit phase

estimation.

As we know, PLLs are widely used in tracking systems, and they usually have

narrow capture range. The characteristic is based on analog PLL. However, even

though ADPLL had been investigated, their capture range is still limited. Next, we

Chapter 3.

One Bit Quantized Digital PLL in Noiseless

Environment

As we know, most of the PLLs work in a limited capture range. Take the popular

PLL IC CD4046B for example; its capture range is about 10% of the natural

frequency. In this chapter, we focus on the capture range and propose a new method to

reach an ultra-wide capture range in one-bit quantized PLL. The work is done without

any prior information about input signal frequency.

3.1. Frequency detection

By definition, the phase error of PLL is zero or constant when in lock, and the

frequency of input signal and output signal (of NCO) are the same as well. Here, we

discuss the method to adjust the NCO frequency so as to lock the input signal

Phase

Estimation

( )

s t

sgn[ (

s kT

)]

a

b

sgn[sin(2

π

f kT

)]

sgn[cos(2

π

f kT

)]

( )

m

φ

∑

z

( )

m

(

m

1)

φ

−

φ

−

A

NCO

∑

Fig. 3.1 One bit quantized digital PLL in details.

The signals within the one-bit quantized PLL circuit are defined as follows:

 The input signal ( ) cos(2s t = π f tc +θ), where f is the carrier frequency and c θ

is the initial phase.

 The output signals of NCO are cos(2πf to ) and sin(2πf to ), where f is the o

NCO output frequency.

 T is the sampling period. s

 The multiplication of quantized input signal and quantized output signal (cosine branch) is a , where k k =mN+i, i=0,1,...,N−1 and m=0,1, 2,....

 The multiplication of quantized input signal and quantized output signal (sine branch) is b , where k k=mN+i, i=0,1,...,N−1 and m=0,1, 2,....

 I m( ) is the I-channel output,

( 1) ( ) mN N k k mN I m a + − = =

∑

( 1) ( ) mN N k k mN Q m b + − = =

∑

 The phase difference (phase error) between input and output signal isφ( )m , given by

( ) ( ) sgn[ ( )] [1 ] 2 I m m Q m N π φ = − ⋅ − over [−π π, ]. (3.1)  Ω_i( )m is 1

L times of the difference between φ( )m and φ(m−1), where 1 L is the attenuation parameter. In our implement, 1= 1

10

L is taken.  Ωo( )m is the input of NCO.

 f is the natural frequency of NCO and _n K_VCO is the conversion gain. Here we

take f_n =10 (K Hz)and K_VCO =10 (rad−1).

As we see in Fig. 3.1, there is an algorithm for part A (enclosed by dashed line)

to adjust the output frequency to match the input frequency. Note that the range of

phase estimation is over [−π π, ] in Eq. (2.16). For better understanding, we illustrate the algorithm graphically as in Fig. 3.2-Fig. 3.4. First, we demonstrate the method as

two runners on the playground. We would like to measure which one of the runners is

faster or slower, and then adjust the velocity of the runner. Our purpose is to keep the

two runners at the same velocity.

In the above case, suppose we can measure the distance between the two runners

but can not measure the velocity of them. Besides, the velocity of runner B is

adjustable while that of the runner A is fixed. Assume that is runner A and is

Case Ⅰ: 1 t= −T t =T Starting point Direction

Fig. 3.2 Graphical illustration of CaseⅠ.

As shown in Fig. 3.2, we observe that the distance between runner A and B at

time T is longer than the one at time T-1. It means runner B is slower than runner A.

To keep the two runners at the same pace, we increase the speed of runner B.

Case Ⅱ:

In contrast, as shown in Fig. 3.3, the distance of the two runners at time T is less

than that at time T-1. To keep them in the same velocity, we slow down runner B.

t

=

T

Case Ⅲ: 1 t= −T t=T 1 t= +T Starting point Direction

Fig. 3.4 Graphical conception of CaseⅢ.

In the case of Fig. 3.4, we notice that the distance between the runners is the

same at any time. It means that the velocity of the runners is the same, so no

modification is made.

Corresponding to Fig. 3.2-Fig. 3.4, we describe the phase-adjustment method in

Fig. 3.5-Fig. 3.7. Similarly, the one bit quantized digital PLL can only measure:

1. The phase difference between input signal and NCO output signal at time m,

which is presented by φ( )m .

2. The difference between φ( )m and φ(m−1).

In the case of Fig. 3.5-Fig. 3.7, we assume the phase moves counterclockwise and the

origin is at phase zero. Besides, the frequency of input signal is fixed and our goal is

to adjust the frequency of NCO output signal until it matches input signal. Here, we

may regard the input signal as the runner A, and the output signal of NCO as the

runner B. The phase of input signal at time T is presented by the distance from the

starting point to runner A at time T; the phase of NCO output signal corresponds to

runner B. Therefore, the phase error φ( )m is the distance between the two runners at time m. The velocity is referred to the signal frequency. We describe the system again

in these notations.

Case Ⅰ:

In Fig. 3.5, it shows that the phase error at time m (φ( )m ) is larger than the phase error at time m-1 (φ(m−1)). It means the frequency of NCO is lower than the frequency of input signal, so we have to increase the frequency of NCO.

1 t = −m

t

=

m

(

m

1)

φ

−

φ

Fig. 3.5 The phase variation with time, where the angle of is the phase of input

signal, the angle of is the phase of NCO output signal.

Case Ⅱ: (m 1)

φ

φ

Fig. 3.6 The phase variation with time, where the angle of is the phase of input

In this case, φ( )m is smaller than φ(m−1) as shown in Fig. 3.6. The phenomenon represents that the frequency of NCO output signal is higher than the

frequency of input signal. Hence, we decrease the frequency of NCO.

Case Ⅲ:

1

t

= +

m

(

m

1)

φ

+

(

m

1)

φ

−

1

t

= −

m

( )

m

φ

t

=

m

Fig. 3.7 The phase variation with time, where the angle of is the phase of input

signal, the angle of is the phase of NCO output signal.

In this case, Fig. 3.7 shows that the phase error keeps the same at time m-1, m

and m+1. According to the definition of locked state, it means the PLL is in lock.

Thus, we do not have to adjust NCO frequency.

As a result, the operation principle of part A in Fig. 3.1 can be shown as

if φ( )m −φ(m− ≥1) 0 then Ωi( )m ≥ (3.2) 0, if φ( )m −φ(m− <1) 0 then Ω_i( )m < (3.3) 0. If Ωi( )m ≥ , the frequency of NCO will be slightly increased after 0 Ωi( )m

passes through an accumulator which is made for a finer resolution. On the contrary,

if Ωi( )m < , the frequency of NCO will be slightly decreased. Besides, there is a 0 limitation onφ( )m −φ(m−1). To distinguish the polarity of φ( )m −φ(m−1), we have to limit φ( )m −φ(m−1)over[−π π, ]. In other words, we have to revise Eq. (3.2)-(3.3) as

if 0≤φ( )m −φ(m− <1) π then Ωi( )m ≥ 0, (3.4) if − ≤π φ( )m −φ(m− <1) 0 then Ω_i( )m < 0. (3.5) However, becauseφ( )m is over [−π π, ], therefore φ( )m −φ(m−1) may have problems when the adjacent φ( ) and (m φ m−1)cross the boundary. Thus, we modify the value ofφ( )m −φ(m−1)if it is out of [−π π, ]. The modifications are

if −2π φ≤ ( )m −φ(m− < −1) π

then φ( )m −φ(m− =1) φ( )m −φ(m− +1) 2π, (3.6) and

if π φ< ( )m −φ(m− ≤1) 2π

then φ( )m −φ(m− =1) φ( )m −φ(m− −1) 2π. (3.7)

3.2.

Analysis of one bit digital quantized PLL with

ultra-wide capture range

o

f

(

f

)

(

Hz

)

Capture range

10K

50

Fig. 3.8 The expected capture range of the thesis.

In the thesis, we would like to implement a one bit quantized digital PLL with

ultra-wide capture range. Specifically, our purpose is to obtain the capture range to be

over 90% of the natural frequency.

As shown in Fig. 3.8, f is the input frequency we would like to track, _c f is _o the NCO output frequency and the initial value of f is 10K Hz. In our system, o f o

The tracking procedure of our system is mainly separated into two steps:

Step 1. Information collection:

The frequency detection φ( )m −φ(m−1) is not always accurate, so in the beginning we run the one bit quantized digital PLL many cycles (in our case, we take

200 cycles) without changing the output frequency f . The average frequency _o deviation of the first 200 cycles will be much more accurate.

Step 2. Fine frequency adjustment:

After step 1, we obtain an estimate of φ( )m −φ(m−1). Then we take the advantage of digital PLL, which transfers the output frequency f from 10K Hz to o

around f at once. In other words, _c f is near _o f at the 201st cycle. Thus, we can _c use the method in Section 3.1 to slightly adjust NCO output frequency until f is in o

lock with f . _c

Parameter determination:

A. Sampling frequency:

The sampling frequency f is the inverse of sampling period s T . We take s f s

as about 320K Hz, for a fine resolution of initial f . _o

B. Accumulate N times in the beginning:

The value N is adaptive for different input and output frequency variation.

However, we take N as a fixed value for the first 200 cycles mentioned in step 1. The

followings are the process of the determination of N.

1

(1) 2 ( )

2 fo f NTc s

φ = ⋅ π − + , θ (3.8)

which contains the average phase detection from t=T to t=s NT and the initial phase s

difference θ . The second phase difference is 1

(2) 2 ( ) (1)

2 fo f NTc s

φ = ⋅ π − +φ , (3.9)

where the initial phase becomes φ , and(1) 1 2 ( )

2⋅ π fo− f NTc s is the average phase deviation between t= 2NT and t= (s N+1)Ts.

Besides, we assume f is always higher than_o f at the beginning, and the _c maximum range of φ( )m −φ(m−1) is 2π . Therefore, we can infer that

(2) (1) 2 (f_o f NT_c) _s 2 φ −φ = π − < π (fo f NTc) s 1 ⇒ − < 1 ( _{o c}) _s N f f T ⇒ < − ⋅ ( ) s o c f N f f ⇒ < − s o f N f ⇒ < (3.10) If we take s 1 o f N f   =_{ }−

  , then φ( )m −φ(m− =1) 0 may happen in the experiment. The result may cause a serious error in phase estimation. To avoid the

problem, we take N as 5 (2) (1) 2 ( ) 8 o c s f f NT φ −φ = π − < +π π, (3.11) then 13 16 s o f N f   =    . (3.12)

In our implementation, if N is an even number, a serious problem may happen, that is,

( 1) sgn[ ( ) 0] 0, ( ) + − = = = =mN

∑

Therefore, we take N as the maximum odd number of Eq. 3.12 in the simulation.

C. 200 cycles of information collection:

We would like to make sure that the number of sampling is sufficient for

detecting the phase. At least, the total sampling time has to reach almost one period of

every signal. The step makes sure that we can collect the phase information of four

quadrants in every signal. In our case, the lowest possible frequency is 50 Hz, so we

take 200 times information collection to confirm that we still have enough frequency

variation information even if the frequency is only 50Hz. From Eq. (3.12).

( )

2πNT_s× f_c ×200≈2π . (3.14)

3.3. The tracking procedure

In this section, we will discuss the whole process of one bit quantized digital

PLL, including details of every parameter. However, the different input frequency

results in the different process. Here, we divide the input frequency into three parts

and discuss the process of each situation.

Note that the following discussion is based on the assumption of f =10K Hz o

and f_s ≈320K Hz

A. Middle input frequency ragne

o

f

(

Hz

)

f

10K

50

270

8k

The range of middle input frequency is shown in Fig. 3.9, which is about 270 Hz

to 8K Hz . The method we deal with middle input frequency is as mentioned in the

beginning of Section 3.2.

Step 1. Information collection

The function of step 1 has been introduced previously, so we directly take N=25

by Eq. (3.11). The concept can be illustrated graphically in Fig. 3.10.

As shown in Fig. 3.10, we observe that the output frequency is unchanged when

m=1~199. In the period, the system keeps accumulating φ( )m −φ(m−1). Until m=200, we finish our last accumulation and measure an accurate value of ∆f . We employ ∆f in Eq. 3.15 as the input of NCO. After adjusted, the output frequencyf o

is quite close to the input frequency f , where _c

200 1 1 1 [ ( ) ( 1)] 2π 200 = φ φ   ∆ = ⋅_ ⋅ − − _ 

∑

Phase

Estimation

( )

s t

sgn[ (

s kT

)]

a

b

sgn[sin(2

π

f kT

)]

sgn[cos(2

π

f kT

)]

( )

m

φ

∑

z

( )

m

(

m

1)

φ

−

φ

−

NCO

∑

200

m

=

f

∆

Phase

Estimation

( )

s t

sgn[ (

s kT

)]

a

b

sgn[sin(2

π

f kT

)]

sgn[cos(2

π

f kT

)]

( )

m

φ

∑

z

( )

m

(

m

1)

φ

−

φ

−

NCO

∑

Fig. 3.11 The block diagram when m>200.

Step 2. Fine frequency adjustment:

Starting from m=201, the system enters another state which is one bit quantized

digital PLL with narrow capture range as shown in Fig. 3.11. One parameter which

we have to emphasize is N. Now, f is quite close too f , so we do not have to worry c

about the limitation of φ( )m −φ(m−1). As a consequence, we take N=1001 to achieve a much finer resolution and assure the sampling time in one cycle is sufficient

for phase estimation.

cycles

(

)

f Hz

201

10k

5k

a

_b

13

In :

,

16

In :

1001.

f

a N

f

b N





= 







=

As shown in Fig. 3.12, the ideal outcome should graphically be similar to the figure.

B. Lower input frequency range

o

f

(

Hz

)

f

_10K

50

270

Fig. 3.13 General range of middle input frequency.

In this case, the range of lower input frequency as shown in Fig. 3.13 is around

50Hz to 270 Hz. The process of tracking the lower input frequency is quite similar to

part A of Section 3.3.

Step 1. Information collection

As shown in Fig. 3.10, we observe that the output frequency is unchanged when

m=1~199. In the period, the system keeps accumulating φ( )m −φ(m−1).

Until m=200, we obtain an accurate value of ∆f . We use ∆f to be the input of NCO as Fig. 3.10. Afterwards, the output frequency f is very close to the input _o frequency f . c

Step 2. Fine frequency adjustment:

Starting from m=201, the system enters another state which is one bit quantized

digital PLL with narrow capture range as shown in Fig. 3.11. Still, we have to

emphasize the parameter N. Now, f is quite close to_o f , so we do not need to _c consider the limitation of φ( )m −φ(m−1). However, if we take N=1001, the sampling time in one cycle is not sufficient for lower frequency. For instance, assume

the signal of 100 Hz to nearly a period in one cycle. Because the sampling frequency

s

f is about 320K Hz, we have to take almost 3200 times. Obviously, N=1001 is not sufficient for lower frequency.

In this case, the parameter N is given by

201 13 16( ) s o f N f   =     (3.16)

where (fo)201is the value of f when m=201. o

cycles

(

)

f Hz

201

10k

100

a

b

Fig. 3.14 Expected outcome of one bit digital quantized PLL with lower input

frequency.

As shown in Fig. 3.14, the ideal outcome should be graphically similar to the figure.

C. Higher input frequency range

o

f

(

Hz

)

f

_10K

50

The following discussion is based on the input frequency which is located around

8K Hz to 10K Hz as shown in Fig. 3.15. The process of tracking higher input

frequency is mainly split into three parts.

Step 1. Information collection

Repeating the process of step 1 in part A of Section 3.3, we would like to

measure an accurate frequency difference between input and output signals. However,

with higher input frequency, some problems may occur.

When m=1~200, we take N=25 as usual. It is a coarse resolution for phase

estimation. This is also the reason why we have to take an average of phase estimation

on the first 200 cycles. Consider the value of φ( )m −φ(m−1), given by ( )m (m 1) 2 (f_o f NT_c) _s over [0, 2 ]

φ −φ − = π − π . (3.17)

A

B

C

Fig. 3.16 Phase diagram of φ( )m −φ(m−1).

For higher input frequency, the value of φ( )m −φ(m−1) is quite small comparing with middle and lower input frequencies. Therefore, we might misjudge

( )m (m 1)

φ −φ − . As shown in Fig. 3.16, the value A is the correct value of

( )m (m 1)

φ −φ − . In the process of estimation, the misjudged value might locate between value B and value C. We take the value B for instance. Note that

system will present, for example, A=0.2π but B=1.8π . If we take the misjudged

value into the estimation system, the outcome of ∆f will be erroneous.

Step 2. Information re-collection

Therefore, we set a counter in the first 200 cycles. The counter is to calculate the

number of ( )φ m −φ(m− ≤1) 50. Once the number of ( )φ m −φ(m− ≤1) 50 is over 70 within the first 200 cycles, we assume that the outcome of ∆f will not be accurate.

To be more specific, we regard the input frequency as sufficiently high when the

number of ( )φ m −φ(m− ≤1) 50 is over 70 within the first 200 cycles. To avoid the mistake, we drop the outcome of ∆f and re-estimate φ( )m −φ(m−1) with longer sampling times in each cycle. In other words, we increase N as follows:

( )m (m 1)=2 (fo 7.8 )K NTs 2 φ −φ − π − < π 1. 10 7.8   ⇒ =_{ }− −   s f N K K (3.18)

If we modify N as 2 (π f_o−8 )K NT_s <2π , the value of φ( )m −φ(m−1) might cross the boundary 0 and 2π when fc ≈8 (K Hz) . On the other hand, when f_c ≈10K (Hz) , N should be large enough to assure φ( )m −φ(m−1) is sufficient. To satisfy the tradeoff, we take N with Eq. (3.18).

Besides, in the re-estimate part, we do not need 200 cycles to estimate

( )m (m 1)

φ −φ − because we have already known that input frequency is sufficient

high. In other words,

( )

In Fig. 3.17, we observe that the output frequency is still fixed as original value

estimate ∆f ' as 300 201 1 1 ' [ ( ) ( 1)] 2π 100 = φ φ   ∆ = ⋅_ ⋅ − − _  m

∑

When m=300, we finish our last accumulation and measure an accurate value of

' f

∆ . We employ ∆f ' as the input of NCO. After adjusted, the output frequencyf o

is quite close to input frequency f . _c

In summary, there are two advantages to increase N in Step 2:

1. Get finer resolution: decrease the range of misjudging.

2. Keep the value of φ( )m −φ(m−1) away from the boundary 0 and 2π .

Phase

Estimation

( )

s t

sgn[ (

s kT

)]

a

b

sgn[sin(2

π

f kT

)]

sgn[cos(2

π

f kT

)]

( )

m

φ

∑

z

( )

m

(

m

1)

φ

−

φ

−

NCO

∑

Step 3. Fine frequency adjustment:

The block diagram is shown in Fig. 3.11. The only parameter we revise here is

that the block diagram occurs when m>300. Starting from m=301, the system is in

another state which is one bit quantized digital PLL with narrow capture range. In the

period, we take N=1001 for the same reason as before. After a few adjustments, the

output frequency is supposed to be in lock with input frequency. As shown in Fig.

3.18, the ideal outcome should be graphically similar to the figure.

cycles

(

)

f Hz

301

10k

9k

201

a

_b

c

Fig. 3.18 Expected outcome of one bit quantized digital PLL with higher input frequency.

D. Summary

Fig. 3.19 is the flowchart of distinguishing f in the first 200 cycles. Define _c

: number of cycles

m ,

: number of samples in each cycle

N ,

10 ,

320 .

f

K Hz

f

K Hz

=

≈

counter<70

13

1001

16(

)

f

N

f





=

_

_

>





Yes

No

No

Yes

when m=201

lower

f

middle

f

higher

f

Fig. 3.19 Flowchart of distinguishing input frequency

After distinguishing the input frequency during the first 200 cycles, we start the

process of fine frequency adjustment. Finally, we achieve the one bit quantized digital

PLL with ultra-wide capture range.

3.4. Simulation Results

We simulate the system with MATLAB. The followings are simulation results of

A. Middle input frequency range

Here we illustrate the tracking process for four values of f over middle c

frequency range and show the NCO output frequency at a specific cycle where X is

the number of cycles and Y means the value of NCO output frequency in Hz.

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 f o (H z ) number of cycles f_c = 7800(Hz) X: 201 Y: 7793 X: 200 Y: 1e+004 X: 2001 Y: 7800 X: 1 Y: 1e+004

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 1 Y: 1e+004 f o (H z ) number of cycles f_c = 5000(Hz) X: 200 Y: 1e+004 X: 2112 Y: 5000 X: 201 Y: 4995

Fig. 3.21 The locking process of f 5000 Hz. c

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 201 Y: 3297 f o (H z ) number of cycles f_c = 3300(Hz) X: 200 Y: 1e+004 X: 45 Y: 1e+004 X: 2001 Y: 3300

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 200 Y: 1e+004 f o (H z ) number of cycles f_c = 770(Hz) X: 201 Y: 761 X: 1 Y: 1e+004 X: 2001 Y: 769.9

Fig. 3.23 The locking process of f 770 Hz. c

B. Lower input frequency range

Here, we depict the locking procedure for four values of f over lower _c frequency range and show the output frequency at a specific cycle where X is the

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 200 Y: 1e+004 f o (H z ) number of cycles f_c = 250(Hz) X: 1 Y: 1e+004 X: 201 Y: 249 X: 2519 Y: 249.9

Fig. 3.24 The locking process of f 250 Hz. c

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 200 Y: 1e+004 f o (H z ) number of cycles f_c = 180(Hz) X: 201 Y: 185 X: 2534 Y: 180 X: 1 Y: 1e+004

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 200 Y: 1e+004 f o (H z ) number of cycles f_c = 100(Hz) X: 24 Y: 1e+004 X: 201 Y: 88.95 X: 2499 Y: 100

Fig. 3.26 The locking process of f 100 Hz. c

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 200 Y: 1e+004 f o (H z ) number of cycles f_c = 50(Hz) X: 1 Y: 1e+004 X: 201 Y: 56.95 X: 2492 Y: 50.16

C. Higher input frequency range

We illustrate the tracking process for four values of f over higher frequency c

and show the output frequency specifically at a specific cycle.

0 500 1000 1500 2000 2500 3000 9960 9965 9970 9975 9980 9985 9990 9995 10000 X: 1 Y: 1e+004 f o (H z ) number of cycles f_c = 9999(Hz) X: 300 Y: 1e+004 X: 2222 Y: 9999 X: 301 Y: 9964

0 500 1000 1500 2000 2500 3000 5000 5500 6000 6500 7000 7500 8000 8500 9000 9500 10000 X: 2326 Y: 9000 f o (H z ) number of cycles f_c = 9000(Hz) X: 301 Y: 8999 X: 300 Y: 1e+004 X: 1 Y: 1e+004

Fig. 3.29 The locking process of f 9000 Hz. c

0 500 1000 1500 2000 2500 3000 5000 5500 6000 6500 7000 7500 8000 8500 9000 9500 10000 X: 2402 Y: 8500 f o (H z ) number of cycles f_c = 8500(Hz) X: 1 Y: 1e+004 X: 300 Y: 1e+004 X: 301 Y: 8516

0 500 1000 1500 2000 2500 3000 5000 5500 6000 6500 7000 7500 8000 8500 9000 9500 10000 X: 1973 Y: 8200 f o (H z ) number of cycles f_c = 8200(Hz) X: 301 Y: 8276 X: 300 Y: 1e+004 X: 1 Y: 1e+004

Fig. 3.31 The locking process of f 8200 Hz. c

D. Simulation results of a ultra-wide capture range

Finally, we observe the locking results of a wide input frequency range. Instead

of showing the locking process, we define that if the final value of f is located o

within [f_c−1,f_c+ when m=3000, the system is called “locked”. We just have to 1] observe the value of f at m=3000, and then we can determine whether the system o

is in-lock or not.

We increase f logarithmically from 50 Hz to 9976 Hz in Fig. 3.32. On Y-axis, c

Y=1 indicates the system is locked and Y=0 shows the system fails to lock. As we see,

our design can lock all the frequencies from 50 Hz to 9976 Hz successfully in

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 -0.5 0 0.5 1 1.5 X: 50 Y: 1 f c (Hz) 1: in -l o cked 0: n o t i n -l o cked

Locked situation in noiseless environment

X: 9976 Y: 1

Fig. 3.32 Locked situation in noiseless environment.

3.5. Summary

In this chapter, we propose methods to deal with different input frequency

signals and then demonstrate one bit quantized digital PLL with ultra-wide capture

range. In the process, the number N is quite important for either the resolution or the

error of phase estimation. Therefore, we modify N to fit different situations. The

unique features of our system are:

1. f is an unknown frequency over [50 Hz, 10K Hz]. _c

2. In noiseless environment, the system achieves almost 99.5% capture range of

the natural frequency.

Chapter 4.

Noise effect

It is known that most of the PLL systems would be affected by noise in reality. In

this chapter, we analyze the performance of one bit quantized digital PLL in noisy

environment. Our discussion is based on the simulation outcomes of different

signal-to-noise ratio (SNR) in dB. We use additive white Gaussian noise (AWGN) to

simulate the noise affect in our system.

4.1. Overview

The model of one bit quantized digital PLL with noise is the same as that in

Chapter 3. The only change is the input signal s t( ), given by ( ) cos(2 _c ) ( )

s t = πf t+θ +n t , (4.1)

where n t( ) is the additive white Gaussian noise.

In addition, we relax the setting of determining whether the system is in-locked

or not. In noiseless case, we find that different input frequency can almost be locked

after m=1000. Therefore, the following discussion is based on calculating the

mean-square-error (MSE) [9] between input frequency and output frequency from

m=1001 to m=3000. If the value of MSE is smaller than 1 Hz, it is called “locked”. In

other words, when the system satisfies

3000 2 1001 1 [( ) ] 1 ( ) 2000 m o m c f f Hz =  ₋ _≤   

∑

Besides, we transform the algorithm of phase estimation from Eq. (3.1) into ( ) ( ) sgn[ ( )] [1 ] 2 ( ) ( ) I m m Q m I m Q m π φ = − ⋅ − + (4.3)

which has more accurate estimation in noisy environment than Eq. (3.1) [10].

Simulation results

We test f increasing logarithmically from 50 Hz to 9976 Hz in Fig. 4.1-Fig. c

4.5. On Y axis of those figures, Y=1 means locked successfully and Y=0 means

unlocked. . 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 -0.5 0 0.5 1 1.5 1: i n -l o cked ; 0: n o t i n -l o cked f_c(Hz) SNR=20dB X: 50 Y: 1 X: 9976 Y: 1

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 -0.5 0 0.5 1 1.5 1: i n -l o cked ; 0: n o t i n -l o cked f_c(Hz) SNR=10dB X: 50 Y: 0 X: 9976 Y: 0

Fig. 4.2 Simulation results with SNR=10 dB.

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 -0.5 0 0.5 1 1.5 1: i n -l o cked ; 0: n o t i n -l o cked f_c(Hz) SNR=0dB X: 50 Y: 0 X: 9976 Y: 0

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 -0.5 0 0.5 1 1.5 X: 50 Y: 0 1: i n -l o cked ; 0: n o t i n -l o cked f_c(Hz) SNR=-10dB X: 9976 Y: 0

Fig. 4.4 Simulation results with SNR=-10 dB.

0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 -0.5 0 0.5 1 1.5 1: i n -l o cked ; 0: n o t i n -l o cked f_c(Hz) SNR=-20dB X: 50 Y: 0 X: 9976 Y: 0

As we see, the higher the SNR, the better the performance. We will discuss the

details in the following section.

4.2. Noise effect

As shown in Fig. 4.1, we found that f between 50~10K Hz could be locked in _o our system when SNR=20 (dB). In Fig. 4.2, the number of successfully locked system

decreases but it only occurs in particular range of f . When SNR=10 dB, there are _o mainly two parts of f being unlocked. o

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 201 Y: 215.1 f o (H z ) number of cycles SNR=10dB & f_c=50(Hz) X: 2242 Y: 270.5

0 500 1000 1500 2000 2500 3000 5000 5500 6000 6500 7000 7500 8000 8500 9000 9500 10000 f o (H z ) number of cycles SNR=10dB & f_c=8072(Hz) X: 1876 Y: 8379 X: 301 Y: 8310 X: 300 Y: 1e+004 X: 1 Y: 1e+004

Fig. 4.7 The unlocked process of f = 8072 Hz with SNR=10 dB. _c

The first part is around the lowest frequency 50 Hz. As shown in Fig. 4.6, the

system can not track and lock the input frequency 50 Hz with SNR=10dB. We

observe that the phase estimation by the first 200 cycles is not sufficient, so (fo)201

is still away from 50 Hz. Obviously, the first step is not able to accurately estimate

∆f and the system will not be locked eventually. In mathematics, we found that the first 200 cycles plays an important role in the system. As discussed in Section 3.2, the

number of 200 cycles is determined by the lowest input frequency to make sure even

the lowest frequency could be sampled almost one period. Nevertheless, the one

period sampling provides insufficient information for phase estimation in noisy

environment. This is the reason why unlock frequencies are close to 50 Hz in Fig. 4.2.

When SNR=10 dB, we found that there are a few unlocked frequencies around

8K Hz. The detail of unlocked process is shown in Fig. 4.7 for f_c =8072 (Hz . We ) analyze the value of f and find that the accurate phase estimation of the first 200 o

cycles is the key factor. In this case, the reason for a wrong estimation of the first 200

cycles is concerning with the accumulated value of counter and the value of

( )m (m 1)

φ −φ − . As discussed in part C of Section 3.3, if φ( )m −φ(m−1) is small, the system might have a wrong estimation of φ( )m −φ(m−1). In a noiseless environment, the value of φ( )m −φ(m−1). However, in a noisy environment, there are many serious misjudgments. Those misjudgments make the phase estimation

inaccurate. At the same time, the value of counter is not larger than 70 for the case of

c

f = 8072 Hz, so the system can not enter “the higher frequency judgment” mode. Hence, the system is unlocked.

0 500 1000 1500 2000 2500 3000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 X: 201 Y: 2271 f o (H z) number of cycles SNR=0dB & f_c=2000(Hz) X: 2125 Y: 2321