Analysis of application of the IDDQ technique to the deep sub-micron VLSI testing

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Analysis of Application of the IDDQ Technique to the Deep Sub-Micron

VLSI Testing

CHIH-WEN LU

Department of Electrical Engineering, National Chi Nan University, Nantou Hsien, Taiwan, ROC

cwlu@ncnu.edu.tw

CHUNG LEN LEE

Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC

cllee@cc.nctu.edu.tw

CHAUCHIN SU

Department of Electrical Engineering, National Central University, Chung-Li, Taiwan, ROC

ccsu@ee.ncu.edu.tw

JWU-E CHEN

Department of Electrical Engineering, Chung Hua University, Hsinchu, Taiwan, ROC

jechen@chu.edu.tw

Received May 15, 2001; Revised August 8, 2001

Editor: Kuen-Jong Lee

Abstract. In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1× 107gates, are still differentiable under the condition of random process deviations

and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.

Keywords: IDDQ testing, deep sub-micron, VLSI

1. Introduction

IDDQ testing is an effective testing technique to detect many non-stuck-at fault defects, such as gate oxide de-fects and bridging faults, which are likely to become more important due to the continued shrinking of

de-vice dimensions [2, 3]. However, recently, a work by Williams et al. [10] reported that it will be difficult to apply the IDDQ testing to the deep sub-micron VLSI due to the increased sub-threshold current of the MOS transistor which makes the IDDQ for the defective de-vices be difficult to be differentiated from that of the

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good devices. This is especially true if the distribution of the IDDQ current due to the process variation and different input vectors, which cause different magni-tude of IDDQ current, is considered.

The IDDQ current of VLSI devices is intrinsically statistical, i.e., it falls into a distribution, usually nor-mal distribution. The “mean” and “standard deviation” are two important parameters to be considered when a line is to be drawn between the IDDQ currents of good devices and defective devices. Recently, Lu et al. pro-posed a new current difference testing scheme which, instead to measure the “mean”, i.e., the absolute values of IDDQ currents, compares the IDDQ currents of a single defective chip under different input vectors [4]. If the additional defective current exceeds six times of the “standard deviation” of the IDDQ current distribu-tion of good devices, the defective device is considered “detected”. This greatly increases the resolution of dif-ferentiation of the good device and the defective device for the IDDQ testing.

In this work, the distributions of the IDDQ currents for the deep sub-micron CMOS in the year of 2011, which has a feature size of 50 nm, are studied consid-ering both the process variation and the random input vectors. It is found that although the mean of the dis-tribution of the IDDQ current is almost linearly pro-portional to the size of circuit, the standard deviation of the IDDQ distribution is proportional to the square root of the circuit size. For the worst case estimation for the VLSI of year 2011, the standard deviation is only approximately 5.67 µA for a circuit of the size of 1× 107 gates while the minimum additional de-fect current is 34.1 µA. That means that the IDDQ currents of the good and defective devices are still dif-ferentiable. Based on the estimated results, two IDDQ testing schemes which can detect the defects in a deep sub-micron VLSI are proposed. Through this study, it is concluded that the IDDQ testing is still applicable to deep sub-micron CMOS VLSI for the next ten years.

2. Estimation of Defect-Free and Defective IDDQ

The IDDQ current is caused by several kinds of leak-age currents which are sub-threshold current, reverse-biased p-n junction leakage current, gate-induced drain leakage current, bulk punch-through current and tun-neling current [1]. All the leakage currents are affected by the process variation, the states of the circuit [9], and the input vector. In this section, the distributions of the IDDQ currents of the defect-free and defective CMOS

devices will be analyzed considering the above factors. The analysis is of a hierarchical approach, i.e., starting from the transistor device level considering the process variation, to the circuit level considering the states of gates.

2.1. Estimation of Defect-Free IDDQ

In the deep sub-micron region, the sub-threshold cur-rent grows exponentially due to the scaled down of the threshold voltage. Hence, only the sub-threshold cur-rent of the MOS transistor is considered.

The sub-threshold current of a MOS is given by [6]:

Is= µ0 ox Tox W L V 2 t exp  VGS− VT+ ηVDS nVt  (1)

whereµ0 is the carrier surface mobility,oxis the di-electric permitivity of oxide, Toxis the oxide thickness,

W is the channel width, L is the channel length, Vt is the thermal voltage, VT is the threshold voltage, n is a technology dependent parameter andη models the drain induced barrier lowering (DIBL). The variation of the sub-threshold current is mainly caused by the vari-ations of W, L, Toxand VT. Assuming that the process variation of W, L, Toxand VTare normal distributions, we can calculate the expected value and variance of sub-threshold current in a NMOS or PMOS transistor,

E[IS] and VAR[IS], by [5]

E[Is]=  µW+3σW µW−3σW  µL+3σL µL−3σL  µTox+3σTox µTox−3σTox  µVT+3σVT µVT−3σVT Is ×√ 1 2πσW exp  −(W − µW)2 2σ2 W  ×√ 1 2πσL exp  −(L − µL)2 2σL2  ×√ 1 2πσTox × exp  −  Tox− µT ox 2 2σ2 Tox ×√ 1 2πσVT × exp  −  VT − µVT 2 2σ2 VT d W d Ld Toxd VT (2) E Is2 =  µW+3σW µW−3σW  µL+3σL µL−3σL  µTσ x+3σTox µTσ x−3σTox  µVT+3σVT µVT−3σVT Is2 ×√ 1 2πσW exp  −(W − µW)2 2σW2 

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×√ 1 2πσL exp  −(L − µL)2 2σ2 L  ×√ 1 2πσTox × exp  −  Tox− µTox 2 2σT2ox ×√ 1 2πσVT × exp  −  VT− µVT 2 2σV2T d W d Ld Toxd VT (3) VAR[Is]= E2[Is]− E Is2 (4) STD[Is]= VAR[Is] (5)

whereµW, µL, µTox, µVT, andσW, σL, σTox, σVT are the

mean and the standard deviation of W, L, Toxand VT respectively.

For a CMOS logic gate, the subthreshold current is caused from the off-state MOS transistor(s) which is(are) either NMOS or PMOS transistors. The involved MOS transistors are determined by each state of the gate. Hence, the expected value and variance are state-dependent. They can be calculated from Eqs. (2)–(5) for each state.

For the circuit level, we start from the process vari-ation. Under one input vector, the IDDQ of a circuit is a function of process variation. The logic simula-tor can determine all the states of the logic gates for a given input vector. Since the leakage distribution and the states of all CMOS gates are known, the total IDDQ of a circuit can be obtained by summing the currents of all gates. According to the central limited theorem [5], the defect-free IDDQ is a normal distribution. The mean is the summation of the means of all gates. Since the states of all gates have been determined, the leak-age currents of all gates are mutually independent. The variance of a circuit is the summation of the variances of all gates. The standard deviation is the square root of the variation. Its expected value, E[IDDQ(p)], variance,

VAR[IDDQ(p)], and standard deviation, STD[IDDQ(p)], are expressed as follows:

IDDQ(p) = Ng  i=1 Igate,i (6) E[IDDQ(p)] = Ng  i=1 E[Igate,i] (7) VAR[IDDQ(p)] = Ng  i=1 VAR[Igate,i] (8) STD[IDDQ(p)] = VAR[IDDQ(p)] (9)

where Igate,i is the leakage of the i th gate. Ng is the gate number. E[Igate,i] and VAR[Igate,i] are the expected value and variance of the i th gate respectively.

Finally, the IDDQ distribution, which is not only a function of process variation but also input vec-tor, can be obtained by simulating the logic simula-tor for a set of random vecsimula-tors. From the conditional expectation [5], the expected value, E[IDDQ(p, v)], variance, VAR[IDDQ(p, v)], and standard deviation,

STD[IDDQ(p, v)], of IDDQ for a set of Nvrandom vec-tors are expressed as follows:

E[IDDQ(p, v)] = 1 Nv Nv  j=1 Ej[IDDQ(p)] (10) VAR[IDDQ(p, v)] = 1 Nv Nv  j=1 (Ej[IDDQ(p)] − Ej[E[IDDQ(p, v)]])2 + 1 Nv Nv  j=1 Varj[IDDQ(p)] (11) STD[IDDQ(p, v)] = VAR[IDDQ(p, v)] (12)

The defect-free IDDQ of a circuit can then be ob-tained by this hierarchical approach. However, some-times we need a simple formula to calculate the stan-dard deviation for a defect-free circuit. The variance of a circuit is the summation of the variances of all gates (Eq. (8)). The standard deviation is the square root of the variation. Hence, for the worst case, the maximum standard deviation, STDmax[IDDQ], of a circuit can be

expressed as:

STDmax[IDDQ]= Max

NgSTD[Igate] (13)

2.2. Estimation of Defective IDDQ

For the defective circuit, the activated defect draws an excessive current. The additional current is added to the total current. The total IDDQ current can be expressed as follows: Idefective = Ng  i=1 Igate,i+ Id (14)

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3. Estimated Results 3.1. Defect-Free IDDQ

In order to estimate the subthreshold current for the fea-ture technology, the values of technology parameters are given and shown in Table 1. The values of Tox, L and VDD are predicted by the International Technol-ogy Roadmap for Semiconductors (ITRS) 1999 Edi-tion for the year 2011 [8]. From Eq. (1) and Table 1, the subthreshold currents per unit channel width are 81.3 nA/µm and 37.9 nA/µm for NMOS and PMOS respectively. These estimated values are in the same order as the values predicted by the Roadmap. For the estimation of IDDQ in CMOS gates, the values of width for inverter, 2-input NAND and 2-input NOR are shown in Table 2. The minimum width is assumed 0.1µm. The process variation within a single chip is expected smaller then the variation between different chips. The values of process variations between differ-ent chips (called off-chip here) and within a single chip (called on-chip) are shown in Table 3, where the values of 3σL and 3σV T for off-chip ICs are predicted by the

Roadmap. The values for on-chip ICs are assumed as half of the values for off-chip ICs.

From Eqs. (2)–(5) and Tables 1–3, the IDDQ distri-bution of CMOS gates for each state can be estimated. Table 4 shows the expected values and standard

devi-Table 1. Values of technology parameters for the year 2011.

µn µp Tox L Vt

750 cm /v-s 350 cm/v-s 0.7 nm 50 nm 25 mV

VT VDD Wmin n η

0.15 V 0.6 V 0.1µm 1.03 0.01

Table 2. Values of width for inverter, 2-input NAND and 2-input NOR.

INVERTER NAND NOR

PMOS 0.2µm 0.2µm 0.4µm

NMOS 0.1µm 0.2µm 0.1µm

Table 3. Values of process variations for off-chip and on-chip ICs. 3σW 3σL 3σTox 3σVt

Off-chip 10 nm 3.2 nm 0.07 nm 17 mV On-chip 5 nm 1.6 nm 0.035 nm 8.5 mV

Table 4. Expected values and standard deviation of inverter, 2-input NAND and 2-input NOR for off-chip ICs and on-chip ICs.

INVERTER NAND NOR

off-chip 00 8.130, 1.862 nA 14.472, 3.286 nA 16.260, 2.633 nA 01 7.588, 1.723 nA 16.260, 3.692 nA 15.176, 3.439 nA 10 16.260, 3.692 nA 15.176, 3.439 nA 11 15.176, 2.437 nA 13.507, 3.061 nA on-chip 00 7.974, 0.904 nA 14.195, 1.596 nA 15.948, 1.278 nA 01 7.443, 0.837 nA 15.948, 1.793 nA 14.885, 1.670 nA 10 15.948, 1.793 nA 14.885, 1.670 nA 11 14.885, 1.183 nA 13.248, 1.486 nA The first value is the expected value and the second one is the standard deviation.

Table 5. The maximum standard deviation,σg, among all gates

for different W/L ratios for the year of 2011.

W/L 20 15 10 5 3 2

σgnA (off chip) 38.82 27.62 18.41 9.210 5.530 3.692

σgnA (on chip) 17.88 13.41 8.941 4.472 2.685 1.793

ation of inverter, 2-input NAND and 2-input NOR for each state for off-chip and on-chip ICs respectively, where the first value is the expected value and the sec-ond one is the standard deviation. The maximum stan-dard deviations of the gates are 3.692 nA and 1.793 nA for off-chip and on-chip ICs respectively. The maxi-mum standard deviations of the gates for other W/L ratios can be obtained by the same procedure and they are shown in Table 5.

The magnitude of IDDQ of a CMOS circuit can be calculated by Eq. (6). Fig. 1 shows the simulated result on the sample histogram of the defect-free IDDQ cur-rent for the same circuit under 2000 random input vec-tors. From this figure, it can be seen that the defect-free IDDQ is a normal distribution. The standard deviation is only 24.65 nA, which is small as compared with the expected value of 39.13µA.

The expected value and standard deviation of a CMOS circuit can be obtained by Eqs. (6)–(12). Fig. 2 shows the expected values versus the gate number for 2000 random input vectors for off-chip and on-chip c6288 circuits. Here the gate number means the parti-tioned size of circuit. The solid line is for the off-chip IC and the dash line is for the on-chip IC. From this

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Fig. 1. The simulated result on the sample histogram of the defect-free IDDQ current for the ISCAS’85 circuit c6288 under 2000 random input vectors.

Fig. 2. The expected values of IDDQ versus the gate number for 2000 random input vectors for off-chip and on-chip c6288 circuits.

figure, it can be seen that the defect-free IDDQ is almost linearly proportional to the size of the circuit. Simu-lation for other benchmark circuits shows the similar result.

The IDDQ of a circuit is a function of process varia-tion and input vector. The standard deviavaria-tion due to the process variation can be obtained from Eqs. (8) and (9)

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Fig. 3. (a) The standard deviations of defect-free IDDQ versus the gate number for off-chip c6288 circuit. The dash line is the standard deviation due to the process variation and the solid line is the standard deviation due to the pro-cess variation and different input vectors. (b) The standard deviations of defect-free IDDQ versus the gate number for on-chip c6288 circuit. The dash line is the standard devi-ation due to the process varidevi-ation and the solid line is the standard deviation due to the process variation and different input vectors.

while the standard deviation due to the process varia-tion and input vector can be obtained from Eqs. (11) and (12). Fig. 3(a) and (b) shows the standard devia-tions of defect-free IDDQ versus the gate number for off-chip and on-chip c6288 circuits respectively. The

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Fig. 4. The simulation result of maximum standard de-viation for off-chip and on-chip ICs for the technology of the year 2011. The solid line is for off-chip ICs and the dash line is for on-chip ICs.

dash lines are the standard deviation due to the process variation while the solid lines are the standard deviation due to the process variation and different input vectors. From these two figures, they can be seen that the solid lines approach to the dash lines as the size of circuit increases. That is: the process variation dominates the IDDQ variation of a large circuit. From Eqs. (8) and (9), the standard deviation is proportional to the square root of the circuit size.

For the worst case, the maximum standard deviation of a circuit can be obtained from Eq. (13). Fig. 4 shows the simulated results of maximum standard deviation for W/L ratio of 2 for off-chip and on-chip ICs. The solid line is for off-chip ICs and the dash line is for on-chip ICs. The maximum standard deviation is only 16.5µA for off-chip ICs and 8.02 µA for on-chip ICs even the gate number is up to 2× 107. Simulation for

other W/L ratios shows the similar results.

3.2. Defective IDDQ

Bridging defect resistances have been measured using a process defect monitor for CMOS technology [8]. The majority of the bridges were found to have low re-sistances (below 500 ). However, a small percentage was found in the range of 500 to 20 K . Spectro-scopic analysis of these high resistive bridges showed that the material of the defects could not cause the high resistances. They could be the geometry of the defects

Table 6. The minimum defective current for different W/L ratios for the year of 2011.

W/L 20 15 10 5 3 2

IdµA 226 187 139 78.7 49.8 34.1

resulting in one or two poor contacts. The low resis-tance is expected to have a smaller value in the future due to the smaller space between two bridging nodes. Experiments have shown that more than 95% of the bridging defect resistance values are equal to or less than 1 k . In this work, the value of 1 k is used to estimate the excess defect current. For the estimation of minimum defect current, it is assumed that the de-fect is located between the output of a two-input NOR gate and the output of a two-input NAND gate. The on currents of PMOS and NMOS, which are predicted by 1999 ITRS Roadmap for year of 2011, are 750µA/µm and 350 µA/µm respectively. VDD is 0.6 V. Then, the values of on resistance for PMOS and NMOS are 1.714 K -µm and 0.8 K -µm respectively. Hence the minimum defect current is as:

Id,min=

VDD

2Ron,PMOS+ Rdefect,max+ 2Ron,NMOS

= 34.1 µA (15)

The minimum defective current, Id,min, which are shown in Table 6, for different minimum W/L ratios for the year of 2011 are also calculated.

4. The Maximum Circuit Size for Partitioning

We have shown that the standard deviation is propor-tional to the square root of circuit size. As the size of CUT is increased to a very large value, 6σ of the CUT will be larger than the additional defective cur-rent. That is: the two distributions of defect-free and defective IDDQ will be partially overlapped. Fig. 5(a) depicts this situation where 6σ of the CUT is larger than the additional defective current. In order to separate the two distributions, the CUT should be partitioned into several sub-circuits. The 6σ of sub-circuits should be smaller than the additional defective current, Id,min. The IDDQ testable scheme is shown in Fig. 5(b) in which the 6σ of sub-circuits is smaller than the additional defective current so that the two distributions are dif-ferentiable. From Eq. (13) and Table 5, the maximum partition size for different W/L ratios for the year of 2011 are shown in Table 7.

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Table 7. The maximum partition size (gate number) for different W/L ratios for the year of 2011.

W/L 20 15 10 5 3 2

Size (off chip) 1× 106 1.2 × 106 1.5 × 106 2× 106 2.2 × 106 2.3 × 106 Size (on chip) 4.4 × 106 5.4 × 106 6.7 × 106 8.6 × 106 9.5 × 106 1× 107

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Fig. 5. (a) 6σ of the CUT is larger than the additional defective current so that the two distributions of defect-free and defective IDDQ overlap partially. (b) 6σ of sub-circuits smaller than the ad-ditional defective current so that the two distributions are separated.

5. Testing Schemes Based on Estimated IDDQ

In order to distinguish the non-overlapped distribu-tions, we propose two IDDQ testing schemes to detect the current difference of the deep sub-micron VLSI.

5.1. Current Difference Scheme I

Fig. 6 shows the first testing scheme. The IDDQ cur-rents of the CUT are measured by applied several vec-tors. If the defect is activated by some one vector, it will draws an additional current in the IDDQ. If the IDDQ difference between two vectors is greater than 6 times of standard deviation, 6σon-chip, the CUT is

de-clared as a faulty circuit. The standard deviation of the CUT should be estimated before IDDQ testing. The measurement of IDDQ of this scheme can be either measured by external current sensors or built-in cur-rent sensors (BICSs).

5.2. Current Difference Scheme II

Fig. 7 shows the second testing scheme which com-pares the IDDQ currents between two chips under the same vector. If the IDDQ difference is greater than 6σoff-chip, the chip, which draws a larger IDDQ,

ex-ists at least one defect. The IDDQ measurement of this scheme can only be measured by external current sensors.

Fig. 6. Current difference scheme I. The IDDQ currents of CUT are measured for several testing vectors.

Fig. 7. Current difference scheme II. The IDDQ currents of two chips are measured under the same input vector.

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Table 8. The maximum partition size of the proposed two IDDQ testing schemes for W/L = 2 for the CMOS technology of year 2011.

Scheme I Scheme II maximum partition size 1× 107 2.3 × 106

The IDDQ distributions have been simulated by considering the process variation and different input vectors. The simulated results show that the process variation dominates the IDDQ variation. For test-ing scheme I, IDDQ currents are measured on-chip (for the same chip) while for testing scheme II, they are measured off-chip (for different chips). The vari-ance of an on-chip ICs is expected to be smaller than that of off-chip ICs. Hence, the IDDQ testing scheme I is expected to have a better resolution. The maximum partition size of the above two schemes for W/L = 2 for the year of 2011 are shown in Table 8. For a CUT containing 1× 108gates as an example, the minimum numbers of sub-circuits for on-chip testing (scheme I) and off-chip testing (scheme II) are 10 and 44 respec-tively for the year 2011. If the partition is based on the estimation of the above procedure rather than based on the worst case, the partition number can be fur-ther reduced. Hence, in this work, we conclude that IDDQ testing, which is based on the current difference scheme, is still applicable for the next ten years.

6. Conclusion

The distribution of defect-free IDDQ of a CMOS deep submicron VLSI circuit for the year of 2011 has been estimated. The estimation considers the process varia-tion and different input vectors. The estimated results show that the process variation dominates the IDDQ variation in a VLSI circuit. The expected value is al-most linearly proportional to the size of the circuit. However, the standard deviation is proportional to the square root of the circuit size.

In this work, the model of the subthreshold current is based upon the present day deep sub-micron VLSI device, and the parameter values were from the In-ternational Technology Roadmap for Semiconductors 1999 Edition. The models and parameter values for es-timating IDDQ currents may be modified for the year of 2011. However, the methodology used can be still applicable to estimate the IDDQ currents.

The defect-free and defective IDDQ distributions of a CMOS VLSI containing 1× 107 gates are still

differentiable for the year of 2011. Two IDDQ test-ing schemes, which detect the defective current of the defective distribution from the good distribution, have been proposed. The scheme which compares IDDQ currents on the same chip ICs has a better res-olution than the scheme which measures IDDQ cur-rents for different chips. We conclude that the IDDQ testing still applicable for CMOS VLSI for the next ten years.

References

1. A. Ferr and J. Figueras, “IDDQ Characterization in Submicron CMOS,” in Proc. ITC, 1997, pp. 136–145.

2. A.E. Gattiker and W. Maly, “Current Signarure: Application,” in Proc. International Test Conference, 1997, pp. 156–165. 3. M. Levi, “CMOS is Most Testable,” in Proc. International Test

Conference, 1981, pp. 217–220.

4. C.W. Lu, C.L. Lee, J.E. Chen, and C. Su “A New Testing Scheme Employing Charge Storage BICS Circuit for Deep Submicron CMOS ULSI,” in Proc. of International Workshop on IDDQ

Testing, 1998, pp. 54–58.

5. P.L. Meyer, Introductory Probability and Statiscal Applications, Addison-Wesley Publlishing Company, 1970.

6. W. Nebel and J. Mermet, Low Power Design in Deep

Sub-micron Electronics, Dordrecht: Kluwer Academic Publishers,

1997, p. 99.

7. R. Rodriguez-Montanes, E.M.J.G. Bruls, and J. Figueras, “Bridging Defects Resistance Measurements in a CMOS Pro-cess,” in Proc. ITC, 1992, pp. 892–899.

8. The International Technology Roadmap for Semiconductors (ITRS) 1999 Edition.

9. T.A. Unni and D.M.H. Walker, “Model-Based IDDQ PASS/ FAIL Limit Setting,” in Proc. of International Workshop on

IDDQ Testing, 1998, pp. 43–47.

10. T.W. Williams, R.H. Dennard, R. Kapur, M.R. Mercer, and W. Maly, “Iddq Test: Sensitivity Analysis of Scaling,” in Proc.

ITC, 1996, pp. 786–792.

Chih-Wen Lu received the B.S. degree in Electronic Engineering

from National Taiwan Institute of Technology, Taipei, Taiwan, R.O.C., in 1991, the M.S. degree in Electro-Optic Engineering from National Chiao Tung University, Hsinchu, Taiwan, in 1994, and the Ph.D. degree in Electronic Engineering from National Chiao Tung University, in 1999.

During 1999–2000, he was with the Department of Electrical En-gineering of Day Yeh University, Changhua Hsien, Taiwan. He joined in the Department of Electrical Engineering of Chi Nan University, Nantou Hsien, Taiwan in 2001. His research interests are in the areas of VLSI testing and analog circuit design.

Chung-Len Lee received the B.S. degree from National Taiwan

University, Taipei, Taiwan, R.O.C., in 1968, and the M.S. and the Ph.D. degrees from Carnegie Mellon University, Pittsburgh, PA, in 1971 and 1975, respectively, all in electrical engineering.

Since 1975, he has been with the Department of Electronic Engi-neering, National Chiao Tung University, Hsinchu, Taiwan, where

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he has been engaged in teaching and research in the fields of semi-conductor devices, integrated circuits, VLSI, and computer-aided design and testing. He has supervised more than 120 M.S. and Ph.D. students to complete their theses and has published more than 250 papers in the above areas. He has been involved in various tech-nical activities in the above areas in Taiwan and other parts of Asia.

Dr. Lee is on the Editorial Board of JETTA.

Chauchin Su received the B.S. and M.S. degrees in Electrical

En-gineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1979 and 1981, respectively. He received the Ph.D. degree in Electrical and Computer Engineering from University of Wisconsin at Madison, Madison, in 1990.

Since graduating, he is with the Department of Electrical Engi-neering, National Central University, Chung-Li, Taiwan, R.O.C. His research interests are in the area of mixed analog and digital system testing and design for testability. He is also involved in projects on base band circuit design for wireless communication.

Jwu-E Chen received the B.S., M.S., and Ph.D. degree all in

elec-tronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1984, 1986, and 1990, respectively. He has been an Associate Professor in the Department of Electrical Engineering, Chung Hua University, Hsinchu, Taiwan, since 1990. His research interests include multiple-valued logic, VLSI Testing, reliable com-puting, yield analysis, and psychology of testing. He is a member of IEEE and the Computer Society.

數據

Table 1. Values of technology parameters for the year 2011.

Table 1.

Values of technology parameters for the year 2011. p.4
Table 3. Values of process variations for off-chip and on-chip ICs. 3 σ W 3 σ L 3 σ T ox 3 σ V t

Table 3.

Values of process variations for off-chip and on-chip ICs. 3 σ W 3 σ L 3 σ T ox 3 σ V t p.4
Table 2. Values of width for inverter, 2-input NAND and 2-input NOR.

Table 2.

Values of width for inverter, 2-input NAND and 2-input NOR. p.4
Table 5. The maximum standard deviation, σ g , among all gates

Table 5.

The maximum standard deviation, σ g , among all gates p.4
Table 4. Expected values and standard deviation of inverter, 2-input NAND and 2-input NOR for off-chip ICs and on-chip ICs.

Table 4.

Expected values and standard deviation of inverter, 2-input NAND and 2-input NOR for off-chip ICs and on-chip ICs. p.4
Fig. 3. (a) The standard deviations of defect-free IDDQ versus the gate number for off-chip c6288 circuit
Fig. 3. (a) The standard deviations of defect-free IDDQ versus the gate number for off-chip c6288 circuit p.5
Fig. 2. The expected values of IDDQ versus the gate number for 2000 random input vectors for off-chip and on-chip c6288 circuits.
Fig. 2. The expected values of IDDQ versus the gate number for 2000 random input vectors for off-chip and on-chip c6288 circuits. p.5
Fig. 1. The simulated result on the sample histogram of the defect-free IDDQ current for the ISCAS’85 circuit c6288 under 2000 random input vectors.
Fig. 1. The simulated result on the sample histogram of the defect-free IDDQ current for the ISCAS’85 circuit c6288 under 2000 random input vectors. p.5
Table 6. The minimum defective current for different W /L ratios for the year of 2011.

Table 6.

The minimum defective current for different W /L ratios for the year of 2011. p.6
Fig. 4. The simulation result of maximum standard de- de-viation for off-chip and on-chip ICs for the technology of the year 2011
Fig. 4. The simulation result of maximum standard de- de-viation for off-chip and on-chip ICs for the technology of the year 2011 p.6
Fig. 5. (a) 6 σ of the CUT is larger than the additional defective current so that the two distributions of defect-free and defective IDDQ overlap partially
Fig. 5. (a) 6 σ of the CUT is larger than the additional defective current so that the two distributions of defect-free and defective IDDQ overlap partially p.7
Table 7. The maximum partition size (gate number) for different W /L ratios for the year of 2011.

Table 7.

The maximum partition size (gate number) for different W /L ratios for the year of 2011. p.7
Fig. 7 shows the second testing scheme which com- com-pares the IDDQ currents between two chips under the same vector
Fig. 7 shows the second testing scheme which com- com-pares the IDDQ currents between two chips under the same vector p.7
Fig. 6 shows the first testing scheme. The IDDQ cur- cur-rents of the CUT are measured by applied several  vec-tors
Fig. 6 shows the first testing scheme. The IDDQ cur- cur-rents of the CUT are measured by applied several vec-tors p.7
Table 8. The maximum partition size of the proposed two IDDQ testing schemes for W /L = 2 for the CMOS technology of year 2011.

Table 8.

The maximum partition size of the proposed two IDDQ testing schemes for W /L = 2 for the CMOS technology of year 2011. p.8

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