cise reference voltage with flexible trimming capability is achieved by using capacitors. When the supply voltage is 1 V and the tem-perature is 80 C, the supply current is 250 nA. The line sensitivity is 0.76%/V; the PSRR is 41 dB at 100 Hz and 17 dB at 10 MHz. Moreover, the occupied die area is 0.049 mm2.
Index Terms—CMOS voltage reference, nanocurrent,
switched-capacitor.
I. INTRODUCTION
H
IGH-PRECISION and stable reference voltage cir-cuits are widely used in digital and analog circir-cuits like analog-to-digital converters, voltage regulators, DRAMs, flash memories, and other communication devices. The demands for smaller area, lower power consumption, and lower sensitivity to variations in supply voltage and temperature are increasing. The base-emitter voltage of bipolar transistors or the forward voltage of a -junction diode exhibits a negative TC. In ad-dition, when two bipolar transistors operate at unequal current densities, the difference between their base-emitter voltages of bipolar transistors generate (is) directly proportional to the absolute temperature (PTAT). Thus, conventional reference voltage, which is about 1.2 V, exhibits little dependence on temperature while negative and positive temperature coeffi-cients are added with proper weighting generated by resistors. The area of resistors, the noise from resistors, and the variations of resistors with temperature can influence the performance of reference voltage circuit. Furthermore, the supply voltage is necessary to be larger than 1.2 V to provide a traditional reference voltage circuit. Recently, several voltage reference circuits operating with low power supplies were published [1]–[5]. The reversed bandgap principle can effectively scales down the reference voltage to reduce the supply voltage. This structure requires parasitic BJTs and resistors that occupy large silicon area. To overcome these problems, the methodsManuscript received June 28, 2009; revised October 05, 2009. First published January 12, 2010; current version published March 23, 2011. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 96-2221-E-009-240.
C.-Y. Hsieh and K.-H. Chen are with the Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.
H.-W. Huang is with the RichTek Technology Corporation, Hsinchu 302, Taiwan.
Digital Object Identifier 10.1109/TVLSI.2009.2038061
structures have significant temperature coefficients because trimming procedures have not been invented for these structures [7]–[9].
In general, switched-capacitor (SC)-based technique is one popular technique to eliminate the usage of large resistors and reduce the effect of offset voltage of operational amplifier. Fig. 1 shows a modified reference voltage by SC-based technique [10]. When and , the equivalent circuit of Fig. 1 is described in Fig. 1(a). At node , the charge transfer equation is shown as (1)
(1) Similarly, when and , the charge transfer equation of node in Fig. 1(b) is derived as (2)
(2) Combining (1) and (2), the voltage is written as (3)
(3) In this SC-based voltage reference circuit, the bipolar tran-sistors are used to generate both temperature coefficients at the sacrifice of large silicon area. In addition, it needs eight switches and four capacitors to implement it and the switching power loss reduces the power efficiency of this reference voltage circuit. Therefore, this paper proposed a switched-capacitor voltage ref-erence (SCVR) using pure CMOS to minimize the silicon area and temperature coefficient of the reference voltage. Further-more, this circuit only needs nanoampere supply current, and the power supply voltage can be scaled down to 1 V. In Section II, the operating principle of the proposed SCVR circuit is de-scribed. Section III presents the detailed circuit implementation, including the biasing circuit and the op-amp circuit with the auto-zeroing. Design considerations are described in Section III. Trimming flexibility is discussed in Section IV, and measured results are shown in Section V to validate the design concept and performance. Finally, a conclusion is made in Section VI.
II. OPERATINGPRINCIPLE OFPROPOSEDSCVR CIRCUIT
The structure of the SCVR circuit shown in Fig. 2 is composed of a low-power biasing circuit [8], a core circuit, switched capacitors, and an operational transconductance
Fig. 1. (a) Prior art of switched-capacitor voltage reference. The equivalent circuits can be simplified as (b) when' = 1 and ' = 0 and (c) when ' = 0 and ' = 1.
Fig. 2. Low power switched-capacitor voltage reference.
amplifier (OTA) [11] that uses the auto-zeroing technique to become insensitive to the offset voltage. The nonoverlapping clock signals ( , , ) are generated by the circuit in Fig. 3 to produce dead-time regions to avoid switching leakage for achieving high precision. The core circuit inputs and to the OTA during and , respectively. The equivalent schematics of the SCVR circuit are shown in
Fig. 4(a) and (b) when , and , ,
respectively. In the first phase ( and ), the current flowing through transistor is and the gate-source voltage corresponding to a current is stored on capacitors and . The is the current ratio of the different phases. In the second phase ( and ), the current flowing through transistor is equal to , and the gate-source voltage corresponding to current is connected to while is grounded and is put into the
negative feedback loop. From charge conservation, the OTA output express as (4)
(4) is the threshold voltage of transistor , is the elec-tron mobility, is the oxide capacitance per unit area, and and are the width and length of transistor , respec-tively. Since the reference voltage appears in the second phase, the SCVR circuit uses a sample and hold circuit to store the reference voltage. In general, the threshold voltage has neg-ative temperature coefficient. That implies that the biasing cur-rent has to be proportional to the square of the absolute tem-perature and cancel the temperature characteristic of electron mobility to compensate the temperature coefficient. Furthermore, the current is designed as a nanoampere current for reducing power consumption and the zero temperature co-efficients can be achieved by carefully adjusting the values of capacitors - . The nanoampere current with char-acteristic is discussed in detail in Section III.
III. CIRCUITDESCRIPTION
The proposed SCVR circuit is illustrated in Fig. 5. The biasing circuit formed by transistors - exploits -type transistors operating in different regions to produce the
Fig. 4. Equivalent schematic of SCVR circuit. (a) When' = 0 and ' = 1 (b) When' = 1 and ' = 0.
supply voltage. Moreover, the core circuit utilizes transistors and with different aspect ratios to generate different gate-source voltages of the -type transistor with the positive temperature coefficient characteristic. In addition, the SCVR circuit with auto-zeroing stores the offset voltage of the op-amp on capacitors - in the first phase to reduce the effect from input offset voltage.
A. Nanoampere Biasing Current Circuit With Property
Transistors - work as a startup circuit. The biasing circuit consists of four current paths to suppress the channel-length modulation effect. Because the biasing current circuit is composed by the positive close loop, the product of
transcon-ductances is designed to be smaller
than the product of transconductances .
Transistors and are 5 V -type transistors with a higher threshold voltage and operate in the subthreshold re-gion. Transistors and are 3.3 V -type transistors with a lower threshold voltage 0.55 V and operate in the satura-tion region in order to get a low quiescent current. The drain current of an -type transistor that operates in saturation and subthreshold region can be approximated by (5) and (6), re-spectively
(5)
where . According to (7), the biasing
current has characteristic. Furthermore, since the op-erating current in the subthreshold region is very small and no resistors are used in this design [8], a nanoampere of biasing cur-rent can be achieved. The curcur-rent injects into the -type tran-sistor in the core circuit. As a result, substituting (7) into (4) and the can be eliminated, the reference voltage is
(8)
Assume that the first-order negative temperature coefficient of threshold voltage is . The temperature coefficient of the thermal voltage is PTAT. Thus, the temperature dependence of the reference voltage can be obtained by differentiating both sides of (8) with respect to temperature and is given by (9)
(9)
where is the Boltzmann constant and is the electron charge. By setting (9) equal to zero, the relation of capacitor and can be found as follows:
where
(10)
In general, the negative temperature coefficient in our tech-nology is about 0.82 mV C and the positive temperature coef-ficient can be altered through the width and length of tran-sistors and other coefficients. Hence, the sizes of capacitors and can be chosen to get a zero temperature coefficient at
Fig. 5. Circuit of switched-capacitor voltage reference.
B. Proposed 1-V OTA Circuit and Auto-Zeroing
The proposed 1-V OTA circuit is composed of transistors - and - as depicted in Fig. 5. The input stage only uses an -type transistor as common source ampli-fier to save power consumption. The feedback loop ( and ) increases the output impedance and boosts the gain of OTA circuit. In order to operate with low supply voltage, tran-sistor biases the gate voltage of transistor so that it can still operate in the saturation region. Thus, transistors and are 5 V- -type transistors with larger threshold voltage 0.75 V for operating in saturation region while tran-sistor is in subthreshold region
0.7 V . That implies that the gate-source voltage of transistor is less than the threshold voltage of and the related derivation is
(11)
When . Thus, the
min-imum supply voltage of the OTA is given by
1 V. With the minimum supply voltage, transistor can still operate in the saturation region and the SCVR circuit can generate the desired reference voltage. Fig. 6 shows the Bode plot of the proposed OTA circuit from simulation when supply voltage varies from 1 to 4 V. The op-amp has largest gain of about 70 dB when varies from 2 to 4 V at room temperature and lowest gain when is 1 V owing to the suppression of the drain-source voltage of transistor . Also, the phase margin is always larger than 60 , ensuring the stability of this OTA circuit. However, because of asymmetries and process variation of this design, the influence of input offset voltage on the reference voltage [12] is greater than that from gain. As a result, the proposed SCVR circuit employs auto-zeroing shown through four timing conditions in Fig. 7(a)–(d) [10] to decrease the effect from input offset voltage. Fig. 7(a) and (d) show the equivalent schematics of SCVR circuit in phases and , respectively. Moreover, Fig. 7(b) shows
Fig. 6. Simulated Bode plot of proposed 1-V OTA asV varies from 1 to 4 V at temperature= 25 C.
that switch is turned off earlier than switch in Fig. 4 to avoid charge injection from the switch affecting the charge on the capacitors - . After switch is off, the gate-source voltage is determined by the biasing current and the offset voltage is sampled and stored on the capac-itor - . On the other hand, if the switch were turned off before , the voltages stored on the capacitors -would be affected by the charge injection of the switch . Furthermore, the switch is off ahead of to reduce the input-dependence of charge injection effects from to in Fig. 7(c). According to the four timing sequences, the offset voltage can be precisely stored on the capacitors - in the different phases. Considering the offset voltage, the charge of each capacitor is derived as (12)–(14)
(12) (13) (14) The difference charges are not affected when the offset voltage is exactly stored on the capacitors from to . Therefore, since the proposed SCVR circuit has auto-zeroing, the effect from offset voltage can be reduced to generate
Fig. 8. Cancellation diagram of the clock feedthrough and charge injection.
Fig. 9. (a) Positive TC of reference voltage. (b) Negative TC of reference voltage.
the accurate reference voltage in the second phase and thereby it is no longer critical to maintain the high dc gain of the OTA.
IV. DESIGNCONSIDERATION A. Channel Length Modulation Effect
The power supply variation of the proposed switched-capac-itor CMOS voltage reference can be derived from (8). From Fig. 5, because transistors , , , , and are diode-connected, almost all the variation of the supply voltage drops on the drain-source voltages of transistors , , , , , and . Therefore when the supply voltage varies, the biasing current varies because of channel-length modulation [10]. To reduce this problem, the biasing circuit uses transistors with large channel lengths.
However, channel length modulation of , , , , and still slightly affects the biasing current. Transistor operates in the subthreshold region. Since its drain-source voltage is larger than , the variation of the voltage
as shown in (6) can be neglected. Transistors , , , and operate in the saturation region. The channel length modulation of transistors , , and are treated in the same way owing to the current mirror structure. Including channel length modulation, (8) is modified as follows:
(15) Differentiating the (15) with respect to supply voltage gives (16), shown at the bottom of the page. The value of is close to 1.3 in this design. Then, has a small and negative value which is about 1.2
Fig. 10. (a) Implementation of trimming network forC , C , and C . (b) Implementation of switch S S , S S , and S S . (c) The imple-mentation of switchS S .
mV/V. It implies that the reference voltage decreases with the rise of supply voltage and has small variation while the input voltage varies. In addition, differentiating the (15) with respect to temperature can get
(17)
According to (17), the positive coefficient will slowly increase while the supply voltage is increasing.
B. Clock Feedthrough and Charge Injection Effects
Generally speaking, the clock feedthrough and charge in-jection effects [12], [13] influence on the accuracy of the reference voltage. To reduce this problem, the simplest method is to design the switched transistors with small width at the sacrifice of the conduction ability. Therefore, the small widths
of switched-transistors in the design are chosen to be enough for conducting nanoampere current. Unfortunately, the clock feedthrough and charge injection effects still have influence on the reference voltage about 3–5 mV after adopting this simplest method. To further reduce charge injection effects, it is important to carefully design the size of each switch. The detail of the switched parallel-plate capacitors is illustrated in Fig. 8 for explaining the minimization of the effect of the clock feedthrough and the charge injection when the clock is from high to low and the clock is from low to high. When the size of switch is designed equal to the sum of the sizes of switches and , the clock feedthrough from and can be cancelled by the clock feedthrough effects from and . In addition, the charge injection effect is also decreased. The clock feedthrough effect of the capacitance is cancelled by that of the capacitance if switches and have the same size. By choosing switches and
to have the same size, the clock feedthrough effects from capacitances and are eliminated. However, the clock feedthrough effect of the capacitance really has a small ripple for the capacitors , , and . Hence, transistor is used as a dummy switch to cancel this effect. The other charge injections , , and , also can be decreased
Fig. 12. Waveforms of the SCVR circuit.
by the switch arrangements as well. These methods alleviate the clock feedthrough and charge injection effects, and the accuracy of the reference voltage can be guaranteed.
C. Thermal and Flicker Noises
For some applications, the reference voltage circuits are needed to take account of noise performance because the values of the reference voltage are corrupted by thermal noise and flicker noise. The thermal noise and flicker noise from the OTA circuit is the most critical issue in this SCVR circuit. To dramatically reduce the thermal noise, transistor is designed to have the largest transconductance and the transistor is designed to have the smallest transcon-ductance since the thermal noise is proportional to . On the other hand, all the transistors in the OTA circuit have large width and length to effectively decrease the flicker noise since the flicker noise is inversely proportional to the product of width and length.
V. TRIMMINGFLEXIBILITY
Owing to doping gradients, process variations, non-optimum layouts, and high stress areas of die, reference voltages with nonzero temperature coefficients are not accurate enough for sensitive analog circuits. Therefore, the values of the capacitors are adjusted to minimize the temperature coefficient of the refer-ence voltage in this design. According to (9), if the temperature coefficient is not equal to zero, the temperature coefficient can be treated as a slope , which is measured by the relationship
Fig. 13. Measured supply current versus the different supply voltage when tem-perature varies from040 C to 80 C.
TABLE I
PROGRAMMABLEREFERENCEVOLTAGE BY6 BITSDIGITALCODES S
between the reference voltage and temperature. The slope can be simplified from (10) and expressed as (18)
(18) Positive and negative temperature coefficients are eliminated by carefully adjusting the values of capacitors and , re-spectively. In Fig. 9(a), if the measured temperature coefficient is positive, it means the value of positive coefficient is larger than that of negative temperature coefficient. The value of ca-pacitor is decreased by the trimming procedure, and the de-creased value can be expressed as in (19). Similarly, de-creasing the value of capacitor written as in (20) can reduce the negative temperature coefficient
(19) (20) The trimming network for or uses three digital control bits to generate seven voltage levels for the trimming procedure
Fig. 14. Measurement results. (a) Output voltage versus temperature for dif-ferent supply voltages. (b) PSRR at (V = 1 V, C = 0 C and 25 C).
as shown in Fig. 10. The resolution is about 2.5% and enough to accurately adjust the performance within 16.9 ppm C. Thus, the temperature coefficient can be reduced to near zero by trim-ming the values of capacitors and [14]. Similarly, a scal-able voltage reference with 2% resolution can be achieved by adjusting the value of capacitor according to (8). Six digital control bits are used according to the requirement of increasing or decreasing the value of the reference voltage. The trimming implementation circuit also is shown in Fig. 10(a). The imple-mentations of trimming switches are shown in Fig. 10(b) and (c). The advantages of the proposed SCVR circuit are that it uses capacitors with low temperature coefficient and the values of capacitors - can be flexibly adjusted to achieve near zero temperature coefficient and scalable reference voltage value.
VI. EXPERIMENTRESULTS
The proposed SCVR circuit was implemented in TSMC double-poly quadruple-metal 0.35- m CMOS technology. The values of capacitors , , and are set to about 1.5, 0.3,
Fig. 15. Mean reference voltage from 40 tested samples.
and 1 pF, respectively. The threshold voltages of -type and -type transistors are 0.55 and 0.65 V, respectively. The chip micrograph is shown in Fig. 11, and the active silicon area is 0.049 mm .
The measured waveforms are shown in Fig. 12 when clock frequency is equal to 1 kHz, the value of the output filter ca-pacitor is about 20 pF, and the supply voltage is 1 V. The proposed voltage reference can not only operate at low supply voltage, but also has low power consumption and occupies a small area. At room temperature, the supply current is 250 nA at minimum supply voltage 1 V and the supply current of bias circuit, core circuit, and OTA circuit are 90, 25, and 135 nA, respectively. When the supply voltage is at 4 V, the supply current is about 430 nA. The measured output voltage versus temperature for supply voltages over the range of 1 V to 4 V is shown in Fig. 13. Moreover, the measured temperature coeffi-cient with 1 V is 16.9 ppm C. Fig. 14(a) shows a plot of the measured reference voltage versus temperature over the range 40 C to 80 C and the supply voltage varies from 1 to 4 V. The line regulation of reference voltage agrees with (13). The measured power-supply rejection ratio (PSRR) at minimum supply voltage (1 V) without any filtering capacitor is shown in Fig. 14(b). The PSRR is 41 dB at 100 Hz and 17 dB at 10
sensitivity to variations in supply voltage and temperature, but also it can overcome process variations through the use of trim-ming.
VII. CONCLUSION
A switched-capacitor based CMOS voltage reference with nanoampere biasing current is proposed in this paper. The mea-sured results show the temperature coefficient is 16.9 ppm C. An effective suppression of the temperature dependence of the carrier mobility and the channel-length modulation effect is achieved. Furthermore, the flexibility of trimming capacitors is an advantage of our proposed voltage reference for a precise CMOS reference voltage.
ACKNOWLEDGMENT
The authors would like to thank the Industrial Technology Research Institute, the reviewers comments, and Chunghwa Pic-ture Tubes, Ltd. for their help.
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reference with trimming,” in Proc. ISCAS, May 2006, pp. 21–24. Chun-Yu Hsieh was born in Taichung, Taiwan. He received the B.S. degree in electrical and control engineering from Nation Chiao Tung University, Hsinchu, Taiwan, in 2004, where he is currently pursuing the Ph.D. degree in electrical and control engineering.
His research interests include many projects of LED driver ICs and power management ICs.
Hong-Wei Huang received the B.S. degree in elec-tronic engineering from Fu Jen Catholic University, Taipei Taiwan, in 2003 the M.S. degree from National Taiwan University (NTU), Taipei, Taiwan, in 2005, and the Ph.D. degree from Graduate Institute of Elec-tronics Engineering, National Taiwan University, in 2008.
He is with Richtek Technology Corporation, Hsinchu, Taiwan. He was also an important member of Mixed Signal and Power IC Laboratory, Depart-ment of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan. His research interests include power management IC designs and analog integrated circuits of LCD driver controller. He has published over 15 papers in journals and conferences, and also holds several patents.
Ke-Horng Chen (M’04–SM’09) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
From 1996 to 1998, he was a part-time IC De-signer with Philips, Taipei, Taiwan. From 1998 to 2000, he was an Application Engineer with Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager with ACARD, Ltd., where he was engaged in designing power management ICs. He is currently an Associate Professor with the Department of Elec-trical Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of over 80 papers published in journals and conferences, and also holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display (LCD) TV, red, green, and blue (RGB) color sequential backlight designs for optically compensated bend (OCB) panels, and low-voltage circuit designs.
