探討化學氣相沉積在先進動態隨機存取記憶體淺溝槽絕緣的
填洞能力
Study of Shallow Trench Isolation Gap Filling Capability
for Advanced DRAM by Chemical Vapor Deposition
研 究 生：吳兆騰
指導教授：潘 扶 民 博士
中
華
民
國
九
十
五
年
八
月
國 立 交 通 大 學
工學院半導體材料與製程設備研究所
碩 士 論 文
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Study of Shallow Trench Isolation Gap Filling Capability for Advanced DRAM by Chemical Vapor Deposition
探討化學氣相沉積在先進動態隨機存取記憶體淺溝槽絕緣的填洞能力
研 究 生 :吳兆騰 Student: Siu Tang Ng
指導教授 :潘 扶 民 博士 Advisor: Dr Fu-Ming Pan
國 立 交 通 大 學
工學院半導體材料與製程設備研究所 碩 士 論 文
A Thesis
Master Degree Program of Semiconductor Material and Processing Equipment
College of Engineering National Chiao Tung University in Partial fulfillment of the Requirement
for the Degree of Master of Science in
Program of Semiconductor Material and Processing Equipment
Aug, 2006
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國 立 交 通 大 學 工學院半導體材料與製程設備研究所 探討化學氣相沉積在先進動態隨機存取記憶體淺溝槽絕緣的填洞能力 研 究 生 :吳兆騰 指導教授 :潘 扶 民 博士
摘要
在於本碩士論文裡, 我們旨在利用 HARP-SACVD 以化學氣相沉積方 式來探討如何以沒有摻質的玻璃來延伸先進動態隨機存取記憶體淺溝絕緣 的填動能力。根據這次實驗結果，三步驟的沉積方式可以滿足，並沒有發現 縫道在 60 奈米的槽寬度以及 AR 7:1 槽溝之填洞結果。第一步沉積是利用 較高的 Ozone /TEOS 比例來得到極佳的階梯覆蓋，減少表面的選擇性，第 二步沉積旨在不改變 Ozone/TEOS 之比例下，利用較少 TEOS 的流量來完 成淺溝槽之填洞。而最後的沉積目的是增加晶片之生產量。 在本實驗中亦探討 TEOS 的初期流量以及完成 HARP 之玻璃沉積後 回火處裡方式對淺溝槽填洞能力之影響。- iii -
Study of Shallow Trench Isolation Gap Filling Capability for Advanced DRAM by Chemical Vapor Deposition
Student: Siu Tang Ng Advisor: Dr Fu-Ming Pan
Program of Semiconductor Material and Processing Equipment
College of Engineering
National Chiao Tung University
ABSTRACT
In this thesis, we explored the extendibility of shallow trench isolation (STI) gap filling capability of undoped silicate glass (USG) prepared by high aspect ratio process (HARP) in sub-atmosphere chemical vapor deposition (SACVD) systems for sub-70 nm technology nodes for the advanced dynamic random access memory (DRAM) applications. Based on the study, a 3-step deposition process, which is capable of achieving void free gap filling at 0.06μm trench width and > 7:1 aspect ratio with a smooth profile of trench sidewall, was developed. The first step is to deposit a homogeneous nucleation layer with trivial surface selectivity by using a gas source with a high O3/
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achieved. The second step is to deposit a sufficiently thick USG to fill trenches with a small to moderate width by using a gas feed of a relatively high O3/TEOS ratio. The final step is targeted at throughput
enhancement. The effect of initial TEOS composition and annealing treatment after the HARP USG deposition on the trench filling capability was also studied.
Key Words: O3/TEOS, DRAM, shallow trench isolation, HARP,
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誌謝
首先，本人要致上最高的敬意和誠摯的謝意 ，給我的指導教授潘扶 民博士，感謝他嚴謹的治學態度， 給我的耐心指導與教誨，提攜與照顧， 使本人在學術研究上獲益良多，得以順利完成碩士學位。 我也要感謝美商台灣應用材料(Applied Materials)提供本實驗使用 的 HARP SACVD 反應室設備、量測儀器設備與製程上的相關知識的協助， 使個人得以順利的進行相關實驗以及結果資料的取得。此外,我也要感謝 多位台灣應用應材料的同僚的協助：設備工程師-戴翠嵩先生、李秉豪先 生提供 HARP SACVD 應體上的保養與調整。製程工程師-鍾平江先生、蔡 友林先生在實驗過程中提供寶貴的製程經驗分享。另外，也要感謝職務上 的主管-王森煥先生對於個人在學業上與製程實驗上的鼎力支持。 最後，感謝我的太太的支持與鼓勵，關心與包容，使我可以心無旁務 的專注於學業上，在此獻上內心最深的謝意。- 2 -
Table of Contents
Abstract in Chinese．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． ii Abstract in English．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．iii Appreciating．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 1 Contents．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．2 List of figures．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 5 List of tables．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．10 Chapter 1 Introduction 1.1 General background．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．11 1.2 Motivation．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．12 1.3 Organization of this thesis ．．．．．．．．．．．．．．．．．．．．．．．．．．13Chapter 2 Chemical vapor deposition
2.1 Overview of thin film deposition．．．．．．．．．．．．．．．．．．．．．．．．．15 2.2 CVD of dielectrics．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．19
2.3 Thin film phenomena．．．．．．．．．．．．．．．．．．．．．．．．．．．20 2.3.1 Physical properties of thin film．．．．．．．．．．．．．．．．．．．．21
2.3.2 Mechanical properties of thin film．．．．．．．．．．．．．．．．22 2.3.3 Electrical properties of thin film．．．．．．．．．．．．．．．．．．．24 2.3.4 Special properties requirement for microelectronics．．．．．26 2.3.5 Chemical reaction kinetics．．．．．．．．．．．．．．．．．．．．．29
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2.3.6 Plasma fundamental．．．．．．．．．．．．．．．．．．．．．．．．．．33
2.4 Chemical vapor deposition systems
2.4.1 Atmospheric pressure CVD systems．．．．．．．．．．．．．．．．41 2.4.2 Sub-atmospheric CVD SACVD．．．．．．．．．．．．．．．．．．43 2.4.3 Plasma enhanced chemical vapor deposition PECVD．．．．．．．．52 2.4.4 High density plasma HDP CVD．．．．．．．．．．．．．．．．．．．59 2.5 Shallow trench isolation gap fill challenge．．．．．．．．．．．．．．67 2.5.1 Introduction．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．67 2.5.2 Challenge of shallow trench isolation by HDPCVD．．．．．．．．．67
Chapter 3 Experimental procedure
3.1 Introduction．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．70 3.2 Evolution of HARP SACVD．．．．．．．．．．．．．．．．．．．．．．．．．71 3.2.1 HARP chamber configurations．．．．．．．．．．．．．．．．．．．71 3.2.2 Liquid delivery systems．．．．．．．．．．．．．．．．．．．．．．．．74 3.2.3 Pumping systems．．．．．．．．．．．．．．．．．．．．．．．．．．．76 3.2.4 NDIR end point detector．．．．．．．．．．．．．．．．．．．．．．．78 3.3 Methodology．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．80 3.3.1 Experimental preparation．．．．．．．．．．．．．．．．．．．．．．80 3.3.2 Experimental details．．．．．．．．．．．．．．．．．．．．．．．．．．．．81 3.3.3 Recipe optimization．．．．．．．．．．．．．．．．．．．．．．．．．．．82 3.3.4 HARP USG reflow by furnace．．．．．．．．．．．．．．．．．．．86
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Chapter 4 Results and discussion
4.1 Advancement in gap filling．．．．．．．．．．．．．．．．．．．．．．．．．．87 4.2 SHARP film properties．．．．．．．．．．．．．．．．．．．．．．．．．87 4.2.1 Film properties trend．．．．．．．．．．．．．．．．．．．．．．．．88 4.2.2 Film monitoring in three steps recipe．．．．．．．．．．．．．．95 4.2.3 Film repeatability study for bi-layer．．．．．．．．．．．．．．．．．．96 4.2.4 Whole film stability and repeatability test．．．．．．．．．．．．99 4.2.5 Wet etch rate monitoring．．．．．．．．．．．．．．．．．．．．．．．．100 4.3 STI gap fill．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．101 4.3.1 Trench gap filling study by partial deposition．．．．．．．．．．．．101 4.3.2 STI gap filling check with three steps recipe．．．．．．．．．．．．．．103 4.4 STI gap fill window check．．．．．．．．．．．．．．．．．．．．．．．．．．104 4.4.1 O3/TEOS ratio adjustment．．．．．．．．．．．．．．．．．．．．．．．104
4.4.2 Anneal condition．．．．．．．．．．．．．．．．．．．．．．．．．．．．106
Chapter 5 Conclusion．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．109
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Figure captions
Chapter 1
Figure 1.1 Void observed in STI gap fill of 70nm node DRAM technology.
Chapter 2
Figure 2.1 Schematic of events that occur around the substrate surface. Figure 2.2 Complementary MOS (CMOS) inverter.
Figure 2.3 DRAM structures.
Figure 2.4 Showed thermally grown oxide and CVD dielectric film. Figure 2.5 (a)Tensile stress cause concave bending, and (b)Compressive stress causes convex bending of substrate.
Figure 2.6 A parallel-plate capacitor.
Figure 2.7 Step coverage and the related terms. Figure 2.8 Arrival angle and surface mobility.
Figure 2.9 Reflow achieves planarity in doped oxide films. Figure 2.10 The activation energy of the reaction.
Figure 2.11 The deposition rate ( Rg ) is a rapid varying function of temperature.
Figure 2.12 Boltzmann distribution.
Figure 2.13 The sheath potential accelerates ions towards the electrode. Figure 2.14 DC potential difference between the bulk plasma and
electrodes.
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Figure 2.16 Schematic diagram of the SACVD.
Figure 2.17 Vertical (left) and tapered (right) structure types showing gap fill with BPSG with RTP of 850oC for 30seconds.
Figure 2.18 Schematic diagram of PECVD. Figure 2.19 SILANE bonding .
Figure 2.20 Silane mechanism of plsama CVD.
Figure 2.21 Physisorption on the oxide surface through hydrogen bonding.
Figure 2.22 Step coverage and conformality of TEOS and SILANE USG for metal line.
Figure 2.23 Step coverage and conformality of TEOS and SILANE USG in trench .
Figure 2.24 Schematic diagram of HDPCVD.
Figure 2.25 Schematic of deposition, etch and deposition process for gap fill.
Figure 2.26 Concept of HDP CVD is the combination of deposition and sputter.
Figure 2.27 The relation between the incident angle and the transferred energy distribution in bombarded material.
Figure 2.28 A relationship between the angle of incident and sputter yield.
Figure 2.29 Relationship of sputtering rate against void capability. Figure 2.30 A illustration of gap fill evolution is HDP CVD.
Figure 2.31 DPCVD past gap fill approach. Figure 2.32 New geometrical gap fill model.
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Chapter 3
Figure 3.1 65nm node STI trench structure.
Figure 3.2 Chamber design of HARP SACVD.
Figure 3.3 Face plate comparison between standard SACVD and HARP SACVD.
Figure 3.4 Individual liquid line modules. Figure 3.5 TEOS vaporization.
Figure 3.6 Pumping line systems.
Figure 3.7 Basic concepts of NDIR endpoint detector. Figure 3.8 NDIR endpoint graphic monitoring.
Figure 3.9 Contour map of HARP film.
Figure 3.10 TEOS flow rate Vs time during 3-steps USG for gap filling.
Chapter 4
Figure 4.1 Deposition rate against heater temperature.
Figure 4.2 Deposition rate against pressure.
Figure 4.3 Deposition rate against ozone concentration. Figure 4.4 Wet etch rate against pressure.
Figure 4.5 Wet etch rate against heater temperature. Figure 4.6 Wet etch rate against ozone concentration. Figure 4.7 Shrinkage rate against heater temperature. Figure 4.8 Shrinkage rate against TEOS flow.
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Figure 4.10 Shrinkage rate against process pressure. Figure 4.11 Initial layer thickness chart.
Figure 4.12 Initial layer uniformity chart.
Figure 4.13 Second-step deposition thickness chart . Figure 4.14 Second-step deposition uniformity chart.
Figure 4.15 Bulk layer thickness chart. Figure 4.16 Bulk layer uniformity chart. Figure 4.17 Whole film thickness chart. Figure 4.18 Whole film uniformity chart. Figure 4.19 Whole film reflected index chart. Figure 4.20 Wet etch rate vary TEOS trend chart.
Figure 4.21 SEM shown Dep-1 for STI dense area without annealing. Figure 4.22 SEM shown Dep-1 for STI trench area without annealing. Figure 4.23 SEM shown Dep1+2 for STI dense area without annealing.
Figure 4.24 SEM shown Dep1+2 for trench area without annealing. Figure 4.25 SEM shown STI trench void free in dense area after steam annealing.
Figure 4.26 SEM shown STI open area after steam annealing. Figure 4.27 SEM shown STI void free in trench area after steam annealing.
Figure 4.28 SEM shown void free with initial low TEOS flow after furnace steam annealing (DOE_1-3,5).
Figure 4.29 SEM shown void initial low TEOS flow in DOE_4 after furnace steam annealing.
Figure 4.30 SEM shown voids free in dense area of STI after steam furnace annealing.
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Figure 4.31 SEM shown voids free in trench after steam furnace annealing.
Figure 4.32 SEM shown reflow angle after HARP USG deposition after steam furnace annealing.
Figure 4.33 SEM shown void observation in dense area of STI after dry furnace annealing.
Figure 4.34 SEM shown void observation in trench by using dry furnace annealing only.
Figure 4.35 SEM shown bigger reflow angle after HARP USG deposition by using dry annealing only.
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Table captions
Chapter 2
Table 2.1 properties of a typical glow discharge Table 2.2 possible collision in silane plasma
Chapter 3
Table 3.1 experimental design table Table 3.2 optimizes three steps recipe Table 3.3 split conditions for STI gap fill
Table 3.4 post HARP annealing conditions split
Chapter 4
Table 4.1 results of experiments
Table 4.2 film properties monitoring in each deposition Table 4.3 DOE film properties monitoring
Table 4.4 initial layer repeatability test
Table 4.5 second-step deposition repeatability test Table 4.6 bulk layer repeatability and stability test Table 4.7 wet etch rate vary TEOS flow
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Chapter 1
Introduction
1.1 General Background
Shallow trench isolation (STI) has rapidly become a vital electrical isolation scheme as CMOS technologies are scaled down below 0.25µm generation. This technique has the advantages of having no bird’s beak and no encroachment. When two devices are separated by a trench, the electrical field lines have to travel a longer distance and change direction twice, so there are considerably weakened. Therefore, STI provides abrupt transition from active device to isolation regions and is adequate for preventing punch-through and latch-up phenomena [1]. In addition, this technology can concurrently achieve good planarity. One of the process steps involved in STI technique is trench-fill dielectrics for STI, which is where un-doped silicate glass (USG) is deposited.
Many challenges are encountered in the design of the STI process for electrical isolation. The greatest challenge lies on providing void-free, seamless gap filling by oxide deposition. Voids and seams formed during deposition can be enlarge during subsequent CMP and HF etching processes and filled with poly-silicon. This will cause gate-to-gate short failure, junction leakage and degrade overall parametric results and affect chip yields. Moreover, as device dimensions continue to shrink, the distance between
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transistors active areas and STI side-wall also narrow, they become highly critical to obtain good gap filling to avoid deleterious device behavior.
In this study, we conducted screening tests based on different theories and empirical process approaches. A thermal process of HARP SACVD, based on O3/TEOS chemical vapor deposition, to improve USG process significantly on
two important fronts, improves gap filling capability of shallow trench isolation, and ensures no plasma damage to devices.
1.2 Motivation
Rapid progress in transistor scaling has made gap fill technology critical for all advanced devices, as the dimensions of ULSI circuits continue to shrink below nanometer technology. The requirements for shallow trench isolation (STI) include voids free gap filling, better conformal step coverage, low wet etch rate and metallic contamination. It is found that HDP is increasingly finding it difficult to provide a good gap-fill solution for the more aggressive STI structures at technology nodes of < 0.07µm. A viable alternative HARP SACVD based on O3/TEOS ratio is on developing to achieve all requirements
for the advanced dynamic random access memory (DRAM). A understanding of alternative techniques such as the methodology of furnace annealling for HARP USG is required for trench gapfill. Finally, A comprehensive understanding of the next generation of STI films and structure types is required to provide void free gap-fill
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1.3 Organization of This Thesis
There will be five chapters in this thesis compositions.
Chapter 1 introduce to the general background of shallow trench isolation and what challenge will be suffering if future .
SiN SiN
Void
HDP-USG
Pad Nitride
Figure 1.1 Voids observation in STI gap fill of 70nm node of DRAM technology.
Aspect Ratio =7:1
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Chapter 2 presents dielectric chemical vapor deposition basic theory and the process concepts of dielectric CVD likes SACVD, PECVD and HDPCVD.
Chapter 3 demonstrates the film properties of HARP USG films in SACVD as a function of deposition rate, wet etch rate and shrinkage rate in variation of depsotion temperature, ozone concentration and process pressure. The effect of the trench filling with annealing and without annealing is also be explored.
Chapter 4 reveals the results of film properties and reliability in HARP SACVD and the shallow trench isolation gap fill capability through the experiement.
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Chapter 2
Chemical vapor deposition
2.1 Overview of thin film deposition
Chemical vapor deposition (CVD) is a technique for synthesizing materials in which chemical components in vapor phase react to form a solid film at surfaces. The occurrence of a chemical reaction is essential to these means of film growth, as it is the requirement that reactants must start out in vapor phase. Ability to control the components of the gas phase, and the physical conditions of the gas phase, the solid surface, and the envelope surrounding them determines our capability to control the properties of thin films that to be produced.
CVD is a sequential process which starts from initial vapor phase, progress through a series of quasi steady states sub-process, and culminates in the formation of solid film in its final microstructure. This sequence is illustrated schematically in figure 2.1 [2] [3].
a. Diffusion of gaseous reactants to the surface.
b. Adsorption of the reacting species on to surface sites, often after some migration on the surface.
c. Surface chemical reaction between the reactants, usually catalyzed by the surface.
d. Desorption of the by-products away from the surface. e. Diffusion of the by-products away from the surface.
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f. Incorporation of the condensed solid product into the microstructure of the growth film.
Figure 2.1 Schematic of events that occur around the substrate surface. Summation of these events leads to deposition on the wafer.
In microelectronic applications, semiconductor films are patterned to form electronic devices. Conductive films act as a conduit through which electrical signals are transited to and away from these devices. Dielectric films are used to isolate devices to each other and to insulate the conductive wires. The application is enough to deduce many of the properties requirement by dielectric films used in microelectronics [4]. For instance, a dielectric film should have a very low electrical conductance, high breakdown strength, and
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should be physically void-free. Conversely, a conductive film should exhibit high electrical conductance and should has good long-term reliability under conditions of high current density [5]. Since many electrical devices are formed in mono-crystalline semi-conductive films, crystallographic perfection is essential, these are the generic requirements for the three kinds of films in microelectronic.
During the past several years, CVD has become an essential part of very large scale integrated circuit (VLSI) manufacturing. More and more film layers are attempted using CVD due to its often superior conformality. Newer CVD techniques are being developed for the deposition of more layers. It is importance to understand the fundamentals of chemical vapor deposition are therefore crucial to the development of an integrated process for manufacturing large-scale ICs.
In the early 1980s, low power consumption complementary MOS (COMS) circuits started to be dominant in IC design. Today, most ICs are CMOS based. Even though electrical conductivity is the main feature that separates conductors from dielectrics, the roles played by dielectrics in microelectronics are more varied when compared to the applications of conductors. Silicon based integrated circuit technology owes its popularity in no small measurement to the existence of a stable native dielectric silicon dioxide. SiO2
is used as the gate oxide in most devices, where it dictates their performance. Dielectrics are used to isolate electrically active components, either semiconductors or conductors, and they are used as capacitors, they provide protection for the device from ambient impurities and moisture.
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Figure 2.2 Complementary MOS (CMOS) Inverter.
(a) (b)
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2.2 CVD of dielectrics
There are two kinds of dielectrics in an IC chip, thermally grown
dielectrics and chemical vapor deposition dielectrics. Gate oxide is a process of thermally grown oxide layers [6] [7].
Figure 2.4 Show thermally grown oxide and CVD dielectric film.
Thermal oxidation offers the best quality for Si-SiO2 interface and thus it
has a low interface trap density. Therefore, it is almost used to form the gate oxide and field oxide. The following chemical reactions describe the thermal oxidation of silicon in oxygen or water vapor.
Si(solid) + O2 (gas) SiO2(solid)
Si(Solid) + 2H2O(gas) SiO2(solid) + 2H2(gas)
SiO2
SiO2
Silicon
Silicon
Silicon
Silicon Substrate
CVD dielectric film
Thermally grown oxide
SiO2
SiO2
Silicon
Silicon
Silicon
Silicon Substrate
CVD dielectric film
Thermally grown oxide
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CVD dielectrics are mainly used for making interconnections and shallow trench isolation [8]. With device dimensions shrinking and the number of transistors increasing, one layer of metal is no longer enough to connect all transistors, thus, two or more metal layers are employed for making the interconnections.
For IC chips with two metal layers, three metal CVD dielectric layers are needed: pre-metal deposition (PMD), the dielectrics between the two metal layers, or inter-metal dielectrics (IMD), and passivation film deposition.
As device dimensions continue shrinking to sub-micron, more metal layers are needed for making the interconnections. The CMOS IC devices below, with seven layers of metal, needed eight CVD dielectric layers, one pre-metal deposition, six inter-metal depositions and one final passivation film. But for dynamic random access memory (DRAM), there is only three metal layers are employed for making interconnections in even technology goes to 70nm node generation and beyond.
2.3 Thin film phenomena
Having introduced the phenomena that occur during the growth of thin films, let us explore the properties of thin films, from a structural view-point, we will examine the way of physical, mechanical, and electrical properties, that which are affected by the film structure and microstructure. We will also examine deviations in material properties on going from bulk to thin film.
- 21 - 2.3.1 Physical properties of thin films.
Density or specific gravity of thin films can be determined through weight gain measurements using microbalances. We often observe an increasing in density in thin films with increasing thickness, with the bulk density as the upper limit. This phenomenon has been attributed to the smaller grain size and the increased grain boundary area, which is normally less dense than the grain itself [9]. More often, thinner films tend to contain microscopic voids that decrease as a percentage of the film volume as the film grows thicker. The tendencies that lead to crystallographic perfection generally lead to an increase in film density. Density of the film often correlates to resistivity and other film properties affected by the presence of voids.
Surface roughness arisen from the random nature of nucleation and coalescence [10]. Deviation from the average thickness Δt for films grown at relatively low temperature and at limited surface mobility can be modeled according to a poisson distribution.
Δt ∝ √t
In characterizing roughness, both Δt and the periodicity of the peaks and valleys need to be accounted for. Various optical scattering and surface profile-metric techniques have been developed to characterize roughness. Another contributor to surface roughness is the presence of surface grooves. Since higher temperatures often results in large grooves, a direct relationship can be observed between roughness and temperature of growth. In this
- 22 -
situation, measurement of surface roughness yields a direct measuring of the film grain size distribution. Surface roughness acts as an excellent indicator of surface contamination. Often deviation in the film roughness can be directly attributed to leak in the deposition systems and the presence of gaseous impurities such as oxygen [11].
2.3.2 Mechanical properties of thin films
2.3.2.1 Adhesion
The adhesion of grown and deposited films used in ULSI processing must be excellent. If the films lift from the substrate device failure can be result, and thus poor adhesion will represent a potential reliability problem.
Adhesion is also strongly affected by the cleanliness of the substrate. Contamination generally results in poor adhesion, as does an adsorbed gas layer. Cleaning the substrate prior to deposition is therefore important to insure film adhesion capability. Substrate surface roughness can also affect adhesion
[12], for example, increased roughness may promote adhesion because the
substrate exhibits more to surface area than to flat surface, and mechanical interlocking between the film and the substrate may also occur. Excessive roughness, on the other hand, results in coating defects, which may promote adhesion failure.
It is highly advantageous to include a layer of a strong oxide-forming element between the oxide substrate and the metallization. This is particularly
- 23 -
true for gold-based metallization, where a chromium layer can be used to serve as an intermediate “adhesion layer” [13] [14]. The intrinsic stress in thin film is generally not sufficient to result in de-lamination, unless the film is extremely thick. More often, high stress results in the cracking of films.
2.3.2.2 Stress in thin film.
Nearly all films are found to be in a state of internal stress, regardless of the means by which they have been produced. The stress may be compressive or tensile: Compressive stressed films would like to expand parallel to the substrate surface, and in the extreme, film in compressive stress will buckle up on the substrate. Films in tensile stress on the other hand, would like to contract parallel to the substrate, and may crack if their elastic limits are exceeded. In general, the stress in thin film is in the range of 108 to 5X1010 dynes/cm2.
The total stress Q, in a film is the sum: a) any external stress Qext, on the
film, perhaps from another film; b) the thermal stress Qth: and c) the intrinsic
stress Qint. The total stress is written as:
Q = Qext + Qth + Qint
The thermal stress is easily to model, it arises from the difference in thermal expansion between the film and the substrate. During cooling from growth temperature, the film assumed to be tensile stress state if the film wants
- 24 -
to contract more than the substrate will allow. Conversely, the film assumes a compressive stress state if the substrate contracts more than the film wants to. Intrinsic stress reflects the film structure in ways not yet completely understood [15]. It has been observed that the intrinsic stress in a film depends on thickness, deposition rate, deposition temperature, ambient pressure, method of film preparation, and type of substrate used, among other parameters.
Measurement of stress in the thin film can often be accomplished by measuring the curvature of the substrate, either as a disk or as a strip. Interference rings, laser holography, traveling microscopes, and optical curvature measurement techniques have been used to measure curvature of disks and deflection of the strip.
Figure 2.5 (a) Tensile stress causes concave bending, and
(b) Compressive stress causes convex bending of substrate.
2.3.3 Electrical properties of thin films.
The electrical conductivity of a material is due to the motion of charge carriers through the lattice under the influence of applied electric fields [16]. Here I will introduce the properties of dielectric film.
- 25 -
As a class of materials, dielectrics exhibit large energy gaps in their band structure, with few free electrons to participate in electrical conduction. Band gaps in dielectrics can be on the order of a few electron volts. The important characteristics of the dielectric constant that affect its usefulness in microelectronic application are the dielectric constant, the breakdown strength, and the dielectric loss. Dielectric constant or permittivity is a measure of the amount of electrical charge a material can withstand at a given electrical field strength, not to be confused with dielectric strength. For a nonmagnetic, non-absorbing material, the dielectric constant is the square of the index of refraction. A vacuum, the perfect dielectric, has a dielectric constant of unity.
The capacitance C in farads of a parallel-plate capacitor shown in figure 2.6 with surface area A and a dielectric of thickness t in centimeters is given by
C = εoεΑ/4 t = 8.85 x 10-14εΑ/t
A high dielectric constant is required to obtain high values of capacitance for a storage capacitor in a DRAM. Interconnect applications require low capacitance between adjacent metal lines. Even though smaller thickness can result in a high value of the capacitance, dielectric strength or breakdown strength is a measurement of the resistance of the dielectric to electrical breakdown under the influence of strong fields [17]. The structural integrity of insulator, the presence of pinholes and metallic contaminants reduce the dielectric strength.
- 26 -
Dielectric loss is a measure of frictional loss, dissipated as heat, in the presence of a varying electric field. The loss occurs because electric polarization in a dielectric is unable to follow the electric field.
Figure 2.6 A parallel-plate capacitor.
2.3.4 Special properties requirements for microelectronics
Even though there are some introduction of general properties of thin films, such as mechanical characteristics and electron transport, there are certain unique requirements for thin films in microelectronics. These requirements are extensions of the properties discussed in the proceeding sections:
- 27 -
Conformability of a thin film refers to its capability to exactly reproduce surface topography of the under substrate. Conditions during growth and subsequent annealing, along with intrinsic properties of the materials determine conformality [18]. In some cases, geometrical constraints of the substrate topography preclude conformality. These concepts are illustrated in figure 2.7. The need for conformality arises because microelectronic processing proceeds by successively depositing and patterning features on thin films. If successive films do not follow the patterns created on the previous layers, voids in deposited layers begin to form. Etching these layers may result in stringers. These can lead to electrical shorts and opens, or to the failure caused by trapped material in the voids.
Figure 2.7 Step coverage and the related terms.
Arrival Angle and surface mobility can contribute significantly to conformality. However, even though surface mobility is a necessary condition for good step coverage, it is far from being sufficient. Conformality over a right-angled step is termed step coverage, the largest arriving angle it does at
- 28 -
the overhang of the step corner [19]. For the same step height, the narrower the gap, the smaller the arriving angle, and the harder it is to fill.
At lower pressure, the mean free path of the particle is longer, so it can affectively reduce the arriving angle at the step corner and improve sidewall step coverage.
Figure 2.8 Arrival angle and surface mobility.
2.3.4.2 Planarity
A related film properties to conformality is palnarity. Lithographic imagers are used in microelectronic manufacturing to pattern very small features on the substrate, these image tools have limited depths of focus and hence require that each successive layer is sufficiently planar [20]. Planarity, can be achieved by many means, some of which are unrelated to CVD. However, one of the techniques used in planarization is the thermal flowing of doped oxide glasses deposited by CVD under elevated temperature. Figure 2.9 shown a cross-sectional electron micrograph of a thermally deposited
- 29 -
phosphosilicate glass deposited by CVD before and after reflow at a temperature of 800℃. Notice the improvement in the planarity.
Figure 2.9 Reflow achieves planarity in doped oxide films.
2.3.5 Chemical reaction kinetics
Chemical kinetics is the study of the rate and the mechanism by which one chemical species is converted to another. The rate of a reaction is the mass in moles of a product species produced or reactant species consumed in unit time. It can be expressed as
R = Moles with component formed / Mass of solid x time
By the term mechanism it can be account for all the individual collision processes involving the reactant and product atoms that result in the overall rate.
- 30 - 2.3.5.1 Temperature dependence of rate
The rate constant k relates to overall rate of the reaction to the concentration dependent terms. It has been found to be a strong function of temperature and is well represented empirically by the Arrhenius Law [21].
k=A exp (-Ea / kT)
A is the collision frequency term and Ea is the activation energy. The terms collision frequency and activation energy arise out of the concept of an activated complex.
Figure 2.10 Activation energy of the: the change in energy of a reacting species as the reaction proceeds forward the energy needed for the reactants.
AB* is called the activated complex and is in equilibrium with A and B. The energetic of the reaction are shown in figure 2.10. The activated complex is formed by the collision of A and B molecules and is incapable energetically of existing itself. C is formed out of the decomposition of AB*. The rate of
A, B
AB*
C
Reaction coordinate EnergyA, B
AB*
C
Reaction coordinate Energy- 31 -
formation of C is only dependent on thee concentration of AB* and its rate of decomposition.
2.3.5.2 Surface reaction and mass transfer controlled growths
Because the deposition process includes force convection, boundary-layer diffusion, surface absorption, decomposition, surface diffusion, and incorporation, there are several variables to be controlled. Temperature, pressure, flow rate, position, and reaction ratio all are important factors for high-quality films. The industry has optimized these conditions to improve the film properties.
Since the aforementioned steps for a CVD process are sequential, the one that occurs at the slowest rate will determine the deposition rate. The rate-determining steps can be grouped into gas-phase processes and surface processes [22]. For the gas-phase process, the concern is the rate at which gases impinge on the substrate. This model considers the rate at which gases cross the boundary layer that separates the bulk regions of flowing gas and substrate surface. Such transport processes occur by gas-phase diffusion, which is proportional to the diffusivity of the gas and the concentration gradient across the boundary layer. The rate of mass transport is only relatively weakly influenced by the deposition temperature.
On the other hand, at low temperature the surface reaction rate is reduced, and eventually the arrival rate of reactants exceeds the rate at which they are consumed by the surface reaction process. Under such conditions, the deposition rate is surface reaction rate limited. Thus, at high temperature, the deposition is usually mass transport limited, while at low temperature it is
- 32 -
surface reaction rate limited, as shown in figure 2.11. In actual processes the temperature at which the deposition condition moves from one of these growth regimes to the other depends on the activation energy of the reaction and the gas flow conditions in the reactor. In processes that are under surface-reaction-rate-limited conditions, the deposition temperature is an important parameter [23]. That is, uniform deposition rates throughout a reactor require conditions that maintain a constant reaction rate. This, in turn, implied that a constant temperature must also exist everywhere at all wafers. On the other hand, under such conditions the rate at which reactant arrive at the surface is not so important, because their concentrations do not limit the growth rate. Thus, it is not so critical that a reactor be designed to supply an equal flux of reactants to all locations of a wafer surface.
Figure 2.11 The deposition rate Rg is a rapid varying function of temp.(T) in
the surface-reaction-limited regime of operation, whereas it changes only slowly with temperature in the mass-transport-limited regime (high temperature).
- 33 -
In deposition processes that are mass-transport-limited, the temperature control is not so critical. The mass transport process, which limits the growth rate, is only weakly dependent on the temperature [24]. On the other hand, it is very important that the same concentration of reactants be presented in the bulk gas regions adjacent to all locations of a wafer, because the arrival rates of the reactants are directly proportional to the concentration gradient in the bulk gas. Thus to ensure that films are uniform across a wafer, reactors operated in the mass-transport-limited regime must be designed so that all the locations of the wafer surface and all the wafers in a run are supplied with an equal flux of reactant species.
2.3.6 Plasma fundamental
Plasma processes are widely used in the semiconductor industry for etch, CVD, PVD, and photo-resist strip. Plasma is a quasi-neutral gas of charged and neutral particles which exhibits collective behavior.
2.3.6.1 Physical characteristics of plasma
Any body of gas typically contains three species: neutral atoms or molecules, ions and electrons. Their relative concentrations (for example, the degree of ionization) are considerably different in plasma. The concentration of ions in the atmosphere is negligibly small. In typical glow discharge plasma used in CVD processes, ionic concentrations are of the order of 1010 per cm3. The electron concentration is the same as the ion concentration, so the overall plasma is electrically neutral.
- 34 -
From fundamental kinetic theory, the kinetic energy of a particle is given by
ε = ½mν2
An understanding of the interactions between the three types of species
and the energetic involved in these processes is essential for us to make use of plasmas in producing thin films. Energy transfer into plasma and between the species, diffusion phenomena within the plasma and chemical reactions in the presence of charge species are some of the processes that depend on collisions between the three species.
Electron concentration 1010 to 1011 per cm3 Ion concentration 1010 to 1011 per cm3 Electron temperature 3-5eV
Ion temperature 0.05eV Electron velocity 107 cm /s Ion velocity 104 cm /s Table 2.1 Properties of a typical glow discharge.
2.3.6.2 Plasma chemistry
In a field-free space, charged particles behave the same way as neutrals, and their behavior can be treated similarly using the kinetic theory of gases
- 35 -
[25]. Collisions between particles can be written in terns of a mean free path λ
given by
λ=1 / √2 nσ
n is the number density of the particles and σ is the collision cross section.
There are many kinds of inelastic collisions happening simultaneously in plasma. Three of them are the most important in CVD process, ionization, excitation-relation and dissociation.
Ionization in the plasma can occur through many mechanisms; the simplest is electron capture. For neutral species having high electron affinity, the following reaction occurs readily:
F + e- → F-
Electron capture contributes significantly to electron loss in halogen-containing plasma. An important mechanism for the maintenance of a glow discharge is the production of ions through electron impact. For instance, collision between an energetic electron and a xenon atom produces a xenon ion and another electron.
- 36 -
The two electrons are now accelerated by the potential gradient in a sheath to ionize more neutral, starting a chain reaction. The electrons have to posses a higher energy than the ionization potential of the neutral (~12eV for xenon) for this process to occur.
Excitation-Relaxation is an extreme case of the various excited states that an atom or a molecule can reach on electron impact, similar to ionization. There are electron energy thresholds equal to the energy of the first excited state, and they need to be exceeded for the excitation to occur.
e- + A → A* + e- A* → A +h ν
where h is plank constant, and ν is the frequency of the glow light. Different atoms or molecules have different frequencies, that which is why different gases have different glow colors. Oxygen glow is grayish blue, nitrogen glow is pink, and fluorine glow is red, etc.
When a molecule dissociates upon electron impact either its constituent atoms or further ionized products. Of more relevance to CVD is the formation of radicals in the plasma [26]. When an electron collides with a molecule, it can break the chemical bond and generate free radicals which are molecular fragments with unpaired electrons:
- 37 -
Collision Byproducts Energy of Formation
e-+ SiH
4 SiH2+ H2+e- 2.2eV
SiH3+ H +e- 4.0eV Si + 2H2 +e- 4.2eV SiH+ H2+H + e- 5.7eV SiH*+ 2H +e- 8.9eV
Si*+ 2H
2 +2e- 9.5eV
SiH2++ H
2+2e- 11.9eV
SiH3++ H +2e- 12.32eV
Si++ 2H
2+2e- 13.6eV
SiH+ + H2+H + 2e- 15.3eV
e- + AB → A + B + e-
For example, in the Silane oxide process:
e- + SiH4 → SiH3 + H +e-
e- + N2O → N2 + O + e
- 38 - 2.3.6.3 Plasma parameters
There are some plasma parameters like thermal velocity, mean free path and Boltzman distribution [27].
Electron thermal velocity can be expressed as
u = (k T / m) ¹′²
while k=1.38 x 10¯²³ ，T is temperature and m is the particle mass. For plasma in CVD chamber, ，Te ≅ 2eV，thus Ve ≅ 5.93 x107 cm/sec = 1.33x 107 mph.
For Argon ion (Ar+), TAr ≅ 0.05eV, the thermal velocity is as:
Vi=3.46x104 cm/sec = 774 mph
In plasma, both electron and ion energy follow the Boltzman distribution. the average electron energy is about 2eV to 3eV, while ion energy in the bulk plasma is mainly determined by the chamber temperature , ~ 200℃ to 400℃, or 0.03eV to 0.05eV.
圖 2.11 電子能量分怖
Figure 2.12 Boltzmann distribution.
Energy Energy
- 39 - 2.3.6.4 Ion Bombardment
Since electrons move much faster than ions, the electrodes will be charged negative as soon as the plasma is initiated [28]. The negatively charged electrodes will repel negatively charged electrons and attract positive ions, therefore, in the vicinity of the electrodes. There are lesser electrons than ions.
The different between the negative and positive charge causes an electric field, called sheath potential, in that region. The light emission from that region is less intense than the bulk plasma due to fewer electrons and fewer electron collisions, thus a dark space can be observed near the electrodes.
Figure 2.13 The sheath potential accelerates ions towards the electrode where the wafers sits and causes ion bombardment.
- 40 -
In an RF system, the potential on the RF hot electrode changes rapidly. The plasma potential also changes very quickly, because the electron moves fast and anything close to plasma charges negatively, plasma always has a higher potential than anything in contact with it. Therefore, in time average, there is a DC potential difference between the bulk plasma and the electrode. The energy of ion bombardment is determined by the DC bias, which is about 10 to 20 volts in CVD chambers.
Figure 2.14 DC potential difference between the bulk plasma and the electrode .
Plasma potential depends on RF power, pressure, and spacing between the electrodes, since RF power also affects the plasma density, the capacitance (parallel plate) coupled plasma sources can not independently change ion energy and ion flux [29].
- 41 -
Ions are much heavier than electrons, thus the ions move much more slowly in the RF plasma and have much less energy than the electrons, thus, at 13.56MHz the RF field coupled energy exclusively into the electrons and leaves the ions cold.
2.4 Chemical vapor deposition systems
CVD reactors are divided into two primary types: atmospheric pressure and low pressure CVD. There are a number of atmospheric pressure CVD and Sub-atmospheric pressure CVD. Most advanced device films are deposited in systems where the pressure has been lowered. These are called low pressure CVD or LPCVD.
CVD systems ate operated with two principal energy sources: thermal process and plasma process. Thermal sources are tube furnace, hot plates, and RF induction. Plasma enhanced chemical vapor deposition (PECVD) and high density plasma CVD in combination with lower pressure offers the unique advantage of lowered temperatures and good film composition and coverage.
2.4.1 Atmospheric pressure CVD systems
As the name implies, atmospheric CVD systems reactions and deposition take place at atmospheric pressure. There is an another thermal process CVD is called Sub-atmospheric pressure chemical vapor deposition (SAPCVD) which process range is from several torr to 600torr .
- 42 -
Figure 2.15 Schematic diagram of the APCVD.
2.4.1.1 Sub-atmospheric CVD (SAPCVD)
Atmospheric pressure CVD (APCVD) reactors were the first to be in the microelectronics industry. Operation at atmospheric pressures keeps reactor design simple and allow high film deposition rate. APCVD [30] [31], however, is susceptible to gas-phase reactions, and the film typically exhibit poor step coverage. Since APCVD is generally conducted in the mass-transport- limited regime, the reactant flux to all parts of average substrate in the reactor must be precisely controlled.
Wafers are transported to three deposition areas in sequence by a load belt and conveyed out of the hot area by the unload belt. The belt is continuously cleaned of the SiO2 deposited on its surface in a belt cleaner. Central to the
- 43 -
unique injector design. Oxidizers and hydrides, which react to form the film, are kept separate till the gases exit the injector onto the surface of the wafers.
The injector creates a chemical vapor curtain under which the wafers are transported by the belt. The curtain contains a tri-linear flow of oxygen in Nitrogen (N2), and hydride in N2. Deposition occurs in a small zone where the
residence time of the reactants is minimized by the high gas flow volumes. The wafer is heated through a resistive heater block situated beneath the reaction surface.
APCVD benefits on high throughput, good uniformity, and the capability to process large -diameter wafers. However, they have the problems of high gas consumption and frequent need of reactor cleaning.
Films are produced by the following general reactions:
SiH4 + 2O2 → SiO2 + 2H2O
2PH3 + 4O2 → P2O5 + 3H2O
and
B2H6 + 3O2 → B2O3 + 3H2O
- 44 - 2.4.2.1 SACVD Introduction
Recently, Sub-atmospheric pressure CVD is very common systems in 300mm manufacturing for dielectric bulk film deposition and gap filling process by using TEOS and ozone (O3). This CVD technology enables the
formation of oxide films with high conformality and low viscosity under low deposition temperatures. The step angle depends on the ozone concentration,
Borophosphosilicate glass (BPSG) [32] [33] has been widely used as a pre-metal dielectric in advanced very large scale integrated (VLSI) device fabrication. As device dimensions keep shrinking, BPSG has the advantages of filling high aspect ratio gaps and at the same time, achieving global planarization over the device surface due to its reflow capability at elevated temperature (> 800℃), without overstretching the thermal budget as compared to phosphosilicate glass (PSG) films. Using current chemical vapor deposition (CVD) technology, BPSG films can be deposited either by SILANE or O3-TEOS (tetraethylorthosilicate) based BPSG processes, with TEOS/O3
BPSG film shown much better step coverage than SILANE BPSG film. Among all the technologies, sub-atmospheric (SACVD) BPSG using triethylphosphate (TEPO) and triethylborate (TEB) as dopant sources have been studied extensively to yield superior film quality and improved reflowed capability [34]. However, due to the process complexity, very little is known about the reaction mechanism for TEOS/O3 BPSG, even though some
modeling has been done for the un-doped silicon glass (USG) using TEOS/O3
chemistry. Comparing the two processes, BPSG has been proven to have enhanced deposition rate with no surface sensitivity. However, BPSG films
- 45 -
have worse step coverage as deposited, including changes in the reaction mechanism by the addition of doped precursors into the reaction chamber.
In addition, for the TEOS based processes, a certain type of carrier gas, for instant, helium or nitrogen, is utilized to deliver vaporized TEOS and liquid doped sources to the process chamber to reduce gas-phase nucleation for particle control. Due to their distinct physical properties, such as heat capacity and thermal and mass diffusivities, different carrier gases may result in different film characteristics.
The schematic shown in figure 2.16 is the SACVD chamber, which is described in detail elsewhere. Briefly, this is a single wafer process tool equipped with the precision-liquid-injection system (PLIS TM) for accurate and repeatable TEOS, TEB, and TEPO delivery. Liquid TEOS and dopants are vaporized and carried into the process chamber using a carrier gas (He or N2) [35], then mixed with ozone (O3) at the top of the reactor. Both liquid injection
valves and liquid delivery lines are heated to prevent liquid condensation. after flow redistribution through the block and faceplate with optimized hole sizes and density, the gas mixture impinges onto the wafer, which is on a hot surface called heater (400℃ to 550℃), to form BPSG film. The heater temperature is controlled by heating module and the variation temperature is within less than 5℃. During deposition, the gas-phase temperature is controlled by both the heater as well as the chamber wall, which is maintaining at a constant temperature, to reduce gas nucleation. An in situ plasma chamber cleaning process was performed after each wafer deposition to ensure BPSG process repeatability and particle control over thousands of wafers. The controlling
- 46 -
variables for BPSG deposition include liquid flow of (TEOS, TEB, and TEPO), carrier gas type (N2 or He) and flow, heater temperature (T), and spacing (Sp),
as well as chamber pressure (Pr).
Figure 2.16 Schematic diagram of the SACVD.
2.4.2.3 Introduction to SACVD process
All film properties were evaluated on 300mm p-type silicon substrates. The film thickness and uniformity were monitoring by KLA Tencor and the doped concentrations were measure using both XRF(X-ray fluorescene spectroscopy) and FTIR, calibrated by inductively coupled plasma atomic emission spectroscopy (ICP-AES) for B2O3 and P2O5 weight percent (w/o).For
gap fill evaluation, all the BPSG films were deposited at 5.0B w/o X 5.0 P w/o, and annealed at 800℃ in N2 ambient for 30 minutes.
For SACVD, reaction temperature are generally at 480 ℃ . Earlier application of the TEOS reaction were in the formation of
- 47 -
borophosphosilicate glass (BPSG) films, with proper doped additives, this reaction is still one of the most popular sub- atmospheric pressure BPSG reaction [36] [37].
Doping of the SiO2 network by network modifiers and other
glass-forming oxides serves the following purpose: (a) Dopant additives tend to lower the melting point of the glass, (b) they alter the viscosity of the glass at high temperatures, and (c) below certain concentrations they introduce the properties if the glass former without phase segregations from the SiO2 matrix.
For instance, boron oxides provide high temperature stability to the glass, whereas phosphorus oxides make the glass hygroscopic. Dopants also alter the glass transition temperature, for instance, ordinary window glass has sodium-based network properties, while the oven-to-table commercial glasses contain glass former such as B2O3.
The common additives to SiO2 for semiconductor applications are boron
and phosphorus oxides for poly-metal dielectrics, and arsenic for doping applications. Boron and phosphorus additions tend to lower the melting temperature, reduce the intrinsic stress in the glass, allow for better glass flow due to reduce viscosity, and phosphorus additions getter sodium ions. Phosphorus doped-glass (PSG) finds application as a passivation film to protect the device against sodium. Boron-doped glass (BSG) is used as a boron doped source.
Borophosphosilicate glass (BPSG) deposited by the Sub-Atmospheric CVD (SACVD) has been investigated for both gap-fill the Inter-layer Dielectric (ILD) trenches before etch back and the structural layer deposition
- 48 -
of the dopant activation to enable the fabrication process for the 90nm DT DRAM [38]. The result obtained suggest that the timing of incorporation of the Phosphorous dopant to the gas phase chemistry of the silicate glass plays an important roles in the reflow mobility and the nitric film consumption. The TEPO introduction should come later and gradually than the forming Borosilicate glass mixture (BSG).
It is important for BPSG applications in the semiconductor industry as an inter-metallic dielectric between the aluminum and the poly-silicon. BPSG deposition in SACVD is based on the pyroligneous decomposition of tetraethylorthosilicate (TEOS), triethylborate (TEB) and, triethylphosphate (TEPO) in an oxidizing atmosphere. The incorporation of Boron and Phosphorous in the BPSG effects the ability of the glass to reflow at temperature ranges compatible with the reduced thermal budget criteria employed in today’s chip devices. The presence of Phosphorous enhances the ability of the glass to getter and trap alkali metal impurities thus, prevent the migration of these deleterious species into the active regions.
In advance ULSI processes, reduction of junction depths caused more restrictive thermal budgets and limit the time and temperature available for the flow anneal process [39]. PSG reflow at 1000-1100 ℃ could result in excessive diffusion of shallow junction. Furthermore, impurity implanted MOS gate oxides cannot be exposed to high temperature (>900℃). However, to easing film coverage over the substrate topography, a flowing glass is still desirable prior to metal deposition. The glass flow temperature as low as 700 ℃ can be obtained by adding the boron dopant to the PSG gas flow mixture.
- 49 -
A ternary (three component) oxide system is formed; B2O3-P2O5-SiO2. The
boron (B) concentration is more dominant in determining the flow characteristics than the phosphorous (P) concentration.
The reflow ability of the glass to provide void free or seam free is critical for providing proper metal contact step coverage [40]. With the scaling down of device feature sizes, the manufacturing challenge presented by submicron devices is the ability to completely fill a narrow trench in a void-free manner. As the trench gets narrower and the aspect ratio (the ratio of the trench height to the trench width) increases, it becomes more likely that the opening of the trench will "pinch off." Pinching off a trench traps a void within the trench. Under certain conditions, the void will be filled during the reflow process; however, as the trench becomes narrower, it becomes more likely that the void will not be filled during the reflow process. Such voids are undesirable as they can reduce the yield of good chips per wafer and the reliability of the devices. Therefore, it is desirable to be able to fill narrow gaps with BPSG in a void-free manner. The difficulty to fill the gaps is observed when conducting in this study, the reduction in interconnect pitches of the 90nm devices and high aspect ratio of the trenches between interconnect lines.
USG process
O
3O
2+ O
O + Si(OC
2H
5)
4USG + volatile organics
heat
heat
O
3O
2+ O
O + Si(OC
2H
5)
4USG + volatile organics
heat
- 50 - PSG process BPSG process
For SA BPSG film gap-fill, a significant improvement of PMD gap-fill has been achieved with changes in a main silicon precursor from TEOS to the mixture of TEOS and fluorinated TEOS, F-BPSG processes met the chosen target gap-fill parameters for “vertical” structure types defined as Gv<0.05 μm
and ARv>2, as can be seen in figure 2.17 as well as tapered structure types. It
is known that fluorine contained compounds, being added to the gas-phase during chemical vapor deposition or plasma-enhanced deposition, improves film step coverage. Fluorinated SABPSG films hence provide much better gap-fill after rapid thermal anneal at 850°C for 30 seconds. This means that from a gap-fill point of view, this approach can be considered as an option for PMD with small device gaps at least at studied structure requirements if other approaches of structure tapering can not be used.
O + TEOS + TEPO PSG + volatile organics
heat
O + TEOS + TEPO PSG + volatile organics
heat
O + TEOS + TEPO + TEB BPSG + volatile organics heat
O + TEOS + TEPO + TEB BPSG + volatile organics heat
- 51 -
Figure 2.17 Vertical (left) and tapered (right) structure types show gap fill with BPSG with RTP of 850oC for 30seconds.
FTIR spectra of samples recorded immediately after film deposition did not reveal any moisture peaks in the area around 3000 cm-1 for both studied 4.5B-4P and 5.5B-4.5P dopant concentrations. The refractive index values have been found to be slightly higher for SA F-BPSG films. RTA of SA F-BPSG films at 850°C for 30secondss was found to decrease refractive index values, increase shrinkage values to twice that of SABPSG films, and increase surface charge values from about 5.8×E10 q/cm2 to 6.5×E10 q/cm2. After
prolonged storage in clean-room conditions followed by RTA anneal, changes in the properties of SA -FBPSG films have been found to be more pronounced indicating that SA -FBPSG film properties need to be investigated in detail.
Gap-fill capability of SAPSG and SABPSG films deposited using 1-step and 2-step deposition processes at 480°C and 550°C and annealed at low thermal budget conditions in a dry gas ambient have been studied for film application as a void-free pre metal dielectric for 0.18 μm device technology and beyond [41]. Gap-fill capability was found to be strongly effected by using different structure types. “Tapered” structures with gaps 0.03 um and aspect ratios up to 6 have been successfully filled with all studied film options using
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rapid thermal anneal at temperatures as low as 800-850°C for 30seconds in nitrogen ambient. Difficulties with film gap-fill capability have been found to arise with the use of “vertical”, “partly vertical” and especially, with “re-entrant” structures. Films of fluorinated borophosphosilicate glass deposited at sub-atmospheric pressure conditions (SA F-BPSG) have been found to be able to improve gap-fill for “vertical” structures significantly at the same low thermal budget anneal condition.
2.4.3 Plasma enhanced chemical vapor deposition PECVD
2.4.3.1 PECVD introduction
When a gas is excited by a high enough electric field, for example, in the reaction chamber of a plasma deposition reactor such as the one shown in figure 2.18, a glow discharge (plasma) is formed. In the plasma, high energy electrons exist that can impart enough energy to reaction gases for reaction that normally take place only at high temperature to proceed near room temperature. The reactor looks superficially like the sputtering equipment, but there are some substantial differences. In plasma-enhanced CVD (PECVD) [42]
[43], the inlet gas contains the reactants for deposition, and the anode instead
of being sputtered away remains unaffected. The voltage applied to sputtering electrodes may be either RF or DC, depending on the specific mode of operation, but plasma deposition requires RF voltage.
The glowing (plasma) region will contain, in addition to the free electrons, normal neutral gas molecules, gas molecules that have become ionized,
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ionized fragment of broken-up gas molecules, and free radicals. Deposition occurs when the molecules of incoming gases are broken-up in the plasma and then the appropriate ions are recombined at the surface to give the desired film.
Plasma enhanced CVD chambers can use Silane to deposit silicon oxide, nitride, and oxy-nitride, they also can use TEOS to deposit doped and un-doped oxide [44] [45].
Figure 2.18 Schematic diagram of PECVD.
2.4.3.2 PECVD process introduction
The surface of both oxide and silicon exposed to the ambient are covered by hydrogen. Thus, the crystal lattice at the surface does not terminate with silicon and oxygen and dangling bond, but with OH in the case of oxide and SiH4 in the case of silicon.
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Thermal energy at 400℃ does not cause the chemisorbed precursors to leave the surface. However, in PECVD processes, ion bombardment has enough energy (10 to 20eV) to remove some chemisorbed precursors off the surface.
Silane is a molecule with a tetrahedron structure: A silicon atoms in the center and four hydrogen atoms, because there is a chemical bond, the chemisorbed molecules have very low surface mobility.
Figure 2.19 SILANE bonding.
Silane is pyrophobia, explosive, and toxic gas that which is widely used in the semiconductor industry as a silicon source to deposit silicon oxide or silicon nitride.
In the case of silane, the parent molecule will neither chemisorb nor physisorb to the oxide surface. The parent molecule is too symmetrical to react with the surface (i.e. chemisrb) and the hydrogen atoms are not capable of
Si H H H H Si H H H H
