Dynamic Characteristic Optimization of 14 a-Si:H
TFTs Gate Driver Circuit Using Evolutionary
Methodology for Display Panel Manufacturing
Yiming Li, Member, IEEE, Kuo-Fu Lee, I-Hsiu Lo, Chien-Hshueh Chiang, and Kuen-Yu Huang, Member, IEEE
Abstract—For thin-film transistor liquid crystal display (TFT-LCD) panel manufacturing, a gate driver circuit with amorphous silicon TFT plays an important role. In this paper, an amorphous silicon gate (ASG) driver circuit is optimized to improve circuit’s dynamic characteristics. The adopted simula-tion-based evolutionary method integrates genetic algorithm and circuit simulator on the unified optimization framework. The circuit consisting of 14 hydrogenated amorphous silicon TFTs (a-Si:H TFTs) used in a large panel is optimized for the given specifications of the rise time 1.5 s, the fall time 1.5 s, and the ripple voltage 3 V with minimizing the total layout area. By optimizing the width and passive components of the 14 devices, the results of this study successfully meet the desired specifications, where the sensitivity analysis is further conducted to verify the characteristic variation with respect to the optimized parameters. To validate the results, the optimized circuit is fabricated with 4- m a-Si:H TFT process, and the experimental result confirms the practicability of achieved design. The ripple voltage within 2.0 V is successfully obtained while the rise and fall times satisfy the required specifications for the fabricated sample. A 35% reduction of the optimized total devices width of a-Si:H TFTs is achieved.
Index Terms—Amorphous silicon gate driver circuits (GDCs), dynamic characteristic, fabrication, fall time, genetic algorithm, liquid crystal display (LCD), measurement, panel manufacturing, ripple voltage, rise time, simulation-based optimization, thin-film transistor (TFT).
I. INTRODUCTION
T
HIN-FILM transistor liquid crystal displays (TFT-LCDs) for the application of smart phones is being developed rapidly in points of resolution, pixels per inch (PPI), number of colors, and brightness. Thus, integrating a driver circuit on the TFT backplane is one of the fascinating challenges in a quarter video graphics array (QVGA) resolution LCD panel because ofManuscript received July 19, 2010; revised October 05, 2010; accepted December 10, 2010. Date of current version April 05, 2011. This work was supported in part by Taiwan National Science Council (NSC), under Contract NSC-97-2221-E-009-154-MY2 and NSC-99-2221-E-009-175, and by the Chimei-InnoLux Display Corp. Miao-Li, Taiwan, under a 2009-2011 grant.
Y. Li is with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and with the Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: ymli@faculty.nctu.edu.tw).
K.-F. Lee and I.-H. Lo are with the Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.
C.-H. Chiang and K.-Y. Huang are with the Chimei-InnoLux Corporation, Science-Based Industrial Park, Chu-Nan, Miao-Li County 350, Taiwan.
Color versions of one or more of the figures are available online at http:// ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JDT.2010.2102336
its many advantages, such as overall cost reduction, compact-ness, and mechanical reliability [1]–[5]. Diverse approaches, such as low temperature polycrystalline silicon (LTPS), hy-drogenated amorphous silicon (a-Si:H) [6], [7], and zinc-oxide (ZnO) [8], [9] are proposed as an active channel material in n-channel TFTs, as well as gate driver circuits sequentially. However, additional processes which resulted in increasing cost are necessary in LTPS technology. Furthermore, there are sev-eral reliable problems of amorphous silicon gate (ASG) driver circuit that should be considered in ZnO film [10]. Therefore, nowadays, because of the cost merits due to simple process and high yield, a-Si:H process has been main stream in gate driver circuit of TFT-LCD for mobile application [11]–[13]. In general, the topology of ASG driver circuit is requested to achieve superior and stable output waveform. Therefore, dy-namic characteristics are usually obtained empirically to meet the required specifications [14]–[16] for given ASG circuits. A trial-and-error method is generally adopted by circuit designers to tune circuit parameters including device geometry, biasing, etc. This design flow generally is a time-consuming task to meet all desired specifications in display circuit manufacturing. In addition, the methodology of simulation-based evolutionary approach has recently been proposed for optimizing device’s doping profile [17]–[19] and equivalent circuit model parameter extraction [20] in our previous works. Optimization results of these studies have confirmed the robustness and efficiency of the proposed method. Systematical optimization approach, based upon simulation-based evolutionary methodology, will be an interesting study for optimal design of TFT-LCD panel circuits, and thus benefit their manufacturing.
In this work, we demonstrate an optimized gate driver circuit on glass substrate to improve dynamic characteristics. Then simulation-based evolutionary algorithm on the unified optimization framework [21] is successfully advanced on performing optimal design of the circuit on a-Si:H TFT-LCD panel. The circuit to be optimized consists of three pull-up control devices, three pull-down control devices, three pull-up output devices and five pull-down output devices, where all devices’ widths are parameters to be designed for the specifi-cations of the rise time 1.5 s, the fall time 1.5 s and the ripple voltage 3 V while we simultaneously consider the minimization of total layout area. As for the optimized solutions achieved by the method, the sensitivity analysis is simultaneously considered to verify how the variation in dy-namic characteristics of optimized circuit. We analyze a set of solutions for optimized ASG driver circuit by varying 0.5 m of each width and 0.2 m of each length statistically. The
LI et al.: DYNAMIC CHARACTERISTIC OPTIMIZATION OF 14 a-Si:H TFTs GATE DRIVER CIRCUIT 275
Fig. 1. (a) Illustration of the method for optimizing the ASG driver circuit. The replacement mechanism is age-based but with 10% elitist and 30% regenerate random individuals. The mechanism of the variation operators: (b) crossover and (c) mutation.
final optimized ASG driver circuit is further fabricated with 4- m process a-Si:H TFT technology. The comparison of dynamic characteristics of measurement and simulation are disscussed in detail.
This paper is organized as follows. In Section II, the genetic algorithm and the implemented simulation-based optimization method are introduced. In Section III, the explored ASG driver circuit is optimized and discussed. In Section IV, the fabricated and measured results are shown to validate our theoretical re-sults. Finally, we draw conclusions and suggest future work.
II. OPTIMIZATIONTECHNIQUE ANDSIMULATIONRESULTS
The unified optimization framework (UOF) [21] enables us to implement the optimization method to design ASG driver cir-cuit with the most suitable parameters. The UOF can evolve the parameter configuration of circuit by genetic algorithm (GA) [22]–[24] and achieve particular performance of the circuit with the parameter configuration as the basis to obtain fitness value by executing external circuit simulator [25]–[28]. The flow is shown in Fig. 1(a); for a script file of netlist depending on ASG driver circuit topology, we define the parameters of ASG driver circuit to be optimized in a circuit mask file. Then, the initial population, i.e., the group of parameter configurations, is gener-ated by engineering design or random selection. Implementation of the evaluation mechanism is by putting the parameters into mask file to obtain the complete circuit netlist file (intermediate file), and then sending the file into circuit simulator to acquire the circuit characteristics automatically. As soon as evaluation is completed for all individuals (an individual indicates a specific configuration), the parents (relatively better individuals) are se-lected by the fitness proportional method and are ready to gen-erate offspring—new individuals. Two variation operators are applied on the parents to attain this goal. The first is one-point crossover [29], [30]. The split point in one-point crossover is randomly determined, then the genes of offspring (here we treat the parameter configuration—individual—as a parameter array, and an element in the array is called gene, which means cer-tain parameter) from beginning to split point will be inherited by one parent, and the rest will be inherited by the other parent, as disclosed in Fig. 1(b). After the crossover operator, the mu-tation operator enables to randomly choose two genes in one
Fig. 2. Comparison of the score convergence behavior of the algorithm in ASG driver circuit among (a) population sizes, where the crossover and mutation rate are fixed at 0.6 and (b) and mutation rate, where the crossover is fixed at 0.6 and population size is fixed at 100, respectively.
individual and exchange them with mutation rate, as shown in Fig. 1(c). Notably, the mutation rate which influences diversity of GA must be carefully determined. Finally, except the best 10% individuals in last generation, which are called elitists, and 30% regenerate individuals, the other part of the population is substituted by the offspring after variation operators. If the char-acteristics meet the requirement prescribed by the circuit de-signer, we output the final optimized solution. If the error be-tween the specifications and characteristics does not meet the convergence criterion, the UOF performs GA to execute next it-eration (genit-eration) from evaluation step. The process will be continued until the specifications are matched. The parameters
Fig. 3. (a) A schematic of active matrix LCD panel controlled by ASG driver circuit. (b) Components of one stage ASG driver circuit and the output waveform affected by corresponding component of ASG driver circuit. (c) Ffirst ASG driver circuit consists of 14 a-Si:H TFTs which used in large loading products such as monitor and screen of TV. (d) Timing diagram of 14-TFTs-ASG driver circuit.
TABLE I
PARAMETERSSETTING OFGENETICALGORITHM IN OURCIRCUITDESIGN
OPTIMIZATION
setting of GA in circuit design optimization is summarized in Table I, and be set in configuration file.
By considering the experiment, Fig. 2(a) shows a compar-ison of the fitness score convergence behavior among popu-lation sizes, where the crossover and mutation rate is fixed at 0.6. The fitness score versus the number of generation suggests that the score convergence behavior does not have a satisfied result if the population size is too small. However, large popu-lation size obviously cause high consumption of time and is not sure to achieve better results. According to our experience, the is good for the optimal design of ASG driver circuit. In addition, Fig. 2(b) shows the fitness score con-vergence behavior for the circuit optimization with different mu-tation rate, where the population size and crossover rate are fixed at 100 and 0.6. An excessively high mutation rate makes the global search in GA similar to random search, whereas the lack of mutation chances may cause local convergence and lose the diversity. The results suggest that the keeps the population diversity and finally has better evolutionary results.
The original and optimization simulation results of proposed ASG driver circuit are discussed. At the first, we briefly intro-duce the operation of explored ASG driver circuit. Then the numerical experiments for the proposed explored ASG driver circuit are realized and discussed. Finally, the sensitivity anal-ysis verifies the characteristic variations of optimized circuits. A schematic of active matrix LCD panel controlled by ASG driver circuit in product [31] is shown in Fig. 3(a); each stage of ASG driver circuit consists of pull-up and pull-down control circuits, pull-up and pull-down output circuits, as shown in Fig. 3(b). The output state, VGH, and rise time of output waveform are influenced by designed pull-up output circuit. The steady state, VGL, and fall time of output waveform are affected by designed pull-down output circuit, respectively. Fig. 3(c) and 3(d) shows one stage circuit of the proposed ASG driver circuit used in products and its timing diagram. The ASG driver circuit with 14 a-Si:H TFTs used in large loading products such as monitor and screen of TV. Then in circuit’s topology, the CLK and CLKB denote the clock signal and clock bar signal; VGL is the steady-state voltage, and is inputted pulse signal. The and are the output signal which supply for the panel and next stage, respectively. Fig. 3(d) shows timing diagram of ASG driver circuit with 14 devices and the operation of 14-TFTs–ASG driver circuit is as follows. When the input signal is high, the node is charged by the input signal ; then, as CLK is changed from low to high, the node voltage is boosted up due to the gate–drain capacitive coupling of M10. Therefore, the output driving ability ( and ) is achieved through M7 and M10. At this time, the high voltage of the
LI et al.: DYNAMIC CHARACTERISTIC OPTIMIZATION OF 14 a-Si:H TFTs GATE DRIVER CIRCUIT 277
Fig. 4. (a) Original and optimized simulation results of 14-TFTs ASG driver circuit. The inset table indicates demanded specifications. (b) Comparison of TFT widths between the original and optimized designs.
node is applied to the gates of M4 simultaneously. Therefore, M11 is turned off, and the high voltage is kept at the node. After generating an output voltage, the node voltage is discharged when the output signal of next stage is applied to the gate of M12. After that, the node is alternately discharged through M13 by using the CLKB signal.
The designed parameters of 14-TFTs ASG driver circuit are the widths of a-Si:H TFT devices, as shown in Fig. 4. The spec-ifications, original, and optimized results of the output signal which contains the fall time, the rise time, and the ripple voltage in the ASG driver circuit are shown in the inset table of Fig. 4(a), respectively. The rise time is defined by the interval of time re-quired for leading edge of a pulse raised from 10% to 90% in the peak pulse amplitude and the definition of fall time is con-trary to rise time. The ripple voltage is defined by maximum peak-to-peak voltage after the pulse. These three electrical char-acteristics are the required specifications in the ASG driver cir-cuit design generally. The inset table of Fig. 4(a) indicates the specifications, original and optimized results. The original re-sult shows that the fall and rise times are within the given speci-fications; however, the ripple voltage compared with our setting criteria is extremely high. Therefore, the aforementioned evolu-tionary approach is activated to find the feasible configuration of device widths based on the netlist file of the initial circuit.
Finally, the ripple voltage after optimization decreases signifi-cantly from 5.419 to 1.904 V while we keep the rise time and fall time satisfied the required specifications. Fig. 4(b) shows the original design by empirical experience and our optimization. There is 35% reduction of the optimized total devices width of a-Si:H TFTs compared with the initial one in this explored ASG driver circuit. For the given targets and specifications, it shows that this methodology provides an automatic mechanic to design the parameters of the explored ASG driver circuit.
Sensitivity analysis is a technique which considers how small changes in decision variables affecting the function outputs. For designed parameters which fulfill aforementioned specifi-cations, we analyze a selected and modified solution for ASG driver circuit by 0.5 m of each width and 0.2 m of each length with optimized widths sequentially. In the mathematical statement, if represents the function value in the anal-ysis point, then we can observe the variation of the function with small perturbation of , then the sensitivity of in respect to can be expressed as [32]
(1) where is each decision variable. Fig. 5 shows the sensitivity of 14-TFTs ASG driver circuit which may result from process variation effects in the circuit, respectively. In Fig. 5(a), the sen-sitivity of 14 parameters is almost lower than 10%. However, the electrical characteristics are rather susceptible to the parameter W8 which controlled the charge ability of the TFT array devices of display panel. Therefore, the parameter W8 induces larger sensitivity. We further examine the sensitivity of length varia-tion with optimized widths, as explored in Fig. 5(b). The same phenomena are observed in ASG driver circuit. The sensitivity of electrical characteristics is also dominated by W8 of 14-TFT ASG driver circuit. Moreover, due to parameter L11 is compo-nent of pull-down output circuit, the sensitivity of fall time is quite large. Finally, the result can guarantee the robustness of our optimized design and confirm promising characteristics of these ASG driver circuits which have benefits to manufacturing of TFT-LCD panel.
III. SAMPLEFABRICATION ANDMEASUREMENTRESULTS
Standard process flow of TFTs is considered for the sample fabrication of optimized ASG driver circuits. The measurement results of rise time, fall time, and ripple voltage of samples are discussed in detail. The inverted-staggered back-channel etched (BCE) type of a-Si:H TFTs fabricated on glass sub-strate is used for gate driver circuit. First, the gate electrode of 300-nm-thick Mo/AlNd (GE) alloy is deposited by physical vapor deposition method on the glass substrate and patterned. Thereafter, 380-nm-thick silicon-nitride SiN , 150-nm-thick undoped a-Si:H layer, 50-nm-thick n+ a-Si:H are deposited by chemical vapor deposition method and the a-Si:H layers are patterned. The silicon-nitride layer is served as the gate insulator and deposition temperature is about 300 C–350 C. The undoped a-Si:H layer is served as the active layer and deposition temperature is about 220 C–350 C. The n+ a-Si:H layer is used to form the ohmic contacts at source/drain (S/D) electrodes, which are deposited by physical vapor deposition method and then patterned. The n+ a-Si:H layer in TFT channel
Fig. 5. Sensitivity analysis of the14-TFTs ASG driver circuits. (a)60.5 m of each width with L = 4 m. (b) 60.2 m of each length with optimized widths sequentially.
Fig. 6. (a) Cross section view of SEM picture of fabricated TFT sample and the process variation of: (b) L5 and (c) L11 of 14-TFTs ASG driver circuit.
region is etched off by dry etching method and then overetched until the undoped a-Si:H layer. The back channel passivation layer Si N of 200-nm-thick is deposited by chemical vapor deposition method and patterned. Finally, the contact hole is deposited with 50-nm ITO layer by physical vapor deposition method, as a pixel electrode (connected with source or drain). A cross-section view of scanning electron microscope (SEM) picture of fabricated TFT sample is shown in Fig. 6(a). In addition, the process variation of lengths of ASG driver circuits which makes agreement to assumptions of sensitivity analysis is shown in Fig. 6(b) and (c). Test chips of the optimized
Fig. 7. Experimental results of rise time, fall time, and ripple voltage for 14-TFTs ASG driver circuit measured by using a Tektronix DP04054 oscillo-scope.
14-TFTs ASG driver circuit are fabricated in the standard 4- m a-Si:H TFT technology.
We examine the tested layout which consists of six stages gate driver circuit and occupies the area of 1.386 mm . A Chroma 58162-E signal generator and a Tektronix DP04054 oscilloscope were used to carry out the aforementioned input signal. As for the measurements more precisely, the input signal, STV (SP), CLK, CLKb, and VSS are set as same as the simulation. Then the measured dynamic characteristics of the chip are illustrated in Fig. 7 where the rise time, fall time, and ripple voltage is 1.23 s, 1.17 s, and 1.9 V, respectively.
LI et al.: DYNAMIC CHARACTERISTIC OPTIMIZATION OF 14 a-Si:H TFTs GATE DRIVER CIRCUIT 279
Fig. 8. (a) Comprehensive comparison among the fabrication data of the orig-inal/optimized setting and the specifications. (b) Comparison of simulation and fabrication results of 14-TFTs ASG driver circuit.
Fig. 9. Optical image of the fabricated 14-TFTs ASG driver circuit occupied area of 0.231 mm .
Comprehensive comparison among the fabrication data of the ASG driver circuit with original/optimized design and the spec-ifications are disclosed in Fig. 8(a). The improvement of ripple voltage is 71% for the 14-TFTs ASG driver circuit while we also successfully maintain the rise time and the fall time within the required specifications. In additional, the experimental characterization results are close to the simulation results or even better than the theoretically estimated data, as listed in Fig. 8(b). Fig. 9 shows the optical image of our optimized one stage ASG driver circuit with 14-TFTs by using SEM and occupied the area of 0.231 mm 1050 m 220 m .
IV. CONCLUSION
In this study, we have demonstrated an optimized ASG driver circuit for manufacturing using the simulation-based evolutionary approach. The approach combines GA with circuit simulator on the unified optimization framework to execute the optimization flow automatically. It successfully extracts the designed parameters in ASG driver circuit. The ripple voltage of 14-TFTs ASG driver circuit is significantly decreased from 5.419 to 1.904 V while we simultaneously maintain its dynamic characteristics within the required specifications. Sensitivity analysis has further shown promising and stable electrical characteristics of optimized parameters. The optimized ASG driver circuit was fabricated using standard process of 4- m a-Si TFTs technology. The experimental results of 14-TFTs
ASG driver circuit are close to simulation results and the im-provement of ripple voltage is 71% as compared with original design. Consequently, this approach is highly extensible to design different functional block of display panel circuits. In additional, the reliabilities, such as temperature and bias-stress, and power consumption in ASG driver circuit are currently examined. Notably, layout technique could be improved em-pirically for approaching to the theoretical estimation of 35% reduction of total layout.
ACKNOWLEDGMENT
The authors thank Chimei-InnoLux Display Corporation, Miao-Li, Taiwan, for instrumental help about the sample fabri-cation and characteristic measurement.
REFERENCES
[1] P. Servati, S. Prakash, A. Nathan, and C. Py, “Amorphous silicon driver circuits for OLED displays,” J. Vac. Sci. Technol., vol. 20, no. 4, pp. 1374–1378, 2002.
[2] K. Khakzar, “Modeling of a-si-thin-film transistors and design of driver circuits for flat panels,” Ph.D. dissertation, Univ. of Stuttgart, Stuttgart, Germany, 1991.
[3] N. Arokia, K. Anil, S. Kapil, S. Peyman, S. Sanjiv, and S. Denis, “Amorphous silicon thin film transistor circuit integration for organic LED displays on glass and plastic,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1477–1486, Sep. 2004.
[4] B. S. Bae, J. W. Choi, J. H. Oh, and J. Jang, “Level shifter embedded in drive circuits with amorphous silicon tfts,” IEEE Trans. Electron Devices, vol. 53, no. 3, pp. 494–498, Mar. 2006.
[5] J. Jeon, K.-S. Choo, W.-K. Lee, J.-H. Song, and H.-G. Kim, “Integrated a-si gate driver circuit for TFT-LCD panel,” in SID Dig.’04, 2004, pp. 10–13.
[6] C.-W. Chen, T.-C. Chang, P.-T. Liu, H.-Y. Lu, K.-C. Wang, C.-S. Huang, C.-C. Ling, and T.-Y. Tseng, “High-performance hydrogenated amorphous-si TFT for AMLCD and AMOLED applications,” IEEE Electron Device Lett., vol. 26, no. 10, pp. 731–733, Oct. 2005. [7] T. Kamiya, K. Nomura, and H. Hosono, “Origins of high mobility and
low operation voltage of amorphous oxide tfts: Electronic structure, electron transport, defects and doping,” J. Display Technol., vol. 5, no. 12, pp. 468–483, Dec. 2009.
[8] V. Subramanian, T. Bakhishev, D. Redinger, and S. K. Volkman, “So-lution-Processed zinc oxide transistors for low-cost electronics appli-cations,” J Display Technol, vol. 5, no. 12, pp. 525–530, Dec. 2009. [9] T.-H. Hwang, S.-I. Hong, W.-K. Hong, W.-H. Cui, I.-S. Yang, O.-K.
Kwon, C.-W. Byun, S.-H. Park, C.-S. Hwang, and K. I. Cho, “A scan driver circuit using transparent thin film transistors,” in SID Dig.’09, 2009, pp. 1136–1139.
[10] D. C. Look, G. C. Farlow, P. Reunchan, S. Limpijumnong, S. B. Zhang, and K. Nordlund, “Evidence for native-defect donors in n-type zno,” Phys. Stat. Sol. (PRL), vol. 95, pp. 1–4, 2005.
[11] M. D. Chun, S. Y. Yoon, Y. H. Jang, K. S. Park, H. Y. Kim, B. Kim, H. N. Cho, S. C. Choi, T. W. Moon, N. W. Cho, S. H. Jo, C. Y. Sohn, C.-D. Kim, and I.-J. Chung, “Bi-directional integrated a-si gate driver circuit for LCD panel with RGBW quad subpixels,” in Proc. ASID’06, 2006, pp. 125–127.
[12] J. H. Koo, J. W. Choi, Y. S. Kim, M. H. Kang, S. H. Kim, E. B. Kim, H. Uchiike, S.-W. Lee, and J. Jang, “Hydrogenated amorphous silicon gate driver made of thin-film transistors,” J. Korean Phys. Soc., vol. 50, no. 4, pp. 933–936, Apr. 2007.
[13] S.-F. Chen, L.-H. Chang, J.-R. Chen, S.-C. Lin, C.-M. Yu, J.-H. Hsu, and I.-C. Chen, “Integrated a-Si TFT gate driver with reducing clock duty ratio,” in SID Dig. 09, 2009, pp. 1092–1095.
[14] N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Sys-tems Perspective. Reading, MA: Addison-Wesley, 1988.
[15] D. Green, Modern Logic Design. Reading, MA: Addison-Wesley, 1986, pp. 15–17.
[16] D. Hodges and H. Jackson, Analysis and Design of Digital Integrated Circuits. New York: McGraw-Hill, 1988.
[17] Y. Li, “Hybrid intelligent approach for modeling and optimization of semiconductor devices and nanostructures,” Comput. Mater. Sci., vol. 45, no. 1, pp. 41–51, 2009.
[18] Y. Li, S. M. Yu, and Y. L. Li, “Intelligent optical proximity correc-tion using genetic algorithm with model- and rule-based approaches,” Comput. Mater. Sci., vol. 45, no. 1, pp. 65–76, 2009.
[19] Y. Li, “A simulation-based evolutionary approach to LNA circuit de-sign optimization,” Appl. Math. Comput., vol. 20, no. 1, pp. 57–67, 2009.
[20] Y. Li and Y. Y. Cho, “Intelligent BSIM4 model parameter extraction for sub-100 nm MOSFET era,” Jpn. J. Appl. Phys., vol. 43, no. no. 4b, pp. 1717–1722, Apr. 27, 2004.
[21] Y. Li, S. M. Yu, and Y. L. Li, “Electronic design automation using a unified optimization framework,” Math. Comput. Simul., vol. 79, no. 4, pp. 1137–1152, 2008.
[22] K. Deb and D. E. Goldberg, J. D. Schaffer, Ed., “An investigation of niche and species formation in genetic function optimization,” in Proc. 3rd Int. Conf. Genetic Algorithms, San Mateo, CA, 1989, pp. 42–50. [23] C. M. Fonseca and P. J. Fleming, S. Forrest, Ed., “Genetic algorithms
for multiobjective optimization: Formulation, discussion and general-ization,” in Proc. 5th Int. Conf. Genetic Algorithms, San Mateo, CA, 1993, pp. 416–423.
[24] D. E. Goldberg, B. Korb, and K. Deb, “Messy genetic algorithms: Mo-tivation, analysis, and first results,” Complex Syst., vol. 3, pp. 93–530, Sept. 1989.
[25] H.-M. Huang and Y. Li, “A unified parameterization technique for TFT-LCD panel design optimization,” in Proc. Int. Asia Symp. Quality Electron. Design, 2009, pp. 153–156.
[26] Y. Li, J. W. Lee, B. S. Lee, C. S. Lu, and W. H. Chen, “A novel SPICE compatible current model for OLED circuit simulation,” in Tech. Proc. 2005 NSTI Nanotechnology Conf. Trade Show, 2005, vol. 3, pp. 103–106.
[27] J. E. Meyer, “MOS models and circuit simulation,” RCA Rev., vol. 32, pp. 42–63, 1971.
[28] S.-Y. Oh, D. E. Ward, and R. W. Dutton, “Transient analysis of MOS transistors,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1571–1578, Aug. 1980.
[29] Z. Michalewicz, Genetic Algorithms + Data Structures = Evolution Programs. New York: Springer, 1996.
[30] G. Lin and X. Yao, “Analyzing crossover operators by search step size,” in Int. Conf. Evol. Comput., 1997, pp. 107–110.
[31] H.-C. Chen, K.-Y. Chiang, M.-D. Chen, C.-P. Kung, and W.-H. Hou, “A-Si robust gate driver for 7.0-in. WVGA LCD panel,” in SID Dig. 07, 2007, pp. 222–225.
[32] A. Saltelli, S. Tarantola, F. Campolongo, and M. Ratto, Sensitivity Analysis in Practice. West Sussex, U.K.: Wiley, 2004.
Yiming Li (M’02) received the B.S. degree in applied
mathematics and electronics engineering, the M.S. degree in applied mathematics, and the Ph.D. degree in electronics from the National Chiao Tung Univer-sity (NCTU), Hsinchu, Taiwan, in 1996, 1998, and 2001, respectively.
In 2001, he joined the National Nano Device Laboratories (NDL), Hsinchu, as an Associate Re-searcher, and the Microelectronics and Information Systems Research Center (MISRC), NCTU, as a Research Assistant Professor, where he has been engaged in the field of computational science and engineering, particularly in modeling, simulation, and optimization of nanoelectronics and very large scale integration (VLSI) circuits. In the fall of 2002, he was a Visiting Assistant Professor with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst. From 2003 to 2004, he was a Research Consultant with the System on a Chip (SoC) Technology Center, Industrial Technology Research Institute, Hsinchu. From 2003 to 2005, he was the Head of the Departments of Nanodevice and Computational Nanoelectronics, NDL, and since the fall of 2004, he was a Research Associate Professor with MISRC. From the fall of 2005 to fall of 2008, he was an Associate Professor with the Department of Communication Engineering, NCTU, where he is currently a Full Professor with the Department of Electrical Engineering, is the Deputy Director of the Modeling and Simulation Center, and conducts the Parallel and Scientific Computing Laboratory. He is also the Deputy Director General of NDL. His current research areas include computational electronics and electromagnetics, physics of semiconductor nanostructures, transport simulation and model parameter extraction for semiconductor and photonics devices, computer-aided-design theory and technology, biomedical and energy harvesting devices simulation, parallel and scientific computing, and optimiza-tion methodology. He has authored or coauthored over 200 research papers appearing in international book chapters, journals, and conferences. He has
served as a Reviewer, Guest Associate Editor, Guest Editor, Associate Editor, and Editor for more than 30 international journals. He has served as an active Reviewer for seven IEEE journals. He has organized and served on several international conferences and was an Editor for proceedings of international conferences.
Dr. Li is a member of Phi Tau Phi and is included in Who’s Who in the World. He was the recipient of the 2002 Research Fellowship Award presented by the Pan, Wen-Yuan Foundation, Taiwan, the 2006 Outstanding Young Electrical En-gineer Award from the Chinese Institute of Electrical EnEn-gineering, Taiwan, and the Best Paper Award of the 2009 IEEE Asia Symposium on. Quality Electronic Design, Kuala Lumpur, Malaysia.
Kuo-Fu Lee received the B.S. degree in electrical
engineering from the Tatung University, Taipei, Taiwan, in 2008 and the M.S. degree in commu-nications engineering from the National Chiao Tung University, Hsinchu, Taiwan, in 2010. His research interests focus on modeling and simulation of semiconductor nano-devices and optimization of amorphous silicon gate (ASG) circuit.
I-Hsiu Lo received the B.S. degree in communication
engineering from the National Chiao Tung Univer-sity in 2009, and is currently a graduate student at the same university.
His research work focus is on evolutionary algo-rithm and optimization of display circuits.
Chien-Hshueh Chiang received the B.S and
M.S. degrees from National Tsing-Hua University, Hsinchu, Taiwan, in 2003 and 2005, respectively, specializing in the design of the analog circuit, the MOSFET process and bipolar junction transistor (BJT), and very large scale integration (VLSI) design.
From 2005, he is with Chimei-Innolux Corporation, Taiwan, working in thin-film transistor liquid crystal display (TFT-LCD) and researches the integrated driving circuit for TFT-LCD. The main development is the mass production of the gate-on-panel (GOP).
Kuen-Yu Huang received the B.S. degree in
electrical engineering from the National Tsing-Hua University, Hsinchu, Taiwan, in 1996, and the M.S. and Ph.D degrees in electronics from the National Chiao-Tung University, Hsinchu, Taiwan, in 1998 and 2005, respectively.
In 2005, he was with the National Center for High-Performance Computing, Hsinchu, Taiwan, as assistant researcher, and responsible for wireless communication system establishment. In 2007, he joined Springsoft Corporation as a technical associate manager in charge of software usage analysis. In 2008, he joined Chimei-Innolux Corporation, Taiwan, as an Associate Manager of CAD department. His research interests include electrical design automation algo-rism, macro circuit modeling for LCD panel, and TFT device circuit model extraction.
Dr. Huang is a member of the IEEE Microwave Theory and Techniques Society, the IEEE Electron Devices Society, and the IEEE Solid-State Circuits Society.
