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IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 10, OCTOBER 2001 463

Impact of Silicide Formation on the Resistance of

Common Source/Drain Region

Bing-Yue Tsui, Member, IEEE, Ming-Da Wu, and Tian-Choy Gan

Abstract—Silicide had been used to reduce the sheet resistance of diffusion region for almost 20 years. However, as the silicided re-gion becomes small, the contact resistance of silicide/silicon inter-face becomes higher than the resistance of the Si diffusion region such that current may not flow into the silicide layer. The effect of silicide thickness and contact resistivity on the total resistance of the silicided diffusion region was studied by two-dimensional sim-ulation. It is observed that below a threshold length, the resistance of silicided diffusion region is higher than the unsilicided diffusion region if the silicon consumption during silicide formation is taken into consideration. Thinner silicide and lower contact resistivity re-duce total resistance and threshold length but the threshold length is still much longer than the typical design rule of poly-Si to poly-Si distance. It is thus recommended to inhibit silicide formation at the common source/drain region at the metal-gate generation.

Index Terms—Contact resistance, silicide, simulation.

I. INTRODUCTION

S

ALICIDE technology had been used for all high–perfor-mance integrated circuit process [1]. Using salicide tech-nology, the high–resistance diffusion region and poly-Si gate are shunted by a low resistivity metal silicide layer. Because silicide is formed by direct reaction of metal with silicon, the contact resistance of silicide-silicon interface is also reduced by the clean interface and large contact area. The advantages of sili-cide had been analytically analyzed by D.B. Scott, et al. [2]. It was shown that the resistance of silicided diffusion region with metal contact could be reduced effectively. However, this is not the case at silicided diffusion region without metal contact, e.g., two MOSFETs connected in serial with a common diffusion re-gion (CDR). At this rere-gion, current flows in Si originally. To take the advantage of silicide, current must flow into silicide at first and flow into Si again. As the length of CDR becomes shorter and shorter, current does not flow into silicide because of the high–contact resistance.

In the previous work, the consumption of heavily doped Si layer by silicide was not considered. With the progress of pro-cessing technology, the scale-down of silicide thickness lags be-hind the scale-down of junction depth [3]. Therefore, the sheet resistance of diffusion region under silicide may be increased by silicide formation apparently. The role of silicide layer at CDR

Manuscript received May 22, 2001; revised July 2, 2001. This work was supported by the National Science Council, Taiwan, R.O.C., under Contract NSC-89-2815-C-009-062R-E. The review of this letter was arranged by Editor C.-P. Chang.

The authors are with the Department of Electronics Engineering and Insti-tute of Electronics, National Chiao–Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: bytsui@cc.nctu.edu.tw).

Publisher Item Identifier S 0741-3106(01)08854-1.

Fig. 1. Schematic cross-sectional view of the structure used for two-dimensional simulation. Resistance components are also indicated.

R is accumulation layer resistance at the gate to source/drain overlap region. R consists of spreading resistance and diffusion resistance of diffusion region

under spacer.R is the resistance of common diffusion region.

becomes interesting. In this work, two-dimensional (2–D) sim-ulation was performed to study the impact of silicide thickness and contact resistivity on the resistance of CDR without metal contact. A brief discussion on the feasibility of unsilicided CDR is provided at last.

II. SIMULATIONPROCEDURE

Fig. 1 shows the cross-sectional view of the structure used for simulation. Two MOSFETs with typical drain structure are connected in serial through a CDR without metal contact. A box shape is used for the junction. It had been reported that the simplified box shape does not affect the validity of simu-lation results of the diffusion region [4]. The carrier concentra-tion is estimated by the Gaussian-distribuconcentra-tion with peak concen-tration at surface. The lateral diffusion is assumed to be 70% of the vertical junction depth. The carrier concentration of the accumulation layer underneath the gate is assumed to be iden-tical to the surface concentration of the heavily doped region ( cm ) and the thickness of this layer is 10 nm [5]. The bulk concentration and the surface concentration of source/drain

extension region is cm and cm ,

respec-tively. The silicide thickness is assumed to be equal to the con-tact interface depth ( ). The right boundary of the accumula-tion layer at right side is kept at and the left boundary of the accumulation layer at left side is kept at 0 V. The structure is par-titioned into resistor network. The node voltage and branch cur-rent were solved numerically by applying Kirchholff’s curcur-rent law to the resistor network. The total resistance ( ) is defined

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464 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 10, OCTOBER 2001

Fig. 2. Total resistance (R ) versus length of common diffusion region (L ) withM of 25 nm, 35 nm, and 55 nm. The  was kept at 10 ohm0m .

as the divided by the total current. It consists of all resistance components between the two accumulation layers as shown in Fig. 1.

The effect of contact resistivity ( ) and silicide thickness ( ) on the total resistance of silicided and unsilicided CDR were simulated. The spacer length ( ) is assumed to be 0.1 m. The junction depth of heavily doped region and source/drain extension region is 0.11 m and 0.07 m, respec-tively. The channel width is fixed at 1 m throughout the work.

III. RESULTS ANDDISCUSSION

Fig. 2 shows the simulated as a function of the distance between spacers ( ) with of 25 nm, 35 nm, and 55 nm. The was fixed to be 10 ohm m . The silicide thickness of 25–35 nm is generally used in the current 0.18 m or 0.13 m technology, while the thickness of 55 nm is the upper limit sug-gested by ITRS roadmap [3]. In the case of unsilicided CDR, decreases linearly with as expected. In the case of silicided CDR, nonlinear phenomenon is observed and it is sur-prising that thicker results in higher at all . Cross point of the characteristics of unsilicided CDR and silicided CDR is observed. The crosspoint is defined as the threshold length ( ) of the CDR. As is longer than , of the silicided CDR is lower than that of the unsilicided CDR and vice versa. It should be noted that the (0.89 m as nm and 0.6 m as nm) is much longer than the general design rule of poly-Si to poly-Si distance.

The simulated results can be understood by considering the two current paths: silicide layer and diffusion layer. If is much longer than the transfer length ( ) of the silicide-silicon contact interface [6], the contact resistance is lower than the dif-fusion resistance and current prefers to flow through the silicide layer. In this case, is composed of the sheet resistance of silicide layer and contact resistance across silicide-silicon in-terface. On the other hand, once becomes close to , the contact resistance is higher than the diffusion resistance and current tends to flow in the diffused layer. Unfortunately, the sheet resistance of diffused layer under silicide is higher than

Fig. 3. Total resistance (R ) versus length of common diffusion region (L ) with of 5, 10, 15, 20, and 50 ohm0m . The M was kept at 35 nm.

that at unsilicided region because the high–concentration layer was consumed by the silicide. The is then the result of two high–resistance paths in parallel and the sheet resistance of sili-cide layer plays minor role. Therefore, thicker silisili-cide thickness results in higher and longer .

Fig. 3 shows the simulated as a function of with of 5, 10, 15, 20, and 50 m . The was fixed at 35 nm. The relation of unsilicided CDR is also shown. The increases with the increase of as expected. Again, the is much longer than the typical design rule of poly-Si to poly-Si distance.

To prove the existence of , test structures with two MOS-FETs connected in serial were fabricated with standard 0.18 m cobalt-salicide CMOS technology. Only NMOS test structure was designed. The gate length is 0.18 m and the spacer length is 0.1 m. A set of test structures employed a silicide-blocking mask to inhibit silicide formation at the CDR. The other set of test structures has typical salicide structure. These structures

were measured at linear region ( , V and

V). The difference of transconductance ( ) between silicided and unsilicided test structures is defined as

silicided unsilicided unsilicided

Fig. 4 shows the measured as a function of . A of 0.24 m was observed. Below 0.24 m, the silicided test struc-tures show lower than the unsilicided test structure. This re-sult confirms the existence of . The low of 3% and the short of 0.24 m arises from the unusual structure of deep junction depth (0.25 m) and thin silicide thickness (28 nm).

IV. CONCLUSION

The impact of silicidation on the resistance of CDR was studied using 2-D simulation. A threshold length was ob-served. As is shorter than , silicided CDR shows higher resistance than the unsilicided CDR. Thinner silicide layer and lower contact resistivity can reduce the . However, the is still much longer than typical design rule of poly-Si to

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TSUI et al.: IMPACT OF SILICIDE FORMATION ON THE RESISTANCE 465

Fig. 4. Measured transconductance difference (1g ) versus length of common diffusion length (L ) between test structures with silicided and unsilicided common diffusion region.

poly-Si distance. The series resistance between the two devices must not be estimated using the sheet resistance of silicide layer. To block the CDR is unacceptable at current poly-Si gate technology because part of the poly-Si gate will also be blocked. Polycide gate allows silcide blocking at CDR but polycide

process is seldom used in high–performance deep–submicron products. Beyond 0.07 m technology node, metal gate may replace poly-Si gate. Then, silicide is only needed at diffusion region but not at gate region. Inhibiting silicide formation at CDR becomes easy. It is, thus, recommended to neglect silicide at CDR in the future metal-gate technology node.

ACKNOWLEDGMENT

The authors would like to thank T. J. Yang at Silicon Inte-grated Systems Corp. for his on test structure fabrication.

REFERENCES

[1] T. Shibata, K. Hieda, M. Sato, M. Konaka, R. L. M. Dang, and H. Iizuka, “An optimally designed process for submicron MOSFETs,” in IEDM

Tech. Dig., pp. 647–650, 1981.

[2] D. B. Scott, W. R. Hunter, and H. Schichijo, “A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits,”

IEEE Trans. Electron Devices, vol. ED-29, pp. 651–661, 1982.

[3] International Technology Roadmap for Semiconductors,

Semicon-ductor Industry Association, 2000, pp. 73–74.

[4] B. Y. Tsui and M. C. Chen, “Series resistance of self-aligned silicided source/drain structure,” IEEE Trans. Electron Devices, vol. 40, pp. 197–206, 1993.

[5] K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series resistance of MOSFETs,” IEEE Trans. Electron Devices, vol. ED-33, pp. 965–972, 1986.

[6] H. H. Berger, “Models for contacts to planar devices,” Solid State

數據

Fig. 1. Schematic cross-sectional view of the structure used for two-dimensional simulation
Fig. 2. Total resistance ( R ) versus length of common diffusion region (L ) with M of 25 nm, 35 nm, and 55 nm
Fig. 4. Measured transconductance difference ( 1g ) versus length of common diffusion length ( L ) between test structures with silicided and unsilicided common diffusion region.

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