Ultra-high-voltage charge pump circuit in low-voltage bulk CMOS processes with polysilicon diodes

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(1)IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 1, JANUARY 2007. 47. Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes Ming-Dou Ker, Senior Member, IEEE, and Shih-Lun Chen, Student Member, IEEE. Abstract—An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25- m 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V powersupply voltage (VDD = 2 5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage ( 18.9 V) in a 0.25- m 2.5-V bulk CMOS process. Index Terms—Charge pump circuit, high-voltage generator, polysilicon diode.. I. INTRODUCTION. C. HARGE pump circuits can generate the dc voltages those are higher than the normal power-supply voltage (VDD) or lower than the ground voltage (GND). Charge pump circuits are usually applied to the nonvolatile memories, such as EEPROM and flash memories, to write or to erase the floating-gate devices [1]. Besides, charge pump circuits can be also used in some low-voltage designs to improve the circuit performance [2]. In the applications of MEMS (micro-electro-mechanical systems) and electroluminescent display, the charge pump circuit must provide the output voltage higher than 15 V, even up to 60 V [3]–[7]. Early, the p-n-junction diodes were applied in the charge pump circuit. However, it is difficult to implement the fully independent p-n-junction diodes in the common silicon substrate. The charge pump circuit realized with transistors in the diode-connected style was reported by Dickson [8], [9]. Owing to the body effect, the pump efficiency of the Dickson charge pump circuit is degraded as the number of the stages increases. Several modified charge pump circuits based on the Dickson charge pump circuit were reported to enhance the pumping efficiency [10], [11]. As the semiconductor process is scaled down, the normal circuit operation voltage (VDD) of the integrated circuits (ICs) is. Manuscript received September 8, 2005; revised February 25, 2006. This work was supported by National Science Council (NSC), Taiwan, R.O.C., under Contract NSC 95-2221-E-009-290. This paper was recommended by Associate Editor T. Ueta. The authors are with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan 300, R.O.C. (e-mail: mdker@ieee.org). Digital Object Identifier 10.1109/TCSII.2006.882854. also decreased. The reliability issue must be considered to design the charge pump circuit in the deep-sub-micron CMOS processes, such as the gate-oxide overstress problem [11]. Fig. 1(a) shows the cross section of the -well diode in the grounded p-substrate with the shallow-trench isolation (STI). The -well diode is one kind of the p-n-junction diodes in the bulk CMOS process. In Fig. 1(a), an undesired parasitic p-n junction exists between the n-well and the grounded p-type substrate. If -well diode is larger the voltage on the cathode of the than the junction breakdown voltage between the n-well and the grounded p-substrate, the charges on the cathode will leak to ground through the parasitic p-n junction. Fig. 1(b) shows the cross section of the diode-connected nMOS, whose gate and drain are connected together, in the grounded p-substrate. In Fig. 1(b), an undesired p-n junction parasitizes between the region (source/drain) and the grounded p-type substrate. Similarly, if the voltages on the cathode or anode of the diode-connected nMOS are larger than the junction breakdown voltage region and the grounded p-type substrate, the between the charges on the cathode or anode will also leak to ground through -well (p-n juncthe parasitic junction. Thus, whenever the tion) diodes or the diode-connected MOSFETs are used to design the charge pump circuit, the maximum output voltage will be limited by the breakdown voltage of the undesired junctions in the standard CMOS process. In the silicon-on-insulator (SOI) CMOS process, the devices are isolated to others by the insulator layer. Thus, the charge pump circuits realized in the SOI process can pump the output voltage higher without the limitation of the parasitic p-n junctions [3], [4]. However, the SOI CMOS process is more expensive than the bulk CMOS process. In this work, an on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes is proposed. The polysilicon diodes have been used in the negative charge pump circuit [12] and the on-chip electrostatic discharge (ESD) protection circuit [13]. Because the anode and the cathode of the polysilicon diodes are fully isolated from the silicon substrate, the voltages on the anode or the cathode of the polysilicon diodes are not limited by the breakdown voltage of the undesired parasitic p-n junction. The proposed on-chip ultra-high-voltage charge pump circuit with the polysilicon diodes has been successfully implemented and verified in a 0.25- m 2.5-V standard (bulk) CMOS process. II. POLYSILICON DIODES A. Device Structure of Polysilicon Diodes The gates of pMOS and nMOS are both realized with the n-type doped polysilicon in the early standard CMOS processes.. 1057-7130/$25.00 © 2007 IEEE.

(2) 48. Fig. 1. Schematic cross sections of (a) the. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 1, JANUARY 2007. p + =n-well diode, and (b) the diode-connected nMOS, in grounded p-type substrate.. Fig. 2. Schematic cross section of the polysilicon diode in the bulk CMOS process.. Due to the work function consideration, the gate of pMOS and the gate of nMOS are realized with the p-type doped polysilicon and the n-type doped polysilicon, respectively, in the recent sub-quarter-micron standard CMOS processes. In order to implement the different types of the polysilicon gates, the intrinsic polysilicon layer is deposited first, and then the p-type and n-type impurities are doped into the intrinsic polysilicon layer to form the pMOS gate and the nMOS gate, respectively. Hence, the diode can be realized on the polysilicon layer in the recent standard CMOS processes those have separated doping impurities for pMOS and nMOS gates. Fig. 2 depicts the cross section of the polysilicon diode in the bulk CMOS process. As shown in Fig. 2, the STI layer is located above the silicon substrate. The polysilicon layer is deposited on the STI layer. Then, the p-type and n-type highly doped regions on the polysilicon are doped with the same process step of the pMOS and nMOS source/drain ion implantation, respectively. Thus, the polysilicon diode is fully compatible to the standard CMOS process without any extra process modification. Because the polysilicon diode is implemented on the STI layer, it is isolated from the silicon substrate. The charges on the anode and the cathode of the polysilicon diode don’t leak to the silicon substrate. Therefore, the polysilicon diodes can be applied to the charge pump circuit without the limitation of the parasitic junctions. In the polysilicon diode, an extra un-doped (intrinsic) polysilicon region (i) can be inserted between the p-type and n-type doped polysilicon regions. The length (Lc) of the un-doped region can be used to adjust the I–V characteristics of the polysilicon diode. B. Characteristics of Polysilicon Diodes The polysilicon diodes with different lengths (Lc) of the un-doped region have been fabricated in a 0.25- m 2.5-V bulk CMOS process, where the Lc is changed from 0.25 to 1.5 m. Fig. 3 shows the measured I–V curves of the polysilicon diodes. Fig. 3. Measured I–V curves of the polysilicon diodes with different lengths (Lc) of the un-doped region.. Fig. 4. Measured cut-in voltages of the polysilicon diodes with different lengths (Lc) of the un-doped region. The cut-in voltages are defined at the 1-A forward biased current.. with different Lc. Fig. 4 shows the measured cut-in voltages of the polysilicon diodes with different Lc, where the cut-in voltages are defined at the 1- A forward biased current. In Fig. 4, the cut-in voltages of these polysilicon diodes vary from 0.47 to 0.58 V. As the length of the un-doped region is larger than 0.9 m, the cut-in voltage saturates at around 0.58 V. Fig. 5 shows the measured reverse breakdown voltages and reverse leakage currents of the polysilicon diodes with different lengths (Lc) of the un-doped center region, where the reverse breakdown voltages are defined at the 1- A reverse biased current and the reverse leakage currents are defined at the 2.5-V reverse biased voltage. In Fig. 5, the reverse breakdown voltage increases when the Lc increases. As the Lc is longer than 1.2 m, the reverse breakdown voltage of the polysilicon diode is higher than 20 V. Moreover, the reverse breakdown voltage is.

(3) KER AND CHEN: ULTRA-HIGH-VOLTAGE CHARGE PUMP CIRCUIT. 49. Fig. 7. Photograph of the four-stage charge pump circuit with five polysilicon diodes (Lc=0.5 m) fabricated in a 0.25-m 2.5-V bulk CMOS process. Fig. 5. Measured reverse breakdown voltages (@ 1-A reverse biased current) and the reverse leakage currents (@ 2.5-V reverse biased voltage) of the polysilicon diodes with different lengths (Lc) of un-doped region.. level as VDD, the voltage fluctuation in each stage can be simply expressed as (3) Hence, (2) can be simplified as (4) The power efficiency of the charge pump circuit is defined as [14], [15]. Fig. 6. Four-stage charge pump circuit realized with 5 polysilicon diodes.. 33 V when the length of the un-doped region is 1.5 m. Hence, the reverse breakdown voltage of the polysilicon diode can be adjusted by changing the length (Lc) of the un-doped center region for different applications.. (5) In (5), (VDD).. is the total current flowing from the power supply can be derived as [14]. III. CHARGE PUMP CIRCUIT WITH POLYSILICON DIODES (6). A. Circuit Implementation Fig. 6 depicts the four-stage charge pump circuit designed with 5 polysilicon diodes (PD1 PD5), where the clock signals, CLK and CLKB, are out-of-phase with the amplitude levels of VDD. RL and CL in Fig. 6 represent the output resistance and capacitance loading, respectively. A larger CL can make the output voltage of the charge pump circuit more stable. As shown in Fig. 6, the charge pump circuit uses the polysilicon diodes as the charge transfer devices. The charges are pushed from the power supply (VDD) to the output node (Vout), stage by stage, in every clock cycle. The voltage fluctuation between each stage can be expressed as (1) where is the voltage amplitude of the clock signals (CLK and CLKB), is the pumping capacitance (C1 C4), is the parasitic capacitance at each pumping node, is the output current, and is the clock frequency. The output voltage of the charge pump circuit can be expressed as (2) where is the cut-in voltage of the polysilicon diode and n is and the number of stages in the charge pump circuit. If are small enough and is large enough, and can be ignored in (1). Because is usually with the same voltage. The power efficiency of the charge pump circuit can be calculated from the (5) and (6). B. Experimental Results The four-stage, eight-stage, and 12-stage charge pump circuits with 10-pF on-chip metal-insulator-metal (MIM) pumping capacitors and the polysilicon diodes of 0.5- m and 1- m un-doped region have been fabricated in a 0.25- m 2.5-V bulk CMOS process. The photograph of the four-stage charge pump circuit realized with 5 polysilicon diodes m is shown in Fig. 7. The independent polysilicon diodes with different lengths of the un-doped region are also implemented in this testchip. Fig. 8 shows the measured waveforms of the 12-stage charge pump circuit with the polysilicon diodes m to drive the capacitive output load. In Fig. 8, the power-supply voltage (VDD) and the amplitude of the clock signals (CLK and CLKB) are 2.5 V, and the clock frequency is 1 MHz. As shown in Fig. 8, the output voltage of the charge pump circuit to drive the capacitive load is as high as 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage ( 18.9 V) in the given 0.25- m 2.5-V bulk CMOS process. Fig. 9 shows the measured output voltages of the four-stage, eight-stage, and 12-stage charge pump circuits with the polysilicon diodes of 0.5- m or 1- m un-doped region (Lc). In Fig. 9,.

(4) 50. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 1, JANUARY 2007. Fig. 8. Measured waveforms (CLK and Vout) of the 12-stage charge pump circuit with the polysilicon diodes (Lc = 0:5 m) to drive capacitive output load. The clock frequency is 1 MHz and VDD is 2.5 V.. Fig. 9. Measured output voltages of the four-stage, eight-stage, and 12-stage charge pump circuits with the polysilicon diodes of 0.5-m and 1-m un-doped region to drive capacitive load. The clock frequency is 1 MHz and VDD is 2.5 V.. the proposed charge pump circuits drive only the capacitive loads with the clock frequency of 1 MHz and the power-supply voltage (VDD) of 2.5 V. As shown in Fig. 9, the measured output voltages of the proposed charge pump circuits with the or 1 m) are almost the same. The polysilicon diodes ( length of the un-doped region (Lc) doesn’t obviously affect the output voltage of the proposed charge pump circuit because the voltage across each polysilicon diode doesn’t exceed VDD (2.5 V), which is much smaller than the reverse breakdown voltages or 1 m). of the polysilicon diodes ( Fig. 10 shows the measured output voltages of the four-stage m charge pump circuit with the polysilicon diodes under different clock frequencies, where the power-supply voltage (VDD) is 2.5 V. When the clock frequency is increased, the output voltages of the charge pump circuit are also increased. But, when the clock frequency is low, the output voltages of the charge pump circuit are degraded, especially with a small RL. In Fig. 10, the charge pump circuit can pump the output voltage close to the ideal value in (4) when the RL is large and the clock frequency is high. Fig. 11 compares the measured output voltages of the four-stage charge pump circuits with the polysilicon diodes of 0.5- m and 1- m un-doped region under different power-supply voltages (VDD). In Fig. 11, the charge pump circuits drive only the capacitive loads, and the clock frequency. Fig. 10. Measured output voltages of the four-stage charge pump circuit (Lc = 1 m) with the output loading of 1 M , 10 M , or without the output resistor under different clock frequencies. The power-supply voltage (VDD) is 2.5 V.. Fig. 11. Measured output voltages of the four-stage charge pump circuits with the polysilicon diodes of 0.5-m and 1-m un-doped region to drive capacitive loads under different VDD. The clock frequency is 100 kHz.. is 100 kHz. As shown in Fig. 11, the polysilicon diode with long m can generate a higher output voltage level length m . As the power-supply than that with short length voltage (VDD) is higher than the breakdown voltage of the polysilicon diode with 0.5- m un-doped region but still lower than that of the polysilicon diode with 1- m un-doped region, the charge pump circuit with the polysilicon diode of 1- m un-doped region still pumps the output voltage higher, but the output voltage of the charge pump circuit with the polysilicon diode of 0.5- m un-doped region is degraded. Fig. 12 shows the measured output voltage of the four-stage m with the output resistors of charge pump circuit 1 M , 10 M , and without the output resistor when the clock frequency is 100 kHz. As shown in Fig. 12, the output voltage is degraded when the RL is small. C. Discussion Comparisons among the charge pump circuits realized with the polysilicon diodes (this work), p-n-junction diodes, and MOS diode (Dickson) [8] are shown in Table I. The voltage fluctuations of each stage in the charge pump circuits realized with polysilicon diodes, p-n-junction diodes, and MOS , diodes (diode-connected MOSFETs) are , and , respectively. and are the cut-in voltages of the polysilicon and is the threshold voltage of p-n-junction diodes, respectively..

(5) KER AND CHEN: ULTRA-HIGH-VOLTAGE CHARGE PUMP CIRCUIT. Fig. 12. Measured output voltages of the four-stage charge pump circuits (Lc = 1 m) with the output resistors of 1 and 10 M and without the output resistor under different VDD. The clock frequency is 100 kHz. TABLE I COMPARISONS AMONG CHARGE PUMP CIRCUITS REALIZED WITH POLYSILICON DIODES (THIS WORK), P-N-JUNCTION DIODES AND MOS DIODES. 51. 2.5-V bulk CMOS process. The polysilicon diodes are implemented on the STI layer, which are fully isolated from the silicon substrate. Therefore, the maximum output voltage of the proposed charge pump circuit with the polysilicon diodes isn’t limited by the breakdown voltages of the parasitic p-n junctions. In addition, the polysilicon diodes are fully compatible to the bulk CMOS processes without any extra process modification. The four-stage, eight-stage, and 12-stage charge pump circuits with 10-pF on-chip pumping capacitors and the polysilicon diodes of 0.5- m and 1- m un-doped center region have been fabricated in a 0.25- m 2.5-V bulk CMOS process. To drive the capacitive load, the measured results show that the four-stage m charge pump circuit with the polysilicon diodes can pump the output voltage as high as 28.08 V, whereas the power-supply voltage (VDD) is 2.5 V. The output loading effect and the dependence of clock frequency on the output voltage of the proposed charge pump circuit have been also measured.. REFERENCES. the MOS device. However, increases due to the body effect while the number of pumping stages increases. The differences of power efficiencies among the charge pump circuits realized with polysilicon diodes, p-n-junction diodes, and MOS diodes at each mainly depend on the parasitic capacitance stage, if the charge pump circuits are realized with the same , number (n) of stages, the same pumping capacitance and the same clock frequency [15]. The parasitic capacitance of the polysilicon diode formed on the STI layer has been studied in [13], which is smaller than those of p-n-junction diode and MOS diode. Thus, the power efficiency of the chare pump circuit realized by polysilicon diodes is better than that of the charge pump circuit realized by p-n-junction diodes or MOS diodes. The area of the charge pump circuit is dominated by the on-chip pumping capacitors, so these three kinds of the charge pump circuits occupy almost the same chip area under the same pumping capacitors and the same number (n) of the stages. As described in the previous section, the output voltage of the charge pump circuit realized with p-n-junction diodes is limited by the breakdown voltage ( 18.9 V) of the parasitic n-well/p-substrate junction, and that of the charge pump circuit realized with MOS Diodes is limited by the breakdown voltage -substrate junction in the given ( 7.4 V) of the parasitic 0.25- m bulk CMOS process. However, the output voltage of the charge pump circuit realized with polysilicon diodes isn’t limited by the breakdown voltages of the parasitic p-n junctions. As shown in Fig. 12, the output voltage of the charge pump circuit realized with the polysilicon diodes to drive the capacitive load can be up to 43 V. IV. CONCLUSION An ultra-high-voltage charge pump circuit realized with the polysilicon diodes has been successfully verified in a 0.25- m. [1] T. Tanzawa, Y. Takano, K. Watanabe, and S. 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