高性能晶片電感器與變壓器之設計、特性分析與應用(II)

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行政院國家科學委員會專題研究計畫成果報告

高性能晶片電感器與變壓器之設計、特性分析與應用(II)

研究成果報告(精簡版)

計畫類別：個別型

計畫編號： NSC 97-2221-E-009-042-

執行期間： 97 年 08 月 01 日至 98 年 07 月 31 日

執行單位：國立交通大學電信工程學系（所）

計畫主持人：吳霖

處理方式：本計畫可公開查詢

中華民國 99 年 01 月 06 日

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of silicon MOSFETs. The proposed methodology is based on the transmission-line theory and the cascade and parallel combina-tions of two-port networks. We use only one “reflect” and one “thru” dummy structure on a wafer to remove the feeding net-works with arbitrary geometry surrounding the MOS transistors. The shielding technique is employed to improve the substrate isolation and fixture scalability. To mitigate the parasitic effects of the dangling leg between the MOSFET and the ground plane, microstriplike interconnects are introduced to mount the devices. Full-wave electromagnetic simulations were also accomplished to substantiate the interconnect scalability and network combina-tions. The MOS transistors and deembedding dummy patterns were implemented in a 0.13-μm standard CMOS technology and characterized up to 30 GHz. Compared with the conventional deembedding methods, the proposed approach consumes less than 33% of chip area and characterization time for modeling test keys, while still maintaining high accuracy.

Index Terms—Deembedding, microwave measurements, model-ing, MOSFETs, parasitics.

I. INTRODUCTION

T

HE DESIGN of silicon-based radio-frequency integrated circuits (RFICs) and monolithic microwave integrated circuits requires reliable process technology and foundry design kits. Device modeling and parasitic extraction are significant issues for circuit design to minimize the failures and frequency shifts. Since reliable RF models call for accurate wafer-level microwave characterization of active and passive components, testing methodologies and modeling test keys should be care-fully developed to evaluate the intrinsic device characteristics.

Manuscript received July 8, 2008; revised October 28, 2008. Current ver-sion published January 28, 2009. The review of this paper was arranged by Editor M. J. Kumar.

M.-H. Cho, D. Chen, R. Lee, and C.-S. Yeh are with the ATD Modeling Division, United Microelectronics Corporation, Hsinchu 300, Taiwan (e-mail: mh.cho@msa.hinet.net).

A.-S. Peng is with the ATD Modeling Division, United Microelectronics Corporation, Hsinchu 300, Taiwan, and also with the Department of Commu-nication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.

L.-K. Wu is with the Department of Communication Engineering, National Chiao Tung University, Hsinchu 300, Taiwan.

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2008.2011685

provides the consistent removal of the unwanted parasitic ele-ments of the on-wafer test fixture.

To extract the intrinsic device parameters from microwave measurements, much research effort has been focused on this particular subject. van Wijnen et al. [1] first reported the open deembedding method to remove the admittances of the probe pads using an open dummy structure. Koolen et al. [2] showed that the open-short deembedding procedure using one open and one short dummy pattern could be used to further subtract the impedances of the probe pads and interconnects. Although many other deembedding techniques for parasitic subtraction have been developed, the open-short deembedding is still the current industry standard due to its simplicity and accu-racy [3]–[6]. The aforementioned deembedding methods utilize lumped equivalent circuits to model the feeding networks of the test fixtures in series–shunt configurations. However, as the device is operated at microwave frequencies and/or the inter-connect length is considerable, the lumped-circuit assumption would become invalid because of the distributed nature of the test structures. In an attempt to solve this issue, Chen and Deen suggested that the deembedding method based on cascade configuration could be used to eliminate the parasitic effects without any lumped-circuit representation [7]. Moreover, a flex-ible cascade-based deembedding was also developed to reduce the consumption of chip area [8].

Although much work has been done to date, most research has focused on the accuracy of the parasitic estimation and correction [9]. The purpose of this investigation was to propose a systematic parasitic deembedding procedure to minimize the chip area and characterization time in a mass-production line. With the utilization of the shielding technique, the suggested reflect and thru dummy structures can be used to calculate the parasitics of probe pads and the transmission-line parameters of interconnects, respectively [10]. Based on the transmission-line theory and microwave network analysis, the proposed method can generate the parasitics of feeding networks with arbitrary geometry to efficiently and accurately deembed the parasitic effects of the fixtured MOS transistors with various gate dimensions and multiplier factors. To validate this geometry-scalable deembedding theory, MOS transistors and deembedding structures were fabricated using a UMC 0.13-μm CMOS process, and full-wave electromagnetic (EM) simulations were carried out.

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300 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 2, FEBRUARY 2009

Fig. 1. Illustration of the on-wafer MOSFET test structure and corresponding dummy structures for proposed geometry-scalable deembedding method.

II. GEOMETRY-SCALABLEDEEMBEDDINGTHEORY

A. On-Wafer Test Fixtures

Fig. 1 shows the on-wafer test fixtures, which contain a device-under-test (DUT) and its corresponding dummy struc-tures, for the proposed deembedding theory. The design of RF test keys for global device modeling must cover the complete physical device dimensions, such as channel length, channel width, finger number, multiplier factor, etc. Therefore, both single- and multitransistor (T1− TM) test fixtures should be

employed to extract the device characteristics, multiplier ef-fects, and proximity effects. In general, the gate and drain of the MOSFET are, respectively, connected to the input and output ports, while the source and silicon substrate are tied together to the ground reference. In our design, the source of the MOSFET is connected to the ground shield beneath the signal traces to form a microstriplike transmission line, and thus, the parasitics of the dangling leg between the transistor and the ground plane can be eliminated by simply using a two-port model [11], [12]. Here, the ground shield not only improves the substrate isolation but also provides good fixture scalability [10] and interconnect scalability [8] for the proposed method. The substrate-shielded reflect structure, which consists of a simple open at the input port and a simple short at the output port or vice versa, is used to remove the parasitics of the ground-signal-ground (GSG) pads [10]. A thru dummy with an N -conductor interconnect (I1− IN) is used to evaluate the

transmission-line parameters for subtracting the interconnect parasitics of the M -transistor test fixtures. It should be noted that the multiconductor thru is employed, instead of a single-conductor one, to mitigate the step-discontinuity effects of the pad-to-interconnect interface [13]. Both the discontinuities, respectively, between the probe pads and the interconnection lines and between the interconnection line and the DUT have low-pass effects on the transmission characteristics. Although the step-discontinuity effects are difficult to be extracted and deembedded, they can be mitigated by using the tapered transition.

Fig. 2(a) shows the semidistributed parasitic model based on the cascade and parallel configurations for the modeling test keys. The parasitic components YPAD and ZPAD, which

Fig. 2. Suggested parasitic models for the proposed on-wafer test structures. (a) DUT. (b) Reflect dummy structure. (c) Thru dummy structure.

can be replicated from the reflect structure in Fig. 2(b), are the shunt admittance and series impedance of the probe pads, respectively. Since, here, the shielding technique is applied, the multiconductor interconnect can be modeled as isolated transmission lines in parallel with each other. As shown in Fig. 2(c), after subtracting the probe-pad parasitics of the

N -conductor thru dummy, the transmission-line parameters of

a single-conductor interconnect calculated using the network analysis can be employed to estimate the parasitic effects of the interconnects with arbitrary geometry.

B. Combination of Microwave Networks

As mentioned in the previous section, both the cascade and parallel combinations of two-port networks would be utilized to establish the deembedding procedure. In this case, it is convenient to characterize the fixtured transistors using the

ABCD-parameter representation. For the cascade connection

of two two-port networks, the overall ABCD matrix [AC] is

equal to the product of the individual ABCD matrices [14], namely [AC] = A1 B1 C1 D1 A2 B2 C2 D2 . (1)

Consequently, the embedding and deembedding of two-port networks can be accomplished by multiplying a given matrix by a matrix and by an inverse of matrix, respectively [8].

Similarly, we can have the overall ABCD matrix [AP] of the

two-port networks connected in parallel as follows: [AP] = A1B2+B1A2 B1+B2 B1B2 B1+B2 C1+ C2+(A1−A_B2₁)(D_+B2₂−D1) D1_BB2₁+B_+B1₂D2 . (2)

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cade and parallel configurations can be evaluated and then deembedded.

C. Deembedding Procedure

As shown in Fig. 2, the ABCD matrices of the probe-pad parasitics for ports 1 and 2 are, respectively

[APAD1] = 1 0 YPAD 1 1 ZPAD 0 1 = 1 ZPAD

YPAD 1 + YPADZPAD

(4) [APAD2] = 1 ZPAD 0 1 1 0 YPAD 1 =

1 + YPADZPAD ZPAD

YPAD 1

. (5)

It should be noted that YPAD= YREFLECT,11 and ZPAD=

1/(YREFLECT,22− YREFLECT,11), where [YREFLECT] is the

admittance matrix of the reflect dummy. The thru dummy can be modeled in cascade connection, and its pad parasitics can be subtracted by using [AINT] = [APAD1]−1[ATHRU][APAD2]−1,

where the superscript “−1” denotes the inverse of the matrix and [ATHRU] and [AINT] are the ABCD matrices of the thru

dummy and the N -conductor interconnect without probe-pad parasitics, respectively. Accordingly, the transmission-line pa-rameters of the N -conductor interconnect, such as characteris-tic impedance ZCand propagation constant γ, can be evaluated

as in [15]. Here, we have [AINT] = cosh γl ZCsinh γl 1 ZC sinh γl cosh γl . (6) Based on the aforementioned results, the parasitic effects of the input/output interconnects with arbitrary line length (l1and

l2) for an M -transistor test fixture can be efficiently calculated

from the ABCD matrix of an N -conductor thru, and thus [AINTi] = cosh γli N Z_MC sinh γli M N ZC sinh γli cosh γli , i = 1, 2. (7) The detailed procedure for S-parameter deembedding is summarized as follows.

1) Measure the S-parameters [SDUT], [SREFLECT], and

[STHRU] of the DUT, reflect, and thru, respectively.

late the ABCD matrix [AD] of the intrinsic MOSFETs

using [AD] = [AIN]−1[ADUT][AOUT]−1.

7) Convert [AD] to its S-parameters [SD].

III. RESULTS ANDDISCUSSION

To verify the proposed deembedding theory, MOS transistors and the corresponding deembedding structures were fabricated using a 0.13-μm eight-metal-layer CMOS process. The NMOS transistors with the dimensions of gate length (Lg) = 0.13 μm,

gate width (Wg) = 4 μm, number of fingers (Nf) = 16, and

multiplier factor (M ) = 1, 2, 4, and 8 were connected in a two-port GSG configuration. The multiconductor interconnects with the dimensions of line length (l1and l2) = 41 μm, line width

(W ) = 6 μm, and line separation (S) = 7.5 μm were designed with the EM simulations and placed between the probe pads and transistors. The solid ground shield under the feeding networks was fabricated using the M1 copper layer (the lowest metal

layer) with thickness of 0.32 μm and electrically connected to the ground pads. The dc and RF measurements of the on-wafer test structures were performed on an Agilent 4142B Modular DC Source/Monitor and an Agilent 8510 C Vector Network Analyzer, respectively. Before starting the S-parameter mea-surements, the measurement system was calibrated using the line-reflect-reflect-match calibration procedure with a ceramic impedance standard substrate.

A. EM Simulations

In this section, the full-wave EM simulations based on the method of moment were performed to design the feeding net-works. As shown in Fig. 3, two two-port microstrip geometries were simulated: shunt microstrips on a silicon substrate and on a ground shield. In practice, the interconnect scalability would be degraded by improper parasitic deembedding [8], and therefore, here, the interconnect length of the thru dummy was set to about 300 μm to mitigate the parasitic effects as well as save the chip area. Fig. 3(a) and (b) shows the simulated characteristic impedances as a function of frequency for un-shielded and substrate-un-shielded shunt microstrips, respectively. The line length and line width were held constant at 300 and 6 μm, respectively, and the line separation (S) was altered from 5 to 100 μm. As the line separation increases, the impedance of the unshielded shunt microstrips becomes lower because of

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Fig. 3. EM-simulated characteristic impedance versus frequency for different guided wave structures. (a) Shunt microstrips without shielding. (b) Shunt microstrips with shielding.

the increasing of the effective line width, while the substrate-shielded ones show approximately identical impedance. We found that the parasitic effects, which come from the EM cou-pling between each microstrip and substrate networks, can be reduced by using the ground shielding. These results indicate that the shunt microstrips can be divided into isolated two-port networks by the use of the ground shielding and careful design of the microstrip geometry. Here, a line separation of 7.5 μm was adopted according to the transistor size and arrangement.

Based on the aforementioned findings, we can efficiently reproduce and deembed the parasitics of the shielded feeding networks with arbitrary line length and number of lines.

B. Microwave Measurements

Fig. 4 shows the layout of the fabricated modeling test keys and dummy structures for the industry-standard open-short deembedding [2] and the proposed method. In this paper, a two-conductor thru is selected to mitigate the step-discontinuity effects of the pad-to-interconnect junction and to generate the interconnect parasitics. Fig. 5 compares the characteristic im-pedances calculated based on (7) to that measured from the thru dummies with various numbers of lines (N = 1, 2, 4, and 8). The return loss and insertion loss of the thru dummies obtained from measurements and calculations are also shown in Fig. 6 for comparison. It can be seen that the calculations match well with the measurements, and it can be proved that only

Fig. 4. Layout of the on-wafer MOSFET test structures and deembedding structures for the open-short method [2] and proposed method.

Fig. 5. Measured and calculated (N = 2) characteristic impedance versus frequency for thru dummy structures with different numbers of lines (N = 1, 2, 4, and 8). The pad parasitics of thru dummies are removed.

Fig. 6. Measured and calculated (N = 2) return loss and insertion loss versus frequency for thru dummy structures with different numbers of lines (N = 1, 2, 4, and 8). The pad parasitics of thru dummies are removed.

one thru dummy would be required. Fig. 7 shows the two-port S-parameters of the MOSFET test fixtures with various multiplier factors (M = 1, 2, 4, and 8) biased at VGS= 1.2 V

and VDS= 1.2 V. These results are deembedded using the

open-short method and the proposed one. As we can see, the results obtained from the two different methods are in excellent agreement over the entire frequency range. Fig. 8(a)–(f) shows some figures of merit such as voltage gain Gu, current

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Fig. 7. Deembedded S-parameters of the fixtured MOSFETs with different multiplier factors (M = 1, 2, 4, and 8) biased at VGS= VDS= 1.2 V. (a) S11.

(b) S12. (c) S21. (d) S22.

gain H21, maximum stable gain M SG, transconductance gm,

gate–drain capacitance Cgd, gate–source capacitance Cgs, and

output resistance Rds. These results also show negligible

differ-ences in transistor characteristics and extracted model param-eters [16] between these two methods. As shown in Figs. 5 and 8, one potential risk is that the interconnection of a different number of lines influences the extracted characteristics, par-ticularly when the number of lines increases. This is because the parasitics of interconnection between shunt microctrips contribute to the extracted transmission-line parameters, and these effects should also be taken into account to improve the

accuracy of the proposed method. As a result, the proposed geometry-scalable deembedding methodology can be used to accurately extract the intrinsic device characteristics.

Typically, the conventional deembedding methods employ more than two dummy structures [2]–[7] for each DUT, and thus, the chip area for modeling test keys is considerable. The geometry-scalable method can reduce the chip area and charac-terization time to less than one-third (33%) of the conventional ones since only two dummy structures are needed for all DUTs on a wafer. In addition, the proposed method can be applied to characterize various devices, such as varactor, resistor, BJT,

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Fig. 8. Deembedded transistor characteristics and extracted model parameters of the fixtured MOSFETs with different multiplier factors (M = 1, 2, 4, and 8) biased at VGS= VDS= 1.2 V. (a) Voltage gain Gu. (b) Current gain H21and maximum stable gain M SG. (c) Transconductance gm. (d) Gate–drain

capac-itance Cgd. (e) Gate–source capacitance Cgs. (f) Output resistance Rds.

MIM capacitor, etc., and its noise deembedding procedure can be constructed based on the studies in [17] and [18].

IV. CONCLUSION

In this paper, a systematic parasitic deembedding method for two-port on-wafer MOSFET characterization has been pre-sented and verified. The proposed deembedding method based on the transmission-line theory and microwave network analy-sis employs only two substrate-shielded dummy structures to replicate and deembed the external parasitic networks of the fixtured MOSFETs over the whole wafer. Both the interconnect scalability and the deembedding accuracy of the proposed method are validated up to 30 GHz. The deembedded results

substantiate that the proposed method is accurate, area efficient, and time saving for evaluating the intrinsic characteristics of silicon-based devices.

REFERENCES

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Bipolar Circuits Technol. Meeting, Sep. 1987, pp. 70–73.

[2] M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, “An improved de-embedding technique for on-wafer high-frequency charac-terization,” in Proc. IEEE Bipolar Circuits Technol. Meeting, Sep. 1991, pp. 188–191.

[3] H. Cho and D. E. Burk, “A three-step method for the de-embedding of high-frequency S-parameter measurements,” IEEE Trans. Electron

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Jun. 2004, pp. 1237–1240.

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Theory Tech., vol. 55, no. 9, pp. 1813–1823, Sep. 2007.

[10] T. E. Kolding, “Shield-based microwave on-wafer device measurements,”

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[11] M.-H. Cho, C.-S. Chiu, G.-W. Huang, Y.-M. Teng, L.-H. Chang, K.-M. Chen, and W.-L. Chen, “A fully-scalable de-embedding method for on-wafer S-parameter characterization of CMOS RF/microwave de-vices,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2005, pp. 303–306.

[12] M.-H. Cho, G.-W. Huang, L.-K. Wu, C.-S. Chiu, Y.-H. Wang, K.-M. Chen, H.-C. Tseng, and T.-L. Hsu, “A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp. 2926–2934, Sep. 2005.

[13] C. Gupta and A. Gopinath, “Equivalent circuit capacitance of microstrip step change in width,” IEEE Trans. Microw. Theory Tech., vol. MTT-25, no. 10, pp. 819–822, Oct. 1977.

[14] G. Gonzalez, Microwave Transistor Amplifiers: Analysis and Design, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1997, ch. 1.

[15] W. R. Eisenstadt and Y. Eo, “S-parameter-based IC interconnect trans-mission line characterization,” IEEE Trans. Compon., Hybrids, Manuf.

Technol., vol. 15, no. 4, pp. 483–490, Aug. 1992.

[16] D. Lovelace, J. Costa, and N. Camilleri, “Extracting small-signal model parameters of silicon MOSFET transistors,” in Proc. IEEE MTT-S Int.

Microw. Symp. Dig., May 1994, pp. 865–868.

[17] H. Hillbrand and P. H. Russer, “An efficient method for computer aided noise analysis of linear amplifier networks,” IEEE Trans. Circuits Syst., vol. CAS-23, no. 4, pp. 235–238, Apr. 1976.

[18] M.-H. Cho, G.-W. Huang, Y.-H. Wang, and L.-K. Wu, “A scalable noise de-embedding technique for on-wafer microwave device characteriza-tion,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 10, pp. 649–651, Oct. 2005.

Ming-Hsiang Cho (S’06–M’08) was born in

Kaohsiung, Taiwan, in 1976. He received the M.S. and Ph.D. degrees in communication engineering from the National Chiao Tung University, Hsinchu, Taiwan, in 2001 and 2008, respectively.

From 2002 to 2006, he was with the National Nano Device Laboratories, Hsinchu, working on wafer-level device characterization and RFIC testing. Since 2006, he has been a Staff Engineer with the ATD Modeling Division, United Microelectronics Corporation, Hsinchu, working on RFCMOS tech-nology development and characterization. He has authored or coauthored over 40 journals and conference papers. His current research interests include the design of passive and active microwave components, antenna theory and applications, microwave measurement techniques, and device characterization.

Dr. Cho is a member of Phi Tau Phi.

An-Sam Peng was born in Hsinchu, Taiwan, in

1976. He received the B.S. degree in electronics engineering from Feng Chia University, Taichung, Taiwan, in 1999, and the M.S. degree in electrical engineering from the National Chung Hsing Univer-sity, Taichung, Taiwan, in 2001.

He is currently a Staff Engineer with the ATD Modeling Division, United Microelectronics Corpo-ration, Hsinchu. He is also with the Department of Communication Engineering, National Chiao Tung University, Hsinchu. His current research interests focus on noise figure characterization and RF device modeling.

Lin-Kun Wu (S’81–M’86) was born in Hsinchu,

Taiwan, in 1958. He received the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Kansas, Lawrence, in 1982 and 1985, respectively.

From November 1985 to December 1987, he was a Postdoctoral Research Associate with the Center for Research Inc., University of Kansas, where he was involved with microwave remote sensing and computational electromagnetics. Since 1988, he has been with the Department of Communication Engi-neering, National Chiao Tung University, Hsinchu, where he is currently a Professor. His current research interests include computational electromagnet-ics, biological effects and medical applications of electromagnetic energy, and electromagnetic compatibility.

Chune-Sin Yeh was born in Hsinchu, Taiwan. He

received the B.S. degree in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, and the Ph.D. degree in electrical engineer-ing from the University of Florida, Gainesville.

Since July 2005, he has been with the ATD Model-ing Division, United Microelectronics Corporation, Hsinchu. Previously, he was with the United Micro-electronics Corporation, the National Semiconduc-tor, BTA Technology, Celestry, and Cadence, all in the area of technology CAD (TCAD) and TCAD-related tools and consulting service business operation.

高性能晶片電感器與變壓器之設計、特性分析與應用(II)

行政院國家科學委員會專題研究計畫 成果報告