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A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail

8-bit Successive Approximation ADC

Hao-Chiao Hong, Member, IEEE, and Guo-Ming Lee

Abstract—An 8-bit successive approximation (SA)

analog-to-digital converter (ADC) in 0.18 m CMOS dedicated for en-ergy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 W in the test, corresponding to a figure of merit of 65 fJ/conversion-step.

Index Terms—ADC, energy efficient, low power, low supply

voltage, W design, successive approximation.

I. INTRODUCTION

M

ANY energy-limited applications such as wireless sensor networks, biometrics, and portable amusement demand the energy-efficient analog-to-digital converter (ADC) to extend the duration of the system powered by the battery. The energy-efficient feature requests the ADC design to be not only low power but also bandwidth effective.

Power saving can be achieved in many aspects. At architec-ture level, different ADC architecarchitec-tures consume different power for the same specification. The successive approximation (SA) ADC exhibits the lowest power reported in literature due to its minimal active analog circuit requirement [1]–[9].

At circuit level, decreasing the supply voltage is an effective way to realize a low power design. The power of digital cir-cuits directly benefits from supply voltage reduction. However, the low supply voltage makes the analog circuit design more difficult. For instance, when the sum of the absolute value of the pMOS’s threshold voltage and that of the nMOS is larger than the supply voltage, conventional analog switches made of transmission gates may not be fully turned on as they are under a higher supply voltage. The MOSFETs expected to be turned on may now have extremely poor conductances [10] and would limit the bandwidth of the circuits. In addition, some useful de-sign techniques such as cascoding and gain-boosting may not be applicable because of the limited signal swing. The low power requirement further sets the restriction that the circuit design should be as simple as possible.

Manuscript received January 1, 2007; revised May 9, 2007. This work was supported by the National Science Council, Taiwan, R.O.C. under Grants NSC-94-2215-E-009-081 and NSC-94-2215-E-009-056.

The authors are with the Department of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan 300, R.O.C., (e-mail: hchong@cn.nctu.edu.tw).

Digital Object Identifier 10.1109/JSSC.2007.905237

For example, the conventional 8-bit charge redistribution based SA ADC in [11] is not suitable for low voltage op-eration. Its input signal connects to all the capacitors of the digital-to-analog converter (DAC) through ten analog switches. When the input signal level is around half the supply voltage, these switches may have very poor on-resistances at a low supply voltage and thus limits the input bandwidth of the ADC. The switch connecting to the common-mode reference will suffer from the same issue as well since is usually designated to be a half of the supply voltage.

The poor on-resistances of the switches can be improved by using the process providing low threshold voltage (low- ) devices, but such a process is more complex and leads to a higher fabrication cost. The low- MOSFETs also have higher leakage currents that will distort the analog samples. Limiting the input signal swing is another solution [7]. Circuit design techniques can also be used to address the issue. Switched-opamp [10], [12], [13] and clock boosting [14]–[16] have been shown to be suitable for low supply voltage design. Yet a boot-strapped switch costs more power than a conventional one. To save the power, the number of the bootstrapped switches should be minimized.

In this paper, an energy-efficient 8-bit SA ADC is demon-strated. This ADC achieves a wide effective resolution band-width (ERBW) by applying only one bootstrapped switch. Consequently, the desired low power characteristic is preserved without compromise of its bandwidth. Section II explains the design of the SA ADC and analyzes its power consumption. Measurement results are presented in Section III. Some appli-cation dependent approaches to further save the energy are also discussed. Finally, Section IV draws our conclusions.

II. DESIGN OF THESUCCESSIVEAPPROXIMATIONADC Although a fully-differential circuit structure achieves better common-mode noise rejection and less distortion, it consumes more power. Since our SA ADC design targets on a moderate resolution, all the circuit components except for the comparator possess single-ended structures in order to reduce the power.

Fig. 1 shows the schematic of the proposed SA ADC, which is similar to that of [7]. The fundamental building blocks of the SA ADC consist of a track-and-hold (T/H) circuit, a charge-re-distribution DAC, a comparator, and a successive approximation register (SAR).

The ADC has three power supplies: , , and . They are designed to be the same voltage . supplies the digital circuits while is the full-scale refer-ence voltage of the ADC. The rest of the circuits are powered by . The SA ADC eliminates the need for any reference 0018-9200/$25.00 © 2007 IEEE

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2162 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 10, OCTOBER 2007

Fig. 1. Schematic of the proposed 8-bit SA ADC.

voltage different from , such as the in [11], thus saving the power of the extra voltage generator.

All switches in the DAC part connect to either or the ground . Consequently, these switches do not suffer from a poor on-resistance. In fact, there is only one analog switch in this architecture that may be non-fully turned on. This partic-ular switch is located in the T/H block and directly connected to the input signal. The control signal of the switch is boosted to achieve an appropriate on-resistance at a supply voltage of 0.9 V. Compared with the conventional SA ADC in [11], the number of the required bootstrapped switches is reduced from eleven to one. As a result, the proposed ADC has lower circuit complexity as well as lower power dissipation.

A. Track-and-Hold Circuit

The T/H circuit is shown in Fig. 2. It is made of a sampling ca-pacitor and a simple nMOS driven by the boosted driver to achieve both low power and a wide bandwidth. The boosted driver produces a periodical output switching

between and the ground . is due to

the charge sharing between the boosting capacitor and the parasitic capacitance at the node. An additional pMOS is added to alleviate the errors induced by the charge injection and clock feed-through impairments of . also helps enhance the on-conductance between and when is close to . Both and have small sizes in order to achieve the following advantages. First, the impair-ments induced by them are mitigated. Second, their leakage currents, which will distort the sampled input, become less. Fi-nally, the power overhead is reduced. In fact, the power of the boosted switch is negligible since the boosted driver operates at one ninth the clock frequency, as will be explained later. Even though both MOSFETs have small aspect ratios, the boosting technique keeps the on-resistance of the sampling switch small. Fig. 3 shows the simulated on-resistance of the boosted switch.

The T/H circuit has a bandwidth of , where is the on-resistance of the boosted switch. Since is set to only 1.28 pF to mitigate the driving issue of the preceding signal source, the bandwidth of the T/H stage is estimated to be larger than 62 MHz.

Fig. 2. Schematic of the T/H stage.

Fig. 3. On-resistance of the boosted switch.

B. Comparator With a Rail-to-Rail Input Range

The low supply voltage inherently limits the maximum input signal swing of an ADC, and thus may lead to a poor peak signal-to-noise ratio (SNR). To overcome the signal swing

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Fig. 4. Schematic of the comparator with a rail-to-rail common-mode input range.

reduction at a low supply voltage, a rail-to-rail input range is required in the SA ADC design. A comparator with a rail-to-rail common-mode input range is substantial for this design in order to achieve the required rail-to-rail input swing.

The proposed comparator is shown in Fig. 4. The p- and n-type differential pairs connected in a parallel manner are used to extend the common-mode input range to the power rails. It is the only block with a fully-differential structure in order to reject the common-mode disturbances induced by the T/H and DAC. Both differential pairs convert the differential input voltages into differential output currents. These currents are summed together respectively to drive the regenerative load formed by and . The two successive inverters with a designated threshold voltage amplify the complementary outputs to their full rail-to-rail logic levels. Additional resetting nMOS and are added to reduce the hysteresis effect in order to speed up the comparator.

The tail currents of the differential pairs are designed to en-sure that both differential pairs still produce sufficiently large differential output currents to drive the regenerative loads in the worst condition. The whole comparator including the bias cir-cuits consumes only 0.6 W at 0.9 V.

The major issue of using such a rail-to-rail comparator is that the offset of the comparator may depend on the common-mode input. Let be defined as the upper-limit voltage such that the pMOS differential pair will not generate sufficiently large currents to trigger the regenerative load within a clock period once the common-mode input is higher than it. Similarly, let the lower-limit voltage be defined such that the nMOS differ-ential pair will not affect the outputs of the comparator if the common-mode input is below . Then, the offset of the com-parator will be dominated by the mismatch of the pMOS differ-ential pair when the common-mode input is between and . Meanwhile, the nMOS differential pair and the following current mirrors determine the offset if the common-mode input is within the range from to . Between the the two ranges discussed above, the mismatches of both differential circuits contribute to the offset of the comparator. This common-mode input dependency of the offset may result in distortion.

The threshold voltage mismatch and the peripheral mismatch of the MOSFETs were shown to be two dominant factors that in-duce the input-referred offset voltage of a differential pair [17]. The square standard deviation of the threshold voltage is known to be

(1) where and represent the effective channel width and length of the MOSFETs and is a process dependent constant. On the other hand, the randomness of the peripherals of the MOS-FETs is a less concern if both and are large enough. Hence, the areas of the MOSFETs, , , and to , were signed to be large so as to address the common-mode input de-pendent offset. In addition, their layouts were carefully done by using a common-centroid style and adding dummy devices.

C. Successive Approximation Register

The SAR generates the necessary control commands based on the successive approximation algorithm to control the T/H, comparator, and DAC [18]. Nine clock cycles are required to complete a single conversion. Cycle one is the reset cycle. It is needed for avoiding the possible residual charge of the DAC induced by the clock feed-through and charge injection of the switches during the conversion of the preceding sample. The input is also sampled in this cycle. This arrangement provides the T/H stage with a full clock cycle to track the input signal. The ADC conducts bit-cycling in the rest of the cycles to produce the final digital outputs to .

The SAR is built with standard CMOS logic gates. It is well known that the power consumption of such a CMOS logic cir-cuit is approximately

(2) where represents the clock frequency, denotes the total capacitance of the circuit nodes, and is the switching activity factor depending on the analog input . In order to

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2164 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 10, OCTOBER 2007

save the digital power, all MOSFETs of the digital gates were designed to be as small as possible to minimize .

D. Digital-to-Analog Converter

The DAC is implemented by using a binary-weighted switched-capacitor array as shown in Fig. 1. to are the control signals generated by the SAR to control the switches of the DAC, and

(3) In the above equation, is the capacitance of the unit capacitor in the switched-capacitor array. Each of the switches connecting to is implemented by a simple PMOS, and a single nMOS is used for the switches connecting to .

The major power of the DAC comes from the reference voltage supply. The power consumption of the reference voltage supply when an input is applied can be calculated according to

(4)

where denotes the period to convert a sample and repre-sents the total charge that supplies to the DAC during the

th cycle.

Let represent the total capacitance of the DAC. In the first cycle, all capacitors of the DAC are reset. There is no charge transferred from to the DAC, thus . During the second cycle, connects to while the connections of the rest of the capacitors are not changed. As a result,

(5) In the third cycle, connects to and connects to

. The output of the DAC at the end of this cycle is (6) supplies and with the necessary charge. If , transfers no charge to . Otherwise, the charge stored in in the second cycle will be shared with . Therefore, the total charge supplied by in the third cycle is written as

(7) Similar deductions lead to a more general expression:

(8) and

(9) Let be zero. By combining (8), (9), and (5) with (4), and then applying (3) to the result, the power consumption of the reference voltage supply is derived to be

(10) According to (10), the unit capacitor in the DAC should be kept as small as possible to save the power dissipation. In prac-tice, the smallest capacitance of is determined by considering the thermal noise, capacitor matching, and the design rules. For our design, the smallest capacitance is not limited by the KT/C thermal noise. Consequently, is set to the minimum value, which is about 24 fF, according to the design rules. The binary-weighted capacitor array is laid out based on a common-cen-troid placement. Each of the non-unit capacitors, to , is made of plural unit capacitors in parallel for a better matching characteristic.

The switches in the passive DAC are designed to achieve a bandwidth larger than 42 MHz, so as not to limit the bandwidth of the ADC.

III. MEASUREMENTRESULTS

The SA ADC was fabricated in a 0.18 m 1P6M CMOS process through the service of National Chip Implementation Center (CIC), Taiwan. Fig. 5 shows the micrograph of the test chip. The test chip occupies 0.70 mm and the active area of the SA ADC is 0.062 mm . In the following measurements, the supply voltages , , and were shorted together on the evaluation board and set to 0.9 V. The amplitude and fre-quency of the test stimulus and the clock frefre-quency were set to , 1.001 kHz, and 1.8 MHz, respectively, unless otherwise noticed.

A. Static Performance

The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the SA ADC are shown in Fig. 6. The INL is in the range of LSB whereas the DNL is within

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Fig. 5. Micrograph of the test chip.

Fig. 6. Measured DNL and INL plots of the SA ADC.

Although it is not possible to directly measure the offset of the comparator versus the common-mode input in our design, the INL plot can provide some information about the impair-ment. The static test can be regarded as if an input distorted by the common-mode input dependent offset were applied to an offset-free ADC. Hence, the common-mode input dependent offset will lead to a slow bending in the INL plot. According to Fig. 6, no significant INL bending was found. It indicates that the offset variation does not degrade the performance of the ADC under test.

B. Dynamic Performance

Fig. 7 plots the measured signal-to-noise-and-distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SA ADC with respect to the stimulus amplitude. The results prove that the ADC indeed has a rail-to-rail input range. Besides, the ADC achieves a peak SNDR and a peak SFDR of 47.4 and 58.9 dB, respectively. It corresponds to an effective number of bit (ENOB) of 7.58 bits.

Fig. 8 shows the measured output spectrum of the ADC where the ADC achieves its peak SNDR. 8192 samples were used to

Fig. 7. Measured SNDR and SFDR versus stimulus amplitude.

Fig. 8. Measured output spectrum of the SA ADC with the00:056 dBFS, 1.001 kHz sinusoidal input.

derive the spectrum. The main spurious tone is the fourth har-monic of the stimulus, showing that the ADC is somewhat asym-metric at the test setup. Nevertheless, the fourth harmonic is only 58.9 dBFS and thus has no significant impact on the SNDR performance of the ADC. The harmonic distortions of the ADC as functions of the input frequency are shown in Fig. 9.

Fig. 10 illustrates the measurement results of the ADC’s SNDR and SFDR versus different stimulus frequencies and amplitudes. The SNDR does not degrade even with the stimulus frequency close to 100 kHz. In other words, this ADC achieves an ERBW no less than its Nyquist bandwidth and the ERBW is independent of the stimulus amplitude.

Fig. 11 depicts the measured SNDR versus the system clock frequency with the 1 kHz sinusoidal stimulus to test the max-imum operation speed of the ADC. The ADC is shown to be able to operate at a clock frequency as high as 2 MHz without no-table SNDR degradation. Further increasing the clock rate will

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2166 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 10, OCTOBER 2007

Fig. 9. Measured harmonic distortion versus input frequency.

Fig. 10. Measured SNDR versus input frequency at different stimulus ampli-tudes.

degrade the performance of the ADC. Since the bandwidths of the T/H and the DAC are all much higher than 2 MHz, it is the comparator that limits the bandwidth of the ADC design.

C. Power Consumption

The total power dissipation of the SA ADC is 2.47 W at 0.9 V and a 200 kS/s output rate. The averaged powers

of , , and are 0.83, 0.98, and 0.66 W,

respectively. The power may be further reduced depending on applications. Fig. 12 displays the measured power consumption of every power supply versus the clock frequency. The same 1-kHz sinusoidal stimulus was applied to the tests.

Most of the analog power is consumed by the comparator. Due to the constant current sources in the comparator, the analog power of the ADC is almost a constant regardless the clock fre-quency. For higher output rate applications, the only necessary modification of this design is increasing the bias currents of the comparator.

Fig. 11. Measured SNDR and SFDR versus clock frequency with the 1 kHz stimulus.

Fig. 12. Measured power versus clock frequency with the 1-kHz stimulus. TABLE I

SUMMARY OF THESA ADC

According to (2) and (10), both powers of and are dynamic powers. They will automatically scale with the clock frequency. Fig. 12 shows that these two powers are

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in-TABLE II

COMPARISON OF THEPROPOSEDSA ADC WITH THESTATE-OF-THE-ARTRESULTS

Fig. 13. Dynamic power versus output code.

deed proportional to the clock frequency. At an output rate of 11.1 kS/s, the ADC totally consumes only 0.78 W.

Reducing the supply voltage is another effective way to fur-ther cut down the power for low output rate applications. Our measurement results show that this ADC has a satisfactory per-formance when operating at a supply voltage as low as 0.83 V and an output rate of 111.1 kS/s. Compared with the dynamic power when the ADC operates at 0.9 V and the same output rate, about 15% of the dynamic power can be saved. Table I lists the summary of the SA ADC design.

Equations (2) and (10) also reveal that the powers of both voltage supplies are input signal dependent. The measured powers of both voltage supplies are plotted in Fig. 13. There is no clear trend for the power of with respect to the output code because of the randomness of . On the other hand, the measured reference voltage power and the estimated values made by (10) show good agreement. Both results demonstrate that a larger output code consumes less reference voltage power. It leads to a possible power saving scenario: the reference voltage power can be saved by adjusting the common-mode voltage of the input, if the input excursion

of the ADC in a certain application is known to be less than the full-scale input range of the ADC. For example, given a sinu-soidal input whose amplitude is 0.32 V, is estimated to be 0.68 W when the common-mode voltage of the input is set to 0.45 V. By adjusting the common-mode voltage to 0.58 V, the reference voltage power is reduced to 0.58 W. About 15% of the reference voltage power can be saved, provided that shifting the common-mode voltage of the input costs no additional power.

D. Comparison With Other Approaches

The figure of merit (FOM) used in [19], [20] is referred here to compare the proposed ADC design with other state-of-the-art works. The FOM is defined as

(11) This FOM is from an energy perspective, instead of a power point of view. It dictates the energy required to accomplish an effective conversion step of an ADC. Table II lists the compar-ison results. The proposed SA ADC spends the least energy for an effective analog-to-digital conversion step. In addition, it achieves the widest ERBW among these sub-1 V, W ADC designs.

IV. CONCLUSION

An energy-effective 8-bit SA ADC is presented. At 0.9 V and an output rate of 200 kS/s, the SA ADC achieves an ERBW up to the Nyquist bandwidth, a peak SNDR of 47.4 dB, a peak SFDR of 58.9 dB, and a rail-to-rail input range. From the energy per-spective, the proposed ADC achieves an FOM of 65 sion-step. The FOM of the ADC is enhanced to be 60 fJ/conver-sion-step at 0.83 V and a 111.1 kS/s output rate.

ACKNOWLEDGMENT

The authors would like to express their gratitude to the National Chip Implementation Center, Taiwan, R.O.C., for implementing the test chips.

REFERENCES

[1] K. Hadidi, V. S. Tso, and G. C. Temes, “An 8-b 1.3-MHz successive-approximation A/D converter,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 880–885, Jun. 1990.

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[2] S. Mortezapour and E. K. F. Lee, “A 1-V, 8-bit successive approxima-tion ADC in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 642–646, Apr. 2000.

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Elec-tronics, Circuits and Systems, Sep. 2001, pp. 859–862.

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Conf. (ISSCC) Dig. Tech. Papers, 2006, pp. 822–831.

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J. Solid-State Circuits, vol. 29, no. 8, pp. 936–942, Aug. 1994.

[13] T. Yoshida, M. Sasaki, and A. Iwata, “A 1-V supply successive approx-imation ADC with rail-to-rail input voltage range,” in Proc. IEEE Int.

Symp. Circuits and Systems (ISCAS), 2005, pp. 192–195.

[14] T. Cho and P. R. Gray, “A 10b, 20 Msamples/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166–172, Mar. 1995.

[15] S. Rabii and B. A. Wooley, “A 1.8-V digital-audio sigma-delta mod-ulator in 0.8-m CMOS,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 783–796, Jun. 1997.

[16] C. J. B. Fayomi, G. W. Roberts, and M. Sawan, “A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18m CMOS technology,” in Proc. IEEE Int. Symp. Circuits and

Systems (ISCAS), 2001, pp. 460–463.

[17] S. J. Lovett, M. Welten, A. Mathewson, and B. Mason, “Optimizing MOS transistor mismatch,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 147–150, Jan. 1998.

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Papers, 2003, pp. 322–323.

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Hao-Chiao Hong (S’98–M’04) received the B.S.,

M.S., and Ph.D. degrees in electrical engineering from National Tsing-Hua University, Taiwan, R.O.C., in 1990, 1992, and 2003, respectively.

From 1997 to 2001, he was with Taiwan Semi-conductor Manufacturing Company (TSMC) where he developed mixed-signal IPs for customers and process vehicles. He joined Intellectual Property Library Company, HsinChu, Taiwan, as the Senior Manager of the Analog IP Department in August 2001. He has been with the Department of Elec-trical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, since February 2004, where he is currently an Assistant Professor. His main research interests include the design-for-testability (DFT) and built-in self-test (BIST) techniques for mixed-signal systems and high-performance mixed-signal circuit design.

Dr. Hong currently serves as Executive Secretary for the Mixed-Signal and RF Consortium. He is a member of VTTF.

Guo-Ming Lee received the B.S. degree from the

De-partment of Electrical Engineering, National Chung Cheng University, Taiwan, R.O.C., in 2004, and the M.S. degree from the Department of Electrical and Control Engineering, National Chiao Tung Univer-sity, Taiwan, in 2006.

His research interest is in mixed-signal circuit de-sign.

數據

Fig. 1. Schematic of the proposed 8-bit SA ADC.
Fig. 4. Schematic of the comparator with a rail-to-rail common-mode input range.
Fig. 10. Measured SNDR versus input frequency at different stimulus ampli- ampli-tudes.
TABLE II

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