A new lossy substrate model for accurate RF CMOS noise extraction and simulation with frequency and bias dependence

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n-MOSFETs. A substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1–18-GHz regime, which did not follow the typical thermal noise theory. Good match with the measured -parameters, -param-eters, and noise parameters before deembedding proves the lossy substrate model. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate deembedding using circuit simulation. The accuracy has been justified by good agreement in

terms of -parameters, and under a wide range of

bias conditions and operating frequencies. Both channel thermal noise and resistance induced excess noises have been implemented in simulation. A white noise factor extracted to be higher than 2 3 accounts for the velocity saturation and channel length modu-lation effects. The extracted intrinsicNF_minas low as 0.6–0.7 dB at 10 GHz indicates the advantages of super-100 GHz offered by the sub-100-nm multifinger n-MOSFETs. The frequency de-pendence of noise resistance suggests the bulk RC coupling induced excess channel thermal noise apparent in 1–10-GHz regime. The study provides useful guideline for low noise and low power design by using sub-100-nm RF CMOS technology.

Index Terms—Lossy substrate, noise, RF CMOS, RLC network.

I. INTRODUCTION

T

HE aggressive scaling of CMOS technology to sub-100-nm scale can offer high-speed devices with cutoff frequency and maximum oscillation frequency approaching 100 GHz and above [1]–[7]. It is really a very attractive solution for low cost RF integrated circuit (IC) devel-opment. However, the tradeoff among various RF performance parameters such as bandwidth, linearity, gain, power, and noise becomes an important reality to be considered. Potentially, we gain higher and but suffer some loss in the noise performance. The challenge arises to look for an optimized design, which can achieve maximum gain and maintain the noise at minimum. Another challenge coming out to trigger our motivation of this study is how to measure the truly intrinsic noise of sub-100-nm devices precisely. Currently it remains a Manuscript received December 31, 2005; revised July 25, 2006. This work was supported in part by the National Science Council under Grant 94-2220-E009-018 and Grant 94-2215-E009-050.

The authors are with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan 30010, R.O.C. (e-mail: jcguo@mail. nctu.edu.tw).

Color versions of Figs. 3, 5(a), 6, 10, and 14 are available online at http:// ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2006.883654

for low-noise RF circuit design. The difficulty stems from the strong dependence of RF noise on the parasitic and coupling effect associated with the gate, transmission line, pads, and lossy substrate, etc. [8]–[10] Gate-induced thermal noise is one of well-known noise sources, and multifinger structures are generally used to reduce the gate resistance . Gate leakage current effect on thermal noise is one more special concern for sub-100-nm MOSFETs with ultra-thin gate oxide. Comparison of calculated dc gate leakage and ac gate displacement currents was performed to verify this effect. It indicates that for an 80-nm n-MOSFET with , the dc gate leakage current at 1.0 V is around 0.64 nA/ m, while the ac gate displacement current can reach as high as 7.22–72.2 A/ m corresponding to frequencies of 1–10 GHz. The obvious dominance of the ac current over the dc leakage current by more than four orders suggests that the gate leakage current effect can be neglected under high frequency in the gigahertz regime.

In our study, more important excess noises were identified to be originated from lossy substrate, lossy pad, and transmis-sion-line coupling effects. The lossy Si substrate generally leads to an extremely complicated RLC effect and there is no effective deembedding method to solve it for intrinsic noise extraction. Regarding the lossy pad rendered through pad-to-substrate coupling, the impact is increasing for miniaturized devices and particularly worse for sub-100-nm Si RF CMOS. It is due to the fact that the pad capacitance may overwhelm the intrinsic devices, which we want to measure and model. The increasing pad impact suggests that the RF pad layout is very critical. As for the transmission-line effect, which is becoming significant with increasing frequency, e.g., above 10 GHz and approaching 20 GHz in this study, it is no longer negligible. All the mentioned excess noises dramatically increase with device size scaling and reveal nonlinear frequency dependence. The observation cannot be explained by typical thermal noise theory and formulas in which linear frequency response was predicted [11], [12]. One of the most popular solutions is the noise correlation matrix method, which is based on circuit theory, developed by Haus and Adler in 1959 [13] and the noise correlation matrix derived by Hillbrand and Russer in 1976 [14]. However, the complicated matrices calculation sometimes suffers fluctuation at a very low noise level and poor accuracy in frequency dependence. Previous study on pad deembedding using the matrices correlation method revealed dramatic fluctuation of (minimum noise figure) in a 0018-9480/$20.00 © 2006 IEEE

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Fig. 1. Flowchart of RF MOSFET characterization and modeling.

wide range of 0.5–1.5 dB. Smoothing was reported to get rea-sonable frequency dependence [9]. A three-step deembedding method incorporating open, short, and through was proposed to deembed the excess noise, which is caused by pad and trans-mission line. However, two specially designed dummy pads for through deembedding of two ports are necessary. Besides, matrices correlation method cannot be avoided for intrinsic noise extraction [15]. A new transmission-line deembedding method was published to extract the lossy substrate and lossy pad effect. In this way, the intrinsic for sub-100-nm n-MOSFETs can be simulated accurately [10]. However, fre-quency-dependent substrate resistance was assumed to account for the deviation from the generally used Fukui formula [12] and match the nonlinear frequency response of measured . Besides, the bias and drain current dependence was not extensively verified. The drain current dependence of noise is quite important for low-power and low-noise RF CMOS design.

In recent research, we proposed an enhanced lossy substrate model in which the complicated frequency dependence can be precisely described by the RLC network without assump-tion of frequency-dependent elements [16]. A good match with measured over a wide range of drain currents ( – mA) and frequencies (1–18 GHz) has been achieved. As for the extraction of intrinsic by using sim-ulation, improvement of the existing BSIM3 model accuracy in terms of mobility, gate capacitance, and the employment of parasitic resistances such as and with correct values becomes a challenge. In this study, calibration

Fig. 2. 80-nm n-MOSFET (N = 6; 18; 36; 72) (a) Measured NF (1–18 GHz). (b) R extracted from Z-parameters and (C ; C ; C ) extracted fromY -parameter.

Fig. 3. Open pad. (a) 2-D layout with two signal pads and four ground pads. Two signal pads are used for connection to gate and drain of the MOSFET. Four ground pad are connected together through M1. (b) 3-D structure to show the metal layers for signal (S) and ground (G) pads and interconnection to DUT.

on the existing gate capacitance model, correct extraction of , and deployment in the original intrinsic MOSFET scheme have been done. Through the mentioned process, a good match is achieved in terms of -pa-rameters, and over a wide range of drain currents and frequencies and the accuracy of the calculated can be justified. The intrinsic as low as 0.6–0.7 dB at 10 GHz calculated by the calibrated intrinsic MOSFET model reveals the advantage offered by the sub-100-nm devices.

II. DEVICECHARACTERIZATION ANDMODELINGFLOW To study the nanoscale CMOS scaling effect on speed and noise, sub-100-nm n-MOSFETs of gate length at 80 nm are used. Multifinger structures are employed to reduce the gate resistance generated RF noise. The finger width is fixed at 4 m and finger numbers of 6, 18, 36, and 72

are designed for study of performance optimization. Fig. 1 illustrates the flowchart to explain the device characterization and modeling procedure for this study. At first, I–V character-ization was done to extract the transconductance that is

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Fig. 4. RLC network circuits for open pads and lossy substrate coupled through the pad. (a) Gate pad as port-1. (b) Drain pad as port-2.

a key parameter governing and noise figure. The gate bias corresponding to the maximum for various was around 0.7 V and drain bias was fixed at V. Following the bias conditions and dc characterization, -pa-rameters were measured by using an Agilent vector network analyzer up to 40 GHz. Open and short deembedding were done on the measured two-port -parameters to extract the intrinsic -, -, and -parameters. Subsequently, C–V model parameters can be extracted from -parameters and can be determined from -parameters. -parameters of the in-trinsic MOSFETs are used to extract the electrodes’ and

such as and . The intrinsic MOSFET

incorporating the parasitic as extracted is adopted by ADS simulation to do I–V and C–V model parameter extrac-tion and optimizaextrac-tion simultaneously. The accuracy of the intrinsic MOSFET model has been extensively verified and validated by a good match with the measurement in terms of

and etc.

The noise parameters ( and or ) were

measured by an ATN-NP5B system to 18 GHz for fixed at maximum and under varying to cover a wide range of drain current ( – mA) for a fixed frequency at 2.4, 5.8, and 10 GHz. A through (thru) line was proposed in the equivalent circuit to emulate the transmission line between the RF probe pad and gate terminal. In this study, we proposed a new RLC equivalent circuit to model the lossy substrate, lossy pad, and thru line’s parasitic to deembed their effect on RF noise. The details of RLC equivalent-circuit development for modeling the lossy substrate and lossy pad will be described in Section III. A full-circuit model can be obtained by integrating the intrinsic MOSFET with the pad capacitance, the substrate and thru line related resistance ( ), capacitance ( ), and induc-tance ( ), which represent the lossy pad and lossy substrate. The extrinsic noise can then be simulated by using the full-cir-cuit model. Through tuning of RLC parameters, the best fit to the measured -parameters and noise parameters can be achieved and the full circuit can be finalized corresponding to optimized

RLC parameters. The intrinsic MOSFET noise can be extracted

by simulation through the lossy substrate and lossy pad deem-bedding from the validated full circuit.

III. SUBSTRATE RLC CIRCUIT NETWORK ANDEXTRINSICNOISEMODEL

Fig. 2(a) shows the measured for 80-nm n-MOSFETs

with various finger numbers and biased

under maximum . The RF noise without deembedding decreases remarkably with increasing . The lower asso-ciated with larger may account for part of the contribution, but cannot explain the dramatic difference up to 4.0 dB be-tween and in 10–18 GHz. Fig. 2(b) indicates extracted from -parameters and the gate capacitances from -parameters after deembedding for various . Obviously, varying plays a tradeoff between and , and the resultant is kept at similar level of around 90–105 GHz for and . It suggests that is not the major factor responsible for the dramatic difference in measured . Regarding the abnormally high measured from the smallest device with , the increasing weighting factor played by the lossy substrate is considered as the major cause.

A. Open Pad Layout, Three-Dimensional (3-D) Structure, and Equivalent RLC Parameter-Extraction Method

Fig. 3(a) and (b) exhibits the open pad layout and 3-D struc-ture used for -parameter deembedding. Herein, metal lines used for connection to the device-under-test (DUT) are stacked from top metal, i.e., M8 and terminated at M3. All DUTs of different share an identical open pad for deembedding. Due to this fact, a single set of RLC equivalent-circuit and model parameters were extracted. This set of RLC model parameters suitable for the open pad will be used as initial values for fur-ther tuning and optimization. Through the optimization, a new set of RLC model parameters can be achieved to fit the full cir-cuit with the DUT (MOSFET) linked with the pads. The details of extraction and optimization flow have been shown in Fig. 1.

Fig. 4(a) and (b) illustrates the equivalent circuits and model parameters that we propose to simulate the lossy substrate ef-fect through gate and drain pads referring to two-dimensional (2-D) layout and 3-D structure in Fig. 3 for clear images. The proposed RLC network incorporating pad capacitance ,

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lossy substrate ( , and ), and transmission line will be connected to the gate and drain terminals of the intrinsic MOSFET. The transmission-line body is con-sisted of series resistor and inductor . The shunt

RLC path to ground at gate/drain pads is used to simulate the

lossy pad and lossy substrate effect. The existence of both ca-pacitive and inductive impedances, i.e., and in series with , is quite different from the conventionally used simple shunt RC circuit. This new RLC network was created to accu-rately capture the unique frequency response associated with the lossy substrate. The RLC network has been extensively verified by comparison with measured results in terms of -parameters and -parameters of open pads for both the gate (port-1) and drain (port-2), respectively.

Fig. 5(a) illustrates the schematic block diagram derived by circuit analysis theory to extract the circuit elements

( and ). Fig. 5(b) indicates the

model parameter-extraction flow based on the circuit analysis. The pad capacitance fF is a physical param-eter calculated by layout and process paramparam-eters rather than from extraction. is around five times the intrinsic gate

capacitance of the smallest device with

, which is around 40 fF in Fig. 2(b). Note that the first run of model parameters extracted based on approximation valid under relatively low/high frequencies (0.2/40 GHz in this study) just serve as the initial guess for further optimization. The optimization was done by using ADS simulation to get the best fit to - and -parameters for both open pads and full circuit (pads and intrinsic MOSFET together).

Fig. 6(a) and (b) shows the good agreement in the Smith chart between simulation and measurement for open pad’s (gate pad as port-1) and (drain pad as port-2). Fig. 7(a)–(d) re-veals the good fit to measured (magnitude and phase) and for the gate pad in which the effect of and can be obviously identified. Fig. 8(a)–(d) indicates the good match with measured (magnitude and phase) and corre-sponding to drain pads where the and effect is revisited and confirmed.

All the results are demonstrated over a wide range of frequen-cies up to 40 GHz. The match simultaneously achieved for both - and -parameters manifests the fact that the proposed RLC network is accurate to account for the lossy substrate effect. Our study suggests that and are three key parameters playing the role to capture the lossy substrate’s feature over wide bandwidth. is the primary element responsible for the phase and magnitude deviation in the full frequency range, as well as the nonlinear frequency response of and . On the other hand, reveals an increasing effect in higher frequencies. The nonlinear frequency response of or introduced by accounts for the nonconstant

ca-pacitance as extracted by and . The

ob-vious two-slope curvature results in larger effective capacitance in lower frequencies corresponding to larger slope and appar-ently smaller effective capacitance at higher frequencies due to much reduced slope to near saturation.

Fig. 5. (a) Schematic block diagram derived by circuit analysis theory to extract the circuit elements. (b) RLC circuit model parameter extraction flow.

B. Lossy Substrate RLC Parameter Extraction for Full Circuit Adopting MOSFET and Pads

Fig. 9 depicts the full-circuit model for sub-100-nm MOSFETs in which the RLC networks representing the lossy pads, lossy substrate, and transmission line are linked with the

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Fig. 6. Smith chart of measuredS and S for open pad (symbol) and the good match by simulation (line) using the proposed RLC circuit. (a)S for gate pad as port-1. (b)S for drain pad as port-1.

intrinsic MOSFET (dashed box). For accurate RF modeling, the body of the intrinsic MOSFET is obviously different from the conventional one limited for dc modeling. The parasitic and associated with MOSFET’s electrodes [gate–source–drain (G/S/D)] were extracted by the -parameter method [17], [18].

The extracted and for various are

tabulated and attached with Fig. 9.

The layout of the intrinsic MOSFET in this study is a three-terminal configuration with source and bulk shorted internally. is a series resistance of metal interconnection to the source and accounts for the substrate network resistance. rep-resents the inductance of the metal line connecting the source/ bulk common node to the ground pad, which is required for accurate high-frequency impedance simulation. Note that the lossy substrate RLC parameters were retuned and optimized through the flow shown in Fig. 1 for every MOSFET of var-ious to fit -parameter, -parameter, and noise parameter before deembedding simultaneously. The difference from the pad-only RLC parameters in Fig. 4 and obvious dependence on account for the additional lossy substrate effect introduced through M3–M1 of the MOSFET, which cannot be extracted from the conventional open-pad deembedding structure with the

Fig. 7. MeasuredS and Im(Y ) for gate pad (symbol) and good fit by sim-ulation (line) using the proposed RLC circuit. (a)S (magnitude and phase) andC effect. (b) Im(Y ) and C effect. (c) S (magnitude and phase) and L effect. (d) Im(Y ) and L effect.

Fig. 8. MeasuredS and Im(Y ) for drain pad (symbol) and good fit by simulation (line) using the proposed RLC circuit. (a)S (magnitude and phase) andC effect. (b) Im(Y ) and C effect. (c) S (magnitude and phase) and L effect. (d) Im(Y ) and L effect.

interconnection line terminated at M3, as mentioned. It is inter-esting to note that the larger led to an increase of all three ca-pacitance parameters, i.e., and , while a decrease of representing an effective substrate resistance.

The full circuit for noise simulation contains the MOSFET body incorporating G/S/D electrodes’ and as the intrinsic part and the proposed RLC networks at two ports as the extrinsic part. Besides the generally considered thermal noises, which are classified as the intrinsic drain current noise, intrinsic in-duced gate noise, and gate resistance inin-duced excess noise to gate and drain terminals [19], pads’ capacitive coupling and sub-strate loss are identified as more important factors responsible for the abnormally worse RF noise measured without effective deembedding. The associated with the intrinsic MOSFET represents the distributed gate and channel resistances. For de-vices with a large finger number, e.g., is effectively reduced and may become not negligible in determining . Regarding ultrahigh frequency, e.g., up to 40 GHz in this study, inductive impedance represented by and be-come important parasitic elements, which can be evidenced by

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Fig. 9. Full-circuit model with intrinsic MOSFET integrated with RLC network in which theR, L, and C parasitics account for lossy pad (C ), lossy substrate (R ; L ; C , and C ), and transmission line (R ; L ) connected to the gate and drain of the MOSFET. RLC model parameters are listed in the table.

-parameters to be shown as follows. To certify the effective-ness and accuracy of the proposed RLC network for lossy pads and lossy substrate, the -parameter was calculated by using the full-circuit schematics in Fig. 9 as the fundamental characteris-tics to be verified.

Fig. 10(a) and (b) demonstrates a good match in and (0.2–40 GHz) between the measurement and simulation for 80-nm n-MOSFETs with various . It is revealed in the Smith chart that and are translated from capacitive to induc-tive mode under higher frequencies for the devices with large finger number . It indicates the dominance of para-sitic inductance existing in the transmission line connected to the gate electrode and pad ( and ). This result suggests the gate transmission-line effect plays an increasingly impor-tant role in high frequencies. The accuracy of the lossy substrate model by the proposed RLC network, as well as the effect played by and , are further verified by magnitude and phase of

and and before deembedding for

de-vices with various .

Regarding the input characteristics at port-1, Fig. 11(a)–(d) indicates a good fit to the measured (magnitude and phase) and for . Figs. 12(a)–(d) and 13(a)–(d)

demon-strate a good match with the measured and for and , respectively. Again, plays a major role in fitting - and -parameters of the full circuit structure in whole frequency range (0.2–40 GHz), while is becoming important in higher frequencies. As for the output feature at port-2, a good fit to the measured (magnitude and phase) and over a full frequency range (0.2–40 GHz) are shown in Figs. 14–16 corresponding to and , respectively. and effects are exactly consistent with those identified for port-1. The accuracy of the lossy substrate model is fur-ther justified by a good match with the measured up to 18 GHz, as shown in Fig. 17(a)–(d) for all .

The RLC network can predict the nonlinear frequency response of extrinsic noise and the excessively high precisely. The nonlinear frequency response is originated from two obviously different slopes associated with lower and higher frequencies, respectively. In the lower frequency region, the effective substrate impedance is dominated by the capacitive mode represented by . As for getting into a higher frequency region, the substrate impedance is dominated by the resistive mode represented by . The capacitive mode substrate impedance will enhance the frequency dependence

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Fig. 10. Smith chart of measuredS and S for full circuit with intrinsic MOSFET and pads. Good match achieved by simulation using the proposed

RLC network. (a)S . (b) S . n-MOSFETs with N = 6; 18; 36; 72, and

op-erating frequencies of 0.2–40 GHz. The symbol is the measured data and the line is the simulation.

Fig. 11. 80-nm n-MOSFET withN = 6. Measured S and Im(Y ) before deembedding (symbol) and good fit by simulation (line) using the proposed full-circuit schematics. (a)S (magnitude and phase) and C effect. (b) Im(Y ) andC effect. (c) S (magnitude and phase) and L effect. (d) Im(Y ) and L effect.

of , which is the major cause responsible for the larger slope w.r.t. frequency and excessively high emerging in the low-frequency region. The effect on is clearly

identified by comparison of two curves simulated with and without illustrated in Fig. 17. plays a minor effect on

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Fig. 17. Comparison of extrinsicNF between measurement (symbol) and simulation (line) for 80-nm n-MOSFETs. (a)N = 6. (b) N = 18. (c) N = 36. (d)N = 72. C effect is demonstrated for each device.

(not shown), but it is an essential element for a precise match with the - and -parameters, particularly to achieve correct phase in high frequencies, as shown previously.

Fig. 18. Measured and modeled extrinsicNF versus drain currentI for 80-nm n-MOSFETs. (a)N = 6. (b) N = 18. (c) N = 36. (d) N = 72 under three frequencies, 2.4, 5.8, and 10 GHz.

Regarding the drain current dependence of , which is important for low power and low noise design, the comparison of extrinsic noise has been done among various , as well as that between measurement and modeling employing the pro-posed lossy substrate network. Fig. 18 demonstrate good agree-ment achieved between the measured and modeled under a wide range of drain currents ( – mA) and fre-quencies (2.4, 5.8, 10 GHz) for all 80-nm n-MOSFETs

. The move of minimum toward higher for larger suggests the penalty of higher power by using larger devices. However, lossy substrate induced excess noise should be deembedded to get the truly intrinsic for rigorous study and correct conclusion. One more concern about the large drain current reaching 100 mA for the largest device

is the potential impact of the dc I–V heating effect. Verification by pulse I–V measurement indicates a lack of negative resistance in the saturation region and suggests a negligible heating effect. Actually, degradation of saturation current and was identified for the multifinger devices with larger and can be modeled by an drop effect due to source series resistance induced voltage drop.

IV. LOSSYSUBSTRATEDEEMBEDDING ANDINTRINSIC NOISEEXTRACTION ANDMODELING

A. Intrinsic MOSFET Model for DC and AC Simulation

Through the extensive verification on the proposed lossy substrate model and the justification of accuracy in terms of the -parameter, -parameter, and noise parameters, the lossy substrate deembedding can be done easily and precisely by removing the substrate RLC network from the full-circuit schematics in Fig. 9. The intrinsic noise can be calculated by using ADS simulation after the lossy substrate deembedding. Before that, the intrinsic MOSFET model accuracy needs to be verified in terms of I–V, C–V, and - and -parameters through dc and high-frequency small-signal simulation. Fig. 19 presents a good match between the model and measurement in

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Fig. 19. Comparison of measured and modeled: (a)I versus V and (b) g versusV for 80-nm n-MOSFETs with N = 6; 18; 36; 72.

Fig. 20. Comparison of measured and modeledIm(Y ) after deembedding for 80-nm n-MOSFETs under frequencies of 1, 2.4, 5.8, and 10 GHz. (a)N = 6. (b)N = 18. (c) N = 36. (d) N = 72.

terms of versus and versus under V

for all 80-nm n-MOSFETs with different finger numbers . This good match validates the calibrated intrinsic model in aspect of mobility, short channel effects (SCEs), and parasitic resistances and . Regarding the intrinsic of major concern, , and are three primary parameters accompanying with to determine

and . The model accuracy in terms of was

generally verified by comparison of -parameters based on the

equations of and .

Good agreement with the measurement in terms of , shown in Fig. 20 and in Fig. 21, justifies the intrinsic model with calibrated gate capacitances.

One more rigorous verification on the intrinsic model accu-racy was done by comparison of extracted from the unit current gain, i.e., . Fig. 22 reveals a promisingly good match with the measured . The deviation is maintained below 5% for all devices with various . The optimized up to 110 GHz corresponding to suggests the tradeoff among , and other parasitics.

Fig. 21. Comparison of measured and modeledIm(Y ) after deembedding for 80-nm n-MOSFETs under frequencies of 1, 2.4, 5.8, and 10 GHz. (a)N = 6. (b)N = 18. (c) N = 36. (d) N = 72.

Fig. 22. Measured and modeledf versus I (V = 1:0 V) for 80-nm n-MOSFETs. (a)N = 6. (b) N = 18. (c) N = 36. (d) N = 72.

B. Intrinsic MOSFET Noise Model and Simulation

The accuracy of and gate capacitances is a prerequisite to predict , and accurate extraction of parasitic resistances at four terminals such as and is essential to calculate with sufficient precision. Re-garding the thermal noise models for MOSFET high-frequency noise simulation, channel thermal noise and resistance induced excess noise are considered in this study. Channel thermal noise, also known as intrinsic drain current noise , was calculated by a modified Van der Ziel’s model [20] given by (1)–(3) in which velocity saturation and channel length modu-lation (CLM) effects were implemented through the calibrated BSIM3 I–V model. Concerning the resistance induced excess noises, additional drain current noise and excess gate current noise were calculated by (4) and (5), respectively [19]. Note that the intrinsic induced gate noise is considered negligible for an 80-nm MOSFET in the operating frequency up to 18 GHz [21]. Fig. 23(a) indicates the simulated intrinsic drain current noise free from and full drain current noise including resistance induced excess noise for all . Fig. 23(b) presents the additional drain current noise calculated by simulation and the comparison with the analytical model given by (4). Fig. 23(c) shows the white noise

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Fig. 23. Drain current noise and gate current noise simulated for 80-nm intrinsic n-MOSFETs after lossy substrate deembedding. Frequencies in 1–18 GHz and biases underV = 1:0 V, V . (a) Intrinsic and full drain current noiseS andS . (b) Additional drain current noise 1S due to ter-minal resistances calculated by simulation and model1S = 4k T R g . (c) White noise factor for intrinsic drain current noise. (d) Resistance induced excess gate noise 1S calculated by simulation and model 1S = 4k T R (!C ) for all N (6, 18, 36, 72).

factor calculated by from simulation,

which reveals values of much larger than the long-channel value of 2/3 and decreasing with frequency from around 1.7 to 1.2 corresponding to 1–18 GHz. Fig. 23(d) indicates the resistance induced excess gate current noise from simulation and comparison with the model given by (5), which matches

dependence quite well as follows:

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body effect coefficient (3) (4) (5) The intrinsic model with the above enhancement can sim-ulate the bias and frequency dependence of noise resistance , as shown in Fig. 24. The bias dependence of trans-lated to dependence for various can be approximated by the generally used analytical model

[11] in which the minimum of corresponds to the maximum of . However, the frequency dependence of cannot be explained by the mentioned model, and bulk resis-tance induced potential fluctuation was proposed as the possible mechanism [22]. Both the measured extrinsic and simulated intrinsic reflected the frequency dependence, and the re-sults suggest the bulk (substrate) RC coupling effect apparent in 1–10-GHz range. The deployment of and junction capac-itances in the intrinsic MOSFET model accounts for the decrease of with increasing frequency.

After extensive justification of the intrinsic MOSFET model in terms of mobility, SCE, and parasitic RC , etc., intrinsic of major interest are calculated by the calibrated intrinsic model.

Fig. 24. IntrinsicR versus I (V = 1:0 V) for 80-nm n-MOSFETs after lossy substrate deembedding.f = 2:4; 5:8; 10 GHz. (a) N = 6. (b) N = 18. (c)N = 36. (d) N = 72.

Fig. 25. IntrinsicNF versusI for 80-nm n-MOSFETs after lossy substrate deembedding.f = 2:4; 5:8; 10 GHz. (a) N = 6. (b) N = 18. (c) N = 36. (d)N = 72.

The results for various under increasing and frequencies are shown in Fig. 25. The minimum of can be pushed to as low as 0.6–0.7 dB at 10 GHz. Super-100-GHz realized by the 80-nm n-MOSFET makes the major contribution and the trend matches with the Fukui formula [12]. The drain current responsible for the minimal is another major concern for low power. This study suggests the penalty of higher suffered by the bigger device using a larger or the total width to achieve the same level of . Of course, consideration of impedance matching in a real circuit is not covered in this scope.

V. CONCLUSION

An accurate lossy substrate model has been developed based on deployment of a new RLC network for sub-100-nm RF MOSFETs. The accuracy is justified by a good match with the measured -parameters, -parameters, and noise parameters before deembedding. The accuracy of the intrinsic MOSFET model has been proven by good agreement in terms

of and under a wide range of

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support.

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Jyh-Chyurn Guo received the B.S.E.E. and M.S.E.E. degrees from National Tsing-Hua Univer-sity (NTHU), Taiwan, R.O.C., in 1982 and 1984, respectively, and the Ph.D. degree in electronics engineering from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, R.O.C., in 1994.

She previously worked within the semiconductor industry with a major focus on device design and very large scale integration (VLSI) technology de-velopment for approximately 19 years. In 1984, she joined the Electronic Research and Service Organi-zation (ERSO)/Industry Technology Research Institute (ITRI), where she was engaged in semiconductor integrated circuit technologies within a broad scope covering high-voltage high-power, submicrometer projects and high-speed static random access memory (SRAM) technologies, etc. From 1994 to 1998, she was with the Macronix International Corporation, where she was engaged in high-density and low-power Flash memory technology development. In 1998, she joined the Vanguard International Semiconductor Corporation, where she was a Device Department Manager for advanced dynamic random access memory (DRAM) device technology development. In 2000, she joined the Taiwan Semiconductor Manufacturing Company (TSMC), where she was a Program Manager in charge of 0.1-m logic CMOS front-end-of-line (FEOL) technology, high-performance-analog (HPA) and RF CMOS technology development. In 2003, she joined NCTU, as an Associate Professor with the Department of Electronics Engineering. She has authored or coauthored over 40 technical papers. She holds 12 international patents in her professional field. Her current research interests cover RF CMOS and high-performance analog device design and modeling, novel nonvolatile memory technology, and device integration technology for system-on-chip (SOC).

Yi-Min Lin was born in Taipei, Taiwan, R.O.C., in 1981. He received the B.S. degree in electrophysics and M.S. degree in electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, R.O.C., in 2004 and 2006, respectively.

His current research interests focus on RF device modeling and characterization.