A new I-V model considering the impact-ionization effect initiated by the DIGBL current for the intrinsic n-channel poly-Si TFT's

A New

Model Considering the

Impact-Ionization Effect Initiated by the DIGBL

Current for the Intrinsic n-Channel Poly-Si TFT’s

Hsin-Li Chen,

Student Member, IEEE

and Ching-Yuan Wu,

Member, IEEE

Abstract—Considering the impact-ionization mechanism

occur-ring in the high drain-bias (V_DS) regime, a new I0V model considering the impact-ionization effect initiated by the drain-induced-grain-barrier-lowering (DIGBL) current has been estab-lished for the intrinsic n-channel poly-Si TFT. The simulation results with considering the developed impact-ionization current model are in excellent agreement with the experimental output characteristics of the intrinsic n-channel poly-Si TFT with the mask-gate length ranging from 5m to 40 m. In resolving the physical parameters and their underlying operation mechanisms including the grain-barrier height, DIGBL current, and impact-ionization current, the developedI0V model will be beneficial to further understand the underlying physics of the intrinsic poly-Si TFT.

Index Terms— DIGBL, impact-ionization,I–V model, poly-Si

TFT.

I. INTRODUCTION

R

ECENTLY, the intrinsic poly-Si thin-film transistors (poly-Si TFT’s) by low-temperature process have received wide investigation for their important applications in the active-matrix liquid crystal display (AMLCD) [1], [2] and the static random-access-memories (SRAM’s) [3]. To optimize the design of the poly-Si TFT’s with high-performance, they should have a reliable analyzer based on the physical mechanisms to correlate the dependence of the electrical characteristics on the fabrication conditions.

The kink effect for the drain-source current of the poly-Si TFT operating in the high drain-bias regime has been investigated by several works [4]–[8]. With the aid of two-dimensional (2-D) numerical simulation, the nature of the kink effect had been identified to be due to the impact-ionization mechanism in the high-field regime near the drain for the intrinsic poly-Si TFT [4]–[7]. On the other hand, when the drain voltage is applied, the grain-barrier heights for both sides of the grain boundary become asymmetric and the grain-barrier height for the side near the source junction will be lower than the side near the drain junction. As a consequence, there will be extra carriers injecting from the source junction Manuscript received May 25, 1998; revised September 14, 1998. This work was supported by the National Science Council, Taiwan, R.O..C, under Contract NSC87-2215-E009-050. The review of this paper was arranged by Editor M. Fukuma.

The authors are with Advanced Semiconductor Device Research Laboratory and Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.

Publisher Item Identifier S 0018-9383(99)02389-8.

through the side with lower grain barrier into the channel, resulting in the increased current. This phenomenon is so called the drain-induced-grain-barrier-lowering (DIGBL) ef-fect [8]. Based upon the interfacial-layer thermionic-diffusion model [9], and considering the DIGBL effect, Lin et al. [8] had analytically simulated the kink output characteristics of the doped Si TFT’s. However, for the intrinsic poly-Si TFT, the doping concentration in the grain must be set to zero. The derivations by assuming the quadratic potential distribution for the grain with finite depletion depth to solve the 2-D Poisson’s equation [8] will be invalid due to the zero doping concentration and the grain-barrier height model will break down. Therefore, the grain-barrier height model and the model developed in [8] cannot be used to simulate the grain-barrier height and the characteristics of the intrinsic poly-Si TFT. To solve this problem, the existence of the trap states in the grain is assumed and the grain-barrier height model for the intrinsic poly-Si TFT can then be established [10]. Moreover, the potential distribution across the depletion region in the grain, which is important to calculate the diffusion velocity of carriers in the model based on the interfacial-layer thermionic-diffusion theory, can be easily obtained. However, with the model considering only the DIGBL effect using the grain-barrier height model for the intrinsic poly-Si TFT, there is still a large deviation in the kink regime of the output curves between the results of simulation and measurement for the intrinsic poly-Si TFT. This implies that, in addition to the DIGBL effect, the impact-ionization should be considered for simulating the kink output characteristics of the intrinsic poly-Si TFT.

In this paper, we will propose an analytical model to simulate the impact-ionization mechanism initiated by the DIGBL current for the intrinsic n-channel poly-Si TFT’s. It will be shown later that the physical meaning for the kink output characteristics is clearly represented in our model and good agreement is obtained between the simulated and experimental results.

II. THEIMPACT-IONIZATION CURRENT MODEL Based on the interfacial-layer thermionic-diffusion theory [9], the model considering the DIGBL effect can be written as

(1)

where is the current of the DIGBL effect; is the channel width (length); is the effective mobility and is given as

(2)

with and is the density of

carriers (free electrons for n-channel device) per area; and (3) where

diffusion velocity of electrons across the depletion region;

effective thermal velocity of electrons across the grain boundary along the channel direction; inverse thermal voltage ;

grain size;

depletion width in the -th grain;

grain-barrier height considering the DIGBL effect. The grain-barrier height model, considering the DIGBL effect for the intrinsic poly-Si TFT, can be expressed as [10]

(4) where

thickness of the active poly-Si film; capacitance of the gate oxide per area; density of the grain boundary states; intrinsic threshold voltage.

From the derivation of the grain-barrier height model for the intrinsic poly-Si TFT [10], it is shown that the potential variation accounting for the formation of the grain-barrier is governed by the reduced Poisson equation

(5) Within the turn-on regime and the space-charge

term , is equal to , which is just

the average concentration of the induced free-carriers with positive sign; that is, the space-charge in the depletion region is composed of the induced free-carriers for the intrinsic poly-Si TFT. The depletion approximation for the diffusion velocity should then be expressed as

(6) where is the thermal voltage. Note that to calculate the dif-fusion velocity, the dopant concentration used for the poly-Si resistor has been replaced by the concentration of the induced free-carriers for the intrinsic poly-Si TFT. The concentration of the induced free-carriers is calculated with the Fermi energy in the strong inversion condition and the extracted grain-barrier height [10]. Based on the Boltzmann approximation

Fig. 1. Cross-sectional view of the saturation region in the intrinsic n-channel poly-SiTFT, which illustrates the multiplication process of the impact-ionization mechanism initiated by the DIGBL current, where  represents the Si atom-site; the arrow with the dashed line shows the path of the generated electron-hole pair.

is expressed by

(7) This identification of the space-charge is important for cor-rectly calculating the diffusion velocity of the free-carriers in the intrinsic poly-Si TFT and enables the extraction of the electrical parameters with reasonable values. Moreover, this conclusion is valid for both the intrinsic and doped poly-Si TFT’s.

When the intrinsic poly-Si TFT operates in the kink regime, the impact-ionization of carriers occurs in the saturation region in which the lateral electric field is greater than the critical electric field . The impact-ionization mechanism in the saturation region is illustrated in Fig. 1, where is the beginning position for the occurrence of impact-ionization at which the electric field is equal to the critical value and the potential is equal to the saturation voltage . As a first-order approximation, we assume that the critical electric fields for both the saturation of the carrier-velocity [8] and the beginning of the impact-ionization are reached in the same point of channel with the potential being . is the length of the saturation region and is the position of the drain junction.

The generated electrons together with the initiating ones from the DIGBL current form the total drain-source current

(8) where is the drain-source current composed solely of the electron flow, considering both the DIGBL effect and the impact-ionization mechanism, which will proceed to initiate the next impact-ionization when moving toward the drain; and is the impact-ionization current initiated by the electrons. The generated holes move toward the source without initiating impact-ionization. Naturally, the generation rate of the electron-hole pairs by the impact-ionization mechanism will be proportional to the quantity of the initiating electron flow. From the discussion above, we can obtain the differential equation for the variation of the impact-ionization current in

the saturation region as follows:

(9) where is the impact-ionization rate of the electrons; and is the incremental space along the channel. It is worthy to note that the DIGBL current participates in the impact-ionization mechanism but is constant over the whole channel region. This is because in the saturation region, the DIGBL current only contributes to initiate the impact-ionization current, and the impact-impact-ionization current will not contribute to the DIGBL current. That is, the electrons of the generated electron-hole pairs are not added to the DIGBL current. The DIGBL current is completely calculated by (1). The variation of the drain-source current then comes mainly from that of the impact-ionization current and is expressed by (10) With (8), (9) and (10), we can obtain

(11) In fact, (11) is a one-dimensional continuity equation of the drain-source current, which accounts for the impact-ionization mechanism of the intrinsic poly-Si TFT. By integrating both sides of (11) over the saturation region with the associated boundary conditions

and

(12) and with the integration variable exchanged from the space to the potential , we can obtain

(13)

where is the lateral electric field. Thus, the total drain-source current considering both the DIGBL effect and the impact-ionization mechanism is obtained as follows

(14)

in which the impact-ionization rate can be derived based on the probability argument and is explicitly expressed as follows [11]

(15) where is the threshold energy of impact-ionization, which is times the bandgap energy of Si; is the optical-phonon mean free path of carriers in Si. Equation (14) intuitively shows that the drain-source current of the intrinsic poly-Si TFT with the kink effect comes from the mechanism of the

Fig. 2. Diagram illustrating the current continuity for the impact-ionization mechanism initiated by the DIGBL current in the intrinsic n-channel poly-Si TFT.

impact-ionization initiated by the DIGBL current through the multiplication operation.

The physical meaning of the boundary conditions for the drain-source current within the saturation region can be identi-fied to be consistent with the current-continuity condition and is illustrated in Fig. 2, in which it illustrates the continuity for the mechanism of the impact-ionization initiated by the DIGBL current. Initially, the electrons injecting from the source junction move toward the drain through the transport mechanisms combined in series, by surmounting the grain barriers, diffusing across the depletion regions near the grain boundaries, and drifting through the inversion regions between the depletion regions. This is the transport mechanism de-scribed by the interfacial-layer thermionic-diffusion model [9]. The DIGBL current is then formed and is constant over the whole channel region. Within the kink regime of the intrinsic poly-Si TFT, the electrons, from the DIGBL current, enter into the saturation region and perform the multiplication-ionization, as illustrated in Fig. 1. Additional electron-hole pairs are generated and the variation of is governed by (11). The electrons and holes generated are separated by the high electric field and move toward the drain and source junction, respectively. When reaching the drain junction, the electron flows, coming both from the DIGBL current and the impact-ionization process, form the total drain-source current . On the other hand, it is important to note that the holes generated are not included as the initiating carriers for the impact-ionization mechanism, because the avalanche-breakdown of the intrinsic poly-Si TFT’s is not observed from the experimental results. Thus, at the beginning of the saturation region where the electric field is of the critical value, is equal to the DIGBL current and is the only source for initiating the impact-ionization mechanism. The DIGBL current and the hole flow generated from the impact-ionization mechanism, form the total drain-source current in the region near the source. Because the extra amount of electrons is equal to that of the holes through the electron-hole pairs generated and the DIGBL current is constant over the whole channel region, the total drain-source current obtained is then constant over the whole channel. Thus, the two boundary conditions considered for the drain-source current are reasonable, and are also the key points in determining whether the construction of this new analytical model is successful or not.

It is noted here that compared with the threshold energy of times Si bandgap for triggering the impact-ionization

process, the effect of carrier recombination is a high-order effect in determining the transport mechanism of the poly-Si TFT operating in the kink regime. Within the physical picture constructed in our model, the mechanism of carrier recombination occurs when the holes generated by the impact-ionization process move toward the source junction [4]. The electrons generated flow out the drain junction to be measured and meanwhile, extra electrons in addition to those due to the DIGBL current inject from the source junction into the channel and recombine with these holes. The impact-ionization current is then formed. Due to the high concentration of the trap states at the grain boundaries with energy level centering in the bandgap, the recombination rate of carriers is large enough that the recombination effect will not be the limiting process in determining the impact-ionization current. Although the mechanism of carrier recombination takes part in the formation of the impact-ionization current, the kink effect is dominated by the mechanism of the impact-ionization initiated by the DIGBL current.

To calculate the total drain-source current , the dis-tribution of the electric field in the saturation region should be known first. The quasi-2-D method had been used to solve the Poisson’s equation in the saturation region and shown that in this region, the distribution of the electric field is nonlinearly dependent on the position [12]. On the other hand, (14) possesses the freedom for the electric field in that any reasonable distribution of the electric field is allowable to be substituted into (14) to calculate the impact-ionization current, provided that the parameters used should be reasonably accepted. For simplicity, we will propose an empirical formula for the nonlinear dependence of the electric field on the position and then on the potential. It is given as follows:

(16) where is the critical electric field accounting for the oc-currence of the impact-ionization within the saturation region; and is an empirical parameter indicating the nonlinear degree for the dependence of the electric field on the potential (and position). It is obvious that when is zero, the electric field is equal to the critical electric field over the whole saturation region and is given by

(17) Substituting (17) into (14) with some mathematical manipula-tion, the drain-source current is obtained as follows:

(18) Equation (18) will be appropriate for the simulation of the long-channel poly-Si TFT’s because the weak dependence of the electric field on the position is considered. As is equal to unity, the electric field is given as

(19)

and the drain-source current can be obtained as

(20)

where the integral in the exponent can not be obtained ana-lytically and should be calculated with numerical integration. The calculation for this numerical integration is time-efficient as expected. Equation (20) will be appropriate for the simulation of the short-channel poly-Si TFT’s because the strong dependence of the electric field on the position is considered.

III. RESULTS AND DISCUSSION

In order to test the validity of the analytical model developed above, the intrinsic n-channel poly-Si TFT’s were fabricated. An intrinsic poly-Si film of 1000 ˚A was deposited onto a 1500

˚

A TEOS buffer layer grown on glass by the LPCVD method and the intrinsic poly-Si film was annealed at 1000 C for 4 h. After being patterned into individual devices, a 700 ˚A TEOS gate oxide was grown, and then another LPCVD poly-Si film of 2500 ˚A was deposited. The source, the drain, and the poly-Si gate were simultaneously implanted using phosphorus ions at 80 keV with a dose of cm . It is noted that the poly-Si channel is undoped.

A. Parameter Extraction

The procedure of the parameter extraction can be divided into three steps. First, using the curve of versus obtained from the Arrhenius plot of the drain-source current, the grain size, the density of the grain boundary states and the Fermi energy in the strong inversion condition are extracted with the analytical model of the grain-barrier height and the detail is presented in [10]. Second, based on the accurate modeling of the grain-barrier height with those parameters extracted previously, the parameters for the model of the interfacial-layer thermionic-diffusion current, including the maximum electron mobility in the surface channel , the empirical constant of the surface-roughness scattering , the effective thermal velocity of electrons across the grain boundary and the scattering-limited velocity , are extracted from the transfer curve of the poly-Si TFT operating in the linear regime. After optimization of the transfer curves, the threshold voltage extracted is 1.123 V. Third, the parameters for the DIGBL effect and the impact-ionization current are extracted from the output curves of the poly-Si TFT operating in the high regime. The critical electric field for velocity saturation and the nonlinear factor of the electric field for the DIGBL effect are extracted by fitting the saturation point and the portion of the output curve before the saturation point. The critical electric field for impact-ionization and the nonlinear factor of the electric field in (16) are extracted from the kink-portion of the output curve. It is noted that is much smaller than , as shown in Table I.

TABLE I

PARAMETERSUSED TOSIMULATE THEI0V CHARACTERISTICS

Fig. 3. Transfer curves of the intrinsic n-channel poly-Si TFT shown in both the logarithmic and linear scales.

Fig. 4. Output characteristics of the intrinsic n-channel poly-Si TFT with

W=LM = 20 m/5 m.

B. Characterization

Fig. 3 shows the experimental and simulated transfer curves both with logarithmic and linear scales. Good agreement in the turn-on regime is obtained and the parameters extracted for the interfacial-layer thermionic-diffusion model are reasonable, as listed in Table I for devices with the mask-gate length ranging from 5 m to 40 m. Due to the tilt etching-bias and the source(drain) dopant diffusion into the active poly-Si film, the effective channel length will be less than

Fig. 5. Output characteristics of the intrinsic n-channel poly-Si TFT with

W=LM = 20 m/10 m.

Fig. 6. Output characteristics of the intrinsic n-channel poly-Si TFT with

W=LM = 20 m/20 m.

the mask-gate length. The deviation between and should be more carefully considered in determining the characteristics of the short-channel device. With optimization, the deviation of the effective channel length from the mask-gate length, , is obtained to be 1 m for the test devices used. Only one set of parameters is needed to accurately simulate the transfer characteristics. This consequence confirms the accuracy of the developed model with correctly resolving the physical parameters for the intrinsic poly-Si TFT’s. The discrepancy in the subthreshold regime shown in the plot of logarithmic scale is due to the fact that the real distribution of the grain-boundary states is continuous within the bandgap. In the subthreshold regime, the sweep of the Fermi level over the continuous distribution of the grain-boundary states within the bandgap will result in the smoother variation of the current [6], [13], which is not considered in our model.

Figs. 4–8 show the experimental and simulated output curves and the solid and dashed lines represent the simulation results with and without considering the impact-ionization mechanism, respectively. With considering only the DIGBL effect, there will be large deviation presented in the kink

Fig. 7. Output characteristics of the intrinsic n-channel poly-Si TFT with

W=LM = 20 m/30 m.

Fig. 8. Output characteristics of the intrinsic n-channel poly-Si TFT with

W=LM = 20 m/40 m.

regime between the measured and simulated output curves. On the other hand, by further considering the impact-ionization mechanism in the model, good agreements are obtained in both regimes dominated by the DIGBL effect (low ) and the kink effect (high ). The parameters used for simulation are listed in Table I. It is encouraged that excellent agreement is obtained even for the short-channel device with a mask-gate length of 5 m. From these figures, it is shown that the impact-ionization of the carriers occurs in the high regime for the devices with various channel lengths. The degree of the impact-ionization increases with the decreased channel length, as expected. The nonlinear dependence factor of the electric field, , is zero for the devices with channel lengths being greater than or equal to 10 m. For 5 m mask-gate length, increases to unity. With the optical-phonon mean-free-path of carriers in Si at room temperature being used, the critical electric field for impact-ionization extracted are within 10 V/cm regime, where the impact-ionization process normally occurs. also shows the decreasing dependence on the increased channel length. of a 5- m device being smaller than that of a 10- m one is due to the fact that of a 5- m device is unity and its empirical formula

of the electric field assumes larger magnitude and stronger dependence on the position than those of a 10- m one with being zero. The complicatedly-behaved output characteristics of the intrinsic poly-Si TFT show strong contrast with the compact form of our analytical model for the impact-ionization current initiated by the DIGBL current.

IV. CONCLUSION

A new analytical model considering the impact-ionization mechanism initiated by the drain-induced-grain-barrier-lowering (DIGBL) current for the intrinsic n-channel poly-Si TFT has been established. The output characteristics of the intrinsic n-channel poly-Si TFT with the DIGBL effect and the impact-ionization mechanism in the low and high regimes, respectively, can be well simulated by the new model established. With these physical mechanisms for both the formation of the grain-barrier height and the transport mechanisms being correctly resolved, the model proposed will be able to well characterize the electrical properties of the intrinsic n-channel poly-Si TFT. The accuracy of this model is also supported by the reasonable values of the physical parameters extracted. Therefore, it can serve as a reliable analyzer to correlate the relationship between the fabrication conditions and the electrical characteristics and will be beneficial to further understand the underlying physics of the intrinsic n-channel poly-Si TFT.

REFERENCES

[1] T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, and N. Konishi, “An LCD addressed by a-Si:H TFT’s with peripheral poly-Si TFT circuits,” in IEDM Tech. Dig., 1993, pp. 389–392.

[2] T. Aoyama, K. Ogawa, Y. Mochizuki, and N. Konishi, “Inverse stag-gered poly-Si and amorphous Si double structure TFT’s for LCD panels with peripheral driver circuit integration,” IEEE Trans. Electron Devices, vol. 43, pp. 701–705, May 1996.

[3] S. D. S. Malhi et al., “Characteristics and three-dimensional integration of MOSFET’s in small-grain LPCVD polycrystalline silicon,” IEEE

Trans. Electron Devices, vol. ED-32, pp. 258–281, Feb. 1985.

[4] M. Validinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio, “Floating body effects in polysilicon thin-film transistors,”

IEEE Trans. Electron Devices, vol. 44, pp. 2234–2241, Dec. 1997.

[5] G. A. Armstrong, S. D. Brotherton, and J. R. Ayres, “A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors,” Solid-State Electron., vol. 39, no. 9, pp. 1337–1346, Sept. 1996.

[6] M. Hack, J. G. Shaw, P. G. Lecomber, and M. Willums, “Numerical sim-ulations of amorphous and polycrystalline silicon thin-film transistors,”

Jpn. J. Appl. Phys., vol. 29, no. 12, pp. L2360–L2362, 1990.

[7] S. Yamada, S. Yokoyama, and M. Koyanagi, “Two-dimensional device simulation for polycrystalline silicon thin-film transistor,” Jpn. J. Appl.

Phys., vol. 29, no. 12, pp. L2388–L2391, 1990.

[8] P. S. Lin, J. Y. Guo, and C. Y. Wu, “A quasi-two-dimensional analytical model for the turn-on characteristics of polysilicon thin-film transistors,”

IEEE Trans. Electron Devices, vol. 37, pp. 666–674, Mar. 1990.

[9] C.-Y. Wu and W.-D. Ken, “A new computer-aided simulation model for polycrystalline silicon film resistors,” Solid-State Electron., vol. 26, no. 7, pp. 675–684, 1983.

[10] H. L. Chen and C. Y. Wu, “An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistors,” IEEE

Trans. Electron Devices, vol. 45, pp. 2245–2247, Oct. 1998.

[11] S. Wang, Solid-State Electronics, New York: McGraw-Hill, 1966, p. 359. [12] G.-S. Huang and C.-Y. Wu, “An analytic saturation model for drain and substrate currents of conventional and LDD MOSFET’s,” IEEE Trans.

Electron Devices, vol. ED-37, p. 1667, July 1990.

[13] M. D. Jacunski, M. S. Shur, and M. Hack, “Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFT’s,”

Hsin-Li Chen (S’95) was born in Tainan, Taiwan, R.O.C., on January 2, 1969. He received the B.S. de-gree in electrical engineering from National Tsing-Hua University, Taiwan, in 1991, and is currently pursuing the Ph.D. degree in the Institute of Elec-tronics, National Chiao-Tung University, Hsinchu, Taiwan.

His present research areas focus on the physical modeling and reliability issues of the amorphous and polycrystalline silicon thin-film transistors.

Ching-Yuan Wu (M’72), for a photograph and biography, see this issue, p. 695.