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DC and AC NBTI stresses in pMOSFETs with PE-SiN capping

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DC A

ND

AC NBTI S

TRESSES

I

N

PMOSFET

S

W

ITH

PE-SIN C

APPING

Chia-Yu Lu, Horng-Chih Lin*, Yi-Feng Chang, and Tiao-Yuan Huang

Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 1001 Ta Hsueh Road, Hsinchu, Taiwan 300, R.O.C

I

NTRODUCTION

PMOS negative bias temperature instability (NBTI) is known to be a critical reliability concern and represents one of the major bottlenecks for product lifetime [1-2]. It had also been shown that the device lifetime under dynamic stress could be much longer than that under static stress [3]. Recently, using process technique to induce uniaxial strain in the channel [4-7] has received a lot of attention. However, the NBTI issue of these strained devices has not been carefully addressed. In this work, we investigate the static and dynamic NBTI of pMOSFETs with compressively strained channel.

D

EVICE

F

ABRICATION

PMOSFETs used in this study have an oxide thickness of 3nm, with 150nm-thick poly-SiGe layer as the gate material. Both 100nm-thick SiN capping and TEOS passivation layers were deposited by PECVD. The SiN capping had been shown previously to introduce significant compressive strain to the channel of pMOSFETs [8].

R

ESULTS

A

ND

D

ISCUSSION

The stress from PE-SiN layer was first examined by probing monitor samples deposited on blanket Si wafers. It was confirmed that the stress is compressive in nature, and its magnitude increases monotonically with thickness. The stress is around –95 MPa for 100nm-thick SiN. Figure 1 shows the percentage increase in the drive current of the SiN-capped devices compared to the controls as a function of channel length. It can be seen that enhancement in drive current is observed with the incorporation of SiN capping layer. These observations are consistent with the film stress measurements as well as previous literature reports on compressive SiN capping [4-5]. ID,sat at VDS= -2V, VG- Vth= -2V Channel Length (Pm) 0 1 2 3 4 5 ' ID,s at /ID,s at (% ) 0 5 10 15 20 25 30 35

Figure 2 shows the results of NBTI stress performed at three different gate biases. It can be seen that the threshold voltage shift, 'Vth, is larger for the devices with SiN capping. The shift curves depict a fractional power-law dependence on time ('Vthv tn). The values of the exponent are roughly 0.2 and 0.3 for samples without and with SiN-capping layer, respectively. Increase in interface state density, 'Nit, is mainly responsible for the observed phenomena, as indicated in the figures. It is noted that both 'Vth and 'Nit approach

saturation for devices with SiN capping when NBTI stress time exceeds 1000 sec. This is because nearly all the interfacial Si-H bonds were already broken by then [8]. From our previous study [8], the maximum transconductance also degrades significantly for devices with SiN layer. The above results clearly indicate that the use of PECVD SiN capping may aggravate NBTI, which is related to the higher density of Si-H bonds at the oxide/Si interface. The abundance of hydrogen species originated from the SiN layer where SiH4 and NH3 were used as precursors. Higher strain energy stored in the channel may also play a crucial role in the aggravated degradation process: the energy may help trigger the electrochemical reactions at the interface. This is consistent with the higher exponent value of the power-time dependence for devices with SiN capping.

Figure 3 shows results of dynamic NBTI stress performed on both control and strained devices under two passivation voltage (VP) conditions. 'Vth and 'Nit are found to be larger in the strained devices, similar to the trend observed in static stress case. Due to the saturation effect of 'Nit in strained devices, 'Nit reaches its peak when the stress time exceeds 2000s, as shown in Fig. 3(b). Similar trend, however, is not observed for the peak values of 'Vth, indicating the existence of another major contributor for the NBTI degradation. Some of the results are normalized and shown in Fig. 4. Threshold voltage is largely recovered for the strained devices, as shown in Fig. 4(a). The dependence of recovery in 'Vth on VP indicates the contribution by some charged species. Since the dependence of 'Nit on VP is negligible (Fig. 4(b)), neutralization of trapped holes in the oxide [9] is suspected as the main culprit for the excessive recovery in Vth as VP is increased from 0 to 1 V, as shown in Fig. 4(a). Although 'Nit in strained devices is independent of VP, as shown in Fig. 4(b), the recovery in 'Nit still constitutes the major contribution of the recovered Vth even at VP of 1 V. This is essentially consistent with the results of static stress shown in Fig. 2. Since the interface states would be passivated by hydrogen-related species [3], our results suggest that neutral hydrogen play a major role in the NBTI degradation and recovery processes [10].

Fig. 1 Drain current increase (@VG-Vth =-2V & VD = -2V) for

PMOSFETs with and without PE-SiN layer.

Control L/W = 0.55Pm/10Pm 100 101 102 1010 1011 1012 1013 VG - Vth = -3.5 V VG - Vth = -3.9 V VG - Vth = -4.3 V Temp = 125 oC n ~ 0.2 Strained 100 101 102 103 104 101 102 103 1011 1012 1013 1014 VG -Vth = -3.5 V VG -Vth = -3.9 V VG -Vth = -4.3 V Temp = 125 oC n ~ 0.29

Fig. 2 'Vth and 'Nit versus stress time at three different gate biases with

L/W = 0.55Pm/10Pm.: (a) control devices, and (b) strained devices.

(b)

Stress Time (sec)

 ' Vth (m V)  ' Vth (m V) ' Nit (cm -2 ) ' Nit (cm -2) Channel Length (Pm) ' ID,sa t /ID, sa t (%) (a)

*Phone: 886-3-571-2121 ext: 54193, Fax: 886-3-572-4361, e-mail:hclin@faculty.nctu.edu.tw

0-7803-9498-4/06/$20.00 ©2006 IEEE IEEE 06CH37728 44th Annual International Reliability

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We have also investigated the effect of AC stress with 50%

duty cycle on the devices. Figure 5 shows 'Vth and 'Nit in devices

that were stressed at four different frequencies, both with and without SiN capping. It is seen that the interface state creation shows only weak frequency dependence in control devices. In reference to the analysis in previous reports [9][11], the observation is reasonable. In contrast, the strained devices depict strong frequency dependence

on both 'Vth and 'Nit. The shift in ǻVth and ǻNit after 5000 sec

stress are plotted as a function of stress frequency in Fig. 6. It is clear

that both ǻVth and ǻNit are strongly dependent on stress frequency in

the strained devices. ǻVth decreases from 214 mV to 94.2 mV when

the stress frequency increases from 1 kHz to 1 MHz. This observation indicates that excess hydrogen contained in the SiN capping layer initiates interface state generation by hydrogen bond breakage, and the process is very sensitive to the stress time. It also implies that aggravated NBTI degradation in the strained devices can be alleviated by high frequency operation. Our results indicate that significant Gm and on current enhancement relative to the control devices can be retained after the 5000 sec stress at high frequency.

C

ONCLUSION

Although the incorporation of a compressive PECVD SiN layer is highly coveted for enhancing the drive current, our results indicate that it may simultaneously aggravate the DC and AC NBTI characteristics of scaled PMOS devices. In other words, it acts like a double-edged sword that cuts both ways. An abundant hydrogen species contained in the PE-SiN layer as well as the strain energy stored in the channel are believed to be the culprits for the worsened reliability. In addition, the neutralization of trapped holes in the

oxide is found to contribute to the recovery in Vth. Finally, a strong

dependence on the frequency of AC stress is observed for the SiN-capped devices, which is ascribed to excess hydrogen species contained in the strained devices. Our observation also suggests that the aggravated NBTI in the strained devices could be alleviated by high frequency operation.

A

CKNOWLEDGMENTS

This work was supported by the National Science Council of the Republic o China under contract No. NSC 93-2215-E-009-033.

R

EFERENCES

[1] S. Ogawa et al., Phys. Rev. B, 1995, pp. 4218-4230. [2] G. La Rosa et al., IRPS, 1997, pp. 282-286. [3] G. Chen et al., IRPS, 2003, pp. 196-202.

[4] F. Ootsuka et al., Tech. Dig. of IEDM, 2000, pp. 575-578. [5] S. Ito et al., Tech. Dig. of IEDM, 2000, pp. 247-250. [6] T. Ghani et al., Tech. Dig. of IEDM, 2003, pp. 978-981. [7] K. Mistry et al., Symp. VLSI Technology, 2004, p. 50. [8] C. Y. Lu et al., SSDM, 2005, pp. 874-875.

[9] V. Huard et al., IRPS, 2004, pp. 40-45.

[10] S. Chakravarthi et al., IRPS, 2004, pp. 273-282. [11] M. A. Alam, Tech. Dig. of IEDM, 2003, pp. 345-348.

0 20 40 60 80 0 10 20 30 VP = 0V VP = 1V Control L/W = 0.55Pm/10Pm Temp = 125 o C Strained, Temp = 125 o C L/W = 0.55Pm/10Pm 0 2000 4000 6000 8000 10000 12000 0 100 200 300 400 500 0 100 200 300 400 VP = 0V VP = 1V

Fig. 3 'Vth and 'Nit versus stress time for dynamic NBTI with stress voltage of VG – Vth = -4 V at L/W = 0.55Pm/10Pm. (a) Control devices. (b) Strained devices. (a) (b) 0 1000 2000 3000 4000 0.0 0.2 0.4 0.6 0.8 1.0 VP = 0V VP = 1V L/W = 0.55Pm/10Pm Temp = 125 o C Strained Control 0.0 0.2 0.4 0.6 0.8 1.0 VP = 0V VP = 1V L/W = 0.55Pm/10Pm Temp = 125 oC Strained Control

Fig. 4 Normalized ǻVth and ǻNit versus stress time. (a) Recovery behavior of ǻVth in control and strained devices under VP = 0 and 1 V. (b) Recovery behavior of ǻNit in control and strained devices under VP = 0 and 1 V.

(a)

(b)

L/W=0.55Pm/10Pm

Stress Time (sec)

100 101 102 103 104  ' Vth (m V) 10 100 1000 1 kHz 10 kHz 100 kHz 1 MHz DC Stress Temp = 125 oC VG -Vth = -3.9 V Strained Control L/W=0.55Pm/10Pm 100 101 102 103 104 ' 1it (c m -2) 1010 1011 1012 1 kHz 10 kHz 100 kHz 1 MHz DC Stress Temp = 125 oC VG -Vth = -3.9 V Strained Control

Fig. 5 (a) ǻVth and (b) ǻNit versus stress time for control and strained samples under AC stress at four different frequencies.

103 104 105 106 0 50 100 150 200 250 300 350 0 20 40 60 80 Control ('Vth) Strained ('Vth) Control ('Nit) Strained ('Nit) DC Temp = 125 oC

Fig. 6 ǻVth and ǻNit versus stress frequency after 5000 sec stress time. (a)

(b) Stress Time (sec)

 ' Vth (m V) ' Nit (1 0 10cm -2)  ' Vth (m V) ' Nit (1 0 10cm -2) ' Nit (cm -2 )

Stress Time (sec)

 ' Vth (m V) Stress Frequency (Hz)  ' Vth (m V) ' Nit (1 0 10 cm -2 )

Stress Time (sec)

No rm a lized ' Nit No rm a lized ' Vth 728

數據

Figure 3 shows results of dynamic NBTI stress performed on  both control and strained devices under two passivation voltage (V P ) conditions
Fig. 4 Normalized ǻV th  and ǻN it  versus stress time. (a) Recovery behavior of ǻV th  in control and strained devices under V P  = 0 and 1 V

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