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An 8 Gbps Fast-Locked Automatic Gain Control for PAM Receiver

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Academic year: 2021

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Fig. 1 illustrates the automatic gain control loop  architecture (AGC), which is composed of a 3 stages variable  gain amplifiers (VGA), an amplitude detector, a level  comparator, an offset cancellation circuit, and a digital  controller
Fig. 2 (a) shows the architecture of the variable gain  amplifier, which is composed of a variable transconductance  input stage followed by a transimpedance gain stage
Fig. 5 Binary search engine.
Fig. 9 shows the chip micrograph. Fabricated in a generic  0.18 μm CMOS technology, the chip size is 0.62 by 0.62 mm 2 .

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