The signal continuity is greatly improved since the coaxial-type transition provides more return current paths compared to the con-ventional transition in the flip-chip structure. The proposed coaxial transition structure shows a real coaxial property from the 3-D electromagnetic wave simulation results. The design rules for the coaxial transition are presented in detail with the key parameters of the coaxial transition structure discussed. For demonstration, the back-to-back flip-chip interconnect structures with the vertical coaxial transitions have been successfully fabricated and charac-terized. The demonstrated interconnect structure using the coaxial transition exhibits the return loss below 25 dB and the insertion loss within 0.4 dB from dc to 40 GHz. Furthermore, the measurement and simulation results show good agreement. The novel coaxial transition demonstrates excellent interconnect performance for flip-chip interconnects and shows great potential for flip-chip packaging applications at millimeter waves.
Index Terms—Coaxial, coplanar waveguide (CPW), flip-chip, in-terconnect, transition.
I. INTRODUCTION
T
HE demands of high frequency interconnect techniques for monolithic microwave integrated circuits (MMICs) are growing with increasing operating frequencies in the wire-less communication systems. Interconnect effects can have significant impacts on the overall system performance at high frequencies. There are several interconnect schemes at the chip level packaging. Wire bonding technique is one of those, which has been widely used in the chip level packaging forManuscript received December 15, 2006; revised December 19, 2007. First published March 16, 2009; current version published May 28, 2009. This work was recommended for publication by Associate Editor T.-C. Chiu upon evalu-ation of the reviewers comments.
W.-C. Wu is with the Department of Material Science and Engineering, National Chiao Tung University, 300 Hsinchu, Taiwan and also with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, SE-412 96 Göteborg, Sweden.
E. Y. Chang, L.-H. Hsu, and C.-H. Huang are with the Department of Material Science and Engineering, National Chiao Tung University, 300 Hsinchu, Taiwan (e-mail: [email protected]).
C. Kärnfelt and H. Zirath are with the Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, SE-412 96 Göteborg, Sweden.
R.-B. Hwang is with the Department of Communication Engineering, Na-tional Chiao Tung University, 300 Hsinchu, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TADVP.2009.2014997
Fig. 1. Conventional vertical transitions of three bumps for CPW-to-CPW flip chip interconnects.
a long time. However, it suffers from serious parasitics when the operating frequency reaches the gigahertz range, due to its very long interconnect path. As a consequence, flip-chip tech-nique is expected as a low cost alternative for high frequency packaging with better transition performances. Flip-chip inter-connects have the advantages of shorter conducting path, lower parasitic effects, better heat dissipation, and smaller size over the traditional bonding-wire interconnects. Thus, a number of studies have been reported for designs and characterizations of flip-chip interconnects at high frequencies [1]–[8].
Flip-chip interconnects are more compatible with coplanar configurations, which are frequently used for very high fre-quency designs to minimize unwanted parasitics. Convention-ally, solder or gold bumps are grown on the ground and signal path of the coplanar waveguide (CPW) structure at the vertical transition region to maintain the continuity in the current flow. Fig. 1 shows the conventional flip-chip interconnect structure with three bumps for CPW-to-CPW transitions. Theories and effects of the bump positions and dimensions have been pre-sented and discussed in several papers [1], [2], [4]–[7]. In the conventional architecture, bump parameters and pad sizes are optimized for better transition characteristics. High impedance line and staggered bumps have been proposed to achieve broadband interconnect performances [1], [5], [7]. Another proposed design reported for better electrical shielding purpose was to use multiple ground bumps arranged in an annular form as the vertical transition at the flip-chip interconnect [8]. This was called pseudo-coaxial vertical transition. However, it was still not a real coaxial transition at the vertical interconnect. In this paper, we propose the coaxial transition for the flip-chip interconnect to replace the conventional two-ground-bump transition for the first time.
Fig. 2. Proposed structure of CPW-to-CPW interconnects with vertical “coaxial transitions.” (a) Substrate-side view. (b) Chip-side view. (c) Full view. (d) Detailed view at transition.
The proposed coaxial transition structure has two C-shaped ground bumps on the substrate and chip respectively to replace the two ground bumps [9]. Fig. 2 shows the flip-chip intercon-nect structure with the novel vertical coaxial transitions. The open ends of the two C-shaped bumps are arranged in opposite directions. The two C-shaped ground bumps together with the center cylindrical signal path form a perfect coaxial structure for better signal transmission, and the performance and charac-teristic properties of this transition will be discussed throughout the rest of this paper.
This paper is organized as follows. First, the fabrication process to realize the coaxial transitions onto the CPW circuits is presented, where the key process step, the thick photoresist lithography, is described in detail. Subsequently, by using the full wave 3-D electromagnetic wave simulator CST Microwave Studio, the electric and magnetic fields are plotted to show the coaxial properties at the transition. In the subsequent section, the main physical parameters of the proposed coaxial transition are described, and the design parameters for the coaxial transi-tion are discussed according to the full wave simulatransi-tion results. The interconnect structures with the coaxial transitions have been successfully fabricated and then radio-frequency (RF) characterized up to 40 GHz to verify the key design parameter of the coaxial transition. The transition model has been exported from the full wave CST simulator and inserted into Agilent Advanced Design System (ADS) simulation tool to simulate the complete flip-chip assembly, which shows good agreement with the measured results. The excellent results demonstrate the potential and feasibility of such coaxial transition for the flip-chip applications at high frequencies.
II. FABRICATION OFCOAXIALTRANSITION
For the proposed coaxial transition in the flip-chip structure, the fabrication of the coaxial bumps is of critical importance. The fabrication process for the coaxial transition onto the CPW circuits was developed in-house and has successfully demon-strated the coaxial concept for the flip-chip interconnects.
Fig. 3 shows the diagrams of the fabrication process proce-dures. Alumina and gallium arsenide (GaAs) were the
Fig. 3. Fabrication procedures of the coaxial transition structure.
materials for the substrate and the chip. The thickness of the substrate and GaAs chip were 254 and 100 , respec-tively. The substrate was 2-in square, and the GaAs was a 3-in wafer. The interconnect metal was gold and was formed by electroplating. First, metal Ti and Au (300 and 500 ) were successively deposited using E-gun evaporator onto the GaAs chip and substrate to form continuous seed layers for the following Au electroplating, as shown in Fig. 3(a). The plating bath was cyanide based solution. Ti was used as an adhesion layer to improve the adhesion of Au to the and GaAs materials, and Au was used as a seed layer for the following electroplating Au onto the matrix. In Fig. 3(b), thin photoresist from Shipley Company was then patterned on the chip and sub-strate to electroplate the circuits of the test structures. After the electroplating of the Au circuits, the thin photoresist was then removed, as shown in Fig. 3(c).
To form the vertical coaxial transition on the CPW circuits, high aspect ratio photolithography was developed, which was the key step in the whole process procedures. The used thick phototresists was from TOK Company. A double coating tech-nique for the thick photoresist was applied to achieve the flat surface of thick photoresist on the whole sample. At each coating step, the sample was baked on the hot plate at the temperature of 120 for 15 min to remove the solvents. A 60- -thick photoresist was obtained finally. The sam-ples were then exposed using Karl-Suss MJB-3 aligner with a broadband exposure. The masks were of film type, which was a low-cost approach with acceptable inaccuracy in the dimen-sions. Fig. 4 shows the SEM pictures of the photoresist profiles with different exposing and developing conditions. Fig. 4(a) and (b) shows the profiles of the thick photoresist with the best exposing and developing conditions after fine tuning. The scan-ning electron microscope (SEM) pictures show excellent pro-files with a smooth side wall and a clean bottom surface. How-ever, if the exposure was insufficient, serious residues remained at the bottom of the exposed areas after developing. Fig. 4(c) shows the SEM image of the serious residues. Fig. 4(d) shows
Fig. 4. SEM images of thick photoresist with different testing conditions. (a), (b) Exposing time: 9 min; developing time: 6 min. (c) Exposing time: 6 minutes; developing time: 6 min. (d) Exposing time: 9 min; developing time: 9 min.
Fig. 5. SEM images of the fabricated coaxial transition structures.
the SEM image of the overdeveloped profile. An over devel-oping time would bring a sloped side wall.
After the successful tests of the thick photoresist lithography, thick photoresist was coated; the positions and dimensions of the coaxial transitions bumps were then patterned both on the chip and substrate with the previously tested conditions, as shown in Fig. 3(d). Then, Au coaxial transitions were electroplated. By carefully controlling the electroplating current density and elec-troplating time, the bump of required heights were achieved, as shown in Fig. 3(e). The final step in the fabrication was the re-moval of the thick photoresist and seed layers. The seed layers were removed with solution for Au and HF dilute solution for Ti to finish the fabrication process, as shown in Fig. 3(f). After the thin metal etch, the test interconnect structure was success-fully fabricated. The SEM images of the fabricated coaxial tran-sition structures are shown in Fig. 5.
III. ELECTRIC ANDMAGNETICFIELDSPROPERTIES OFCOAXIALTRANSITION
The tool for the three dimensional electromagnetic (EM) field analysis of the coaxial interconnect structure is CST Microwave
Fig. 6. Simulated flip chip interconnect structure with the proposed coaxial transition.
Studio. Fig. 6 shows the simulated structure. In the simulation model, the material of the substrate is alumina , and the material of the chip is GaAs. The thickness of the alumina substrate and GaAs chip are 254 and 100 , respectively. The conductor metal is 3- gold. The transmission lines on both the chip and substrate are of CPW type.
Fig. 8. Main parameters of the vertical coaxial transition are chip-side bump height(h ), substrate-side bump height (h ), C-shaped ground bumps wall thickness(t ), and ratio of outer conductor radius to inner conductor radius at the coaxial transition(R = r =r ).
Fig. 7 shows the graphs of the electric field and magnetic filed of the proposed coaxial transition. From the plots, the coaxial transition shows better field confinement as compared to the conventional structure with three bumps at the CPW-to-CPW transitions.
IV. PARAMETERS OF COAXIAL TRANSITION ANDEM SIMULATION
The design and EM simulation of the proposed coaxial tran-sitions are performed using the simulation tool CST Microwave Studio. The effects of the geometric parameters on the inter-connect property are investigated, and the design rules are de-veloped according to the simulation results. For the proposed coaxial transition structure, the geometric parameters in inves-tigation are listed as follows:
1) chip-side bump height ; 2) substrate-side bump height ;
3) C-shaped ground bumps wall thickness ;
4) ratio of outer conductor radius to inner conductor radius of the coaxial transition .
Fig. 8 shows the definitions of the parameters. The charac-teristic impedances of CPWs on the substrate and chip are 50 . The signal widths on the chip and substrate are 50 . Thus, the spacing between the signal and ground on
Fig. 9. Simulation results of return loss versus frequency. The parameters are various chip-side bump heights (h = 10, 30, 50 m) while h equals 30 m, t equals 50m, and R equals 2.5 (r = 25 m, r = 62:5 m).
the chip and substrate are 34 and 24 , re-spectively. Single flip-chip transition structure is simulated to study the reflection property of the interconnect.
Fig. 9 shows the simulation results of the return loss for dif-ferent chip-side bump heights ( to 50 ) while ,
, and are 30 , 50 , and 2.5 ( , ). The results indicate that the increase in from 10 to 30 improves the return loss by 1.6 dB at 40 GHz. How-ever, further increase in from 30 to 50 does not have much effect on the return loss. A similar trend as the parameter is also observed for the parameter, the substrate-side bump heights .
The simulation results of return loss versus frequency with the same values of the substrate-side height and the chip-side bump height are shown in Fig. 10. The results indicate that the increase in and from 10 to 30 improves the return loss by 2.6 dB at 40 GHz. Further increase in and from
Fig. 10. Simulation results of return loss versus frequency. The parameters are various substrate-side and chip-side bump heights (h = h = 10, 30, 50 m) whilet equals 50m, and R equals 2.5 (r = 25 m, r = 62:5 m).
Fig. 11. Simulation results of return loss versus frequency. The parameters are various C-shaped ground bumps wall thickness (t = 10, 50, 100 m) while h equals 30 m, h equals 30 m, and R equals 2.5 (r = 25 m, r = 62:5 m).
30 to 50 has only a small improvement of 1.2 dB at 40 GHz on the return loss.
Fig. 11 shows the simulation results of the return loss versus frequency of the third parameter, C-shaped ground bumps wall thickness while the other parameters , , and are
30 , 30 , and 2.5 ( , ). From
the figure, it is observed that the smaller thickness of the C-shaped bumps wall, the lower the return loss at the in-terconnect is achieved. As the two C-shaped ground bumps to-gether with the center signal bump form a coaxial structure; they both go across the signal lines of the substrate and chip. In this way, the C-shaped ground bump gives a capacitive effect to the signal line and acts as a shunt capacitance. The thinner ground
Fig. 12. Simulation results of return loss versus frequency. The parameters are various ratio of outer conductor radius to inner conductor radius of coaxial tran-sitions (R = r =r = 3, 4, 5, 6, 7 while r = 25 m) while h equals 30 m, h equals 30 m, and t equals 50m.
wall thickness alleviates the capacitive effect and there-fore helps improve the reflection property of the coaxial transi-tion. Due to the process consideration, however, the parameter can not be too small. The process limitation comes from the aspect ratio of the thick photoresist and the mask resolution. In this study, the masks are of film type, which limits the line width on the mask. The dimension of the C-shaped ground bumps wall thickness is set to be 50 for the real fabricated coaxial structure in this study.
The most important parameter for the proposed coaxial tran-sition is the ratio of the outer conductor radius to the inner conductor radius . Fig. 12 shows the sim-ulation results of the return loss versus frequency of the param-eter ranging from 2.5 to 8 while the other parameters , , and are 30, 30, and 50 respectively. From the figure, when increases from 2.5 to 3, there is a small improvement in the return loss about 1.8 dB at 40 GHz. Further increase in to 5 improves the return loss significantly. The return loss for single transition is much less than 20 dB at 40 GHz when the parameter equals to 5, which shows very good interconnect performance. However, the return loss becomes worse when increases further. In the case of , the return loss greatly degrades. From the results, it is suggested that there is an op-timum value of giving the lowest reflection at the transition.
For better understanding of the coaxial transition structure and the effect of the key parameter , it is helpful to develop an equivalent circuit model for the coaxial transition structure. Fig. 13 shows the schematic of the coaxial transition and the developed equivalent circuit model. The associated equivalent circuit model of the coaxial transition consists of three physical transmission lines and two capacitors. The three transmission
lines describe the two CPW transmission lines inside the area of the coaxial structure and the coaxial structure itself. The two capacitors are used to account for the induced capacitances of the C-shaped ground bumps to the signal lines. Table I lists the model parameters of the coaxial transition structure for the case of after simulation and optimization. The shunt capaci-tances in the model were found to be . The impedances of the two CPW transmission lines were
cal-culated to be and , and
the impedance of the coaxial transmission line was
. The high-impedance transmission lines, exhibiting an in-ductive effect, compensate the capacitive effect induced by the C-shaped ground bumps, which results in the low reflection property of the coaxial transition. When the parameter is small, e.g. 2.5, the transition still shows an overall capacitive property because of the lower impedances (i.e. lower inductive effect) of the both CPW transmission lines and the coaxial trans-mission line and the excess capacitance. It explains why the in-crease of from 2.5 to 3 just gives small improvement in the return loss of the transition. The further increase of to 5 leads to higher impedance transmission lines, which enhances the in-ductive effect and makes the overall effect of the coaxial transi-tion match to 50 . In this case, it therefore gives the low return loss for the transition. However, when the value of increases to 8, it results in too much inductive effect and causes an overall inductive property of the transition, which degrades the return loss.
From the simulation results, several rules for the design of the coaxial transition are concluded and summarized as follows. The higher bump height gives the lower return loss at the in-terconnect. The thinner C-shaped ground wall thickness also gives the lower return loss. However, these two parameters of the coaxial transition only show small improvement on the re-flection property. The key parameter of the coaxial transition is the ratio , which greatly affects the interconnect property. It is suggested that there is an optimum value of , which gives the lowest reflection at the transition. With proper design, the
proposed coaxial transition can provide good interconnect per-formance for the flip-chip interconnects with low return loss and low insertion loss over a broad bandwidth at high frequencies up to 40 GHz.
V. EXPERIMENTALRESULTS
According to the discussion in the previous section, the geo-metric parameters of the vertical coaxial transition are the bump height , the C-shaped ground wall thickness , and the ratio of the outer conductor radius to the inner conductor radius at the coaxial transition, where is the key design pa-rameter. To demonstrate the proposed coaxial transition for the flip-chip application and verify the design rules, we have fabri-cated the back-to-back flip-chip interconnect structures with the vertical coaxial transitions for the various ratios by using the in-house developed fabrication process, which has been pre-sented and described in detail in Section II. The thermo-com-pression method was used to flip-chip bond the demonstrated samples. The compression during the bonding operations would bring some small changes to the original geometry of the coaxial transition. The bonding conditions were tested and optimized to avoid too much deformation of the bumps. However, it should be noticed that the best thermo-compression bonding conditions still caused little deformation of the bumps, including the reduc-tion in the bump height and the shift in the parameter of the coaxial transition. Fig. 14 shows the photograph of one flip-chip bonded interconnect structure. The scattering parameters of the test structures were then measured up to 40 GHz by the on-wafer probing measurement system with the Anritsu 37369C vector network analyzer.
For the demonstrated structures, the designed signal width of 50 CPW was 70 both on substrate and on GaAs chip. The inner conductor radius at the coaxial tran-sition was 35 . The C-shaped ground bump wall thickness was 50 . The height of the coaxial-type bump ( and ) was 30 both on the chip and substrate before flip-chip bonding. The interconnect structures with the various designed ratios ranging from 3 to 6 were fabricated and RF char-acterized. Fig. 15 shows the measurement results of the inser-tion loss versus frequency of the CPW transmission line on the substrate and the flip-chip interconnect structure with the coaxial transitions where the designed . These two struc-tures have equal length. Compared with the CPW transmission
Fig. 15. Measurement results of insertion loss versus frequency. Comparison between the CPW transmission line and the flip chip interconnect structure with the proposed coaxial transition(R = 3).
Fig. 16. Measurement results of return loss versus frequency. The parameters are various ratio of outer conductor radius to inner conductor radius of coaxial transitions (R = r =r = 3, 4, 5, 6) while h equals 30 m, h equals 30 m, t equals 50m.
line on the substrate, there are two more vertical coaxial transitions for the case of the flip-chip interconnect structure. Even so, from dc to 30 GHz, it shows no additional insertion loss. Above 30 GHz, the insertion loss only increases less than 0.1 dB.
Fig. 16 shows the measurement results of the return loss and the insertion loss versus frequency of the designed parameter .
different optimum values for the parameter . This should be taken into consideration in advance at the design stage.
About the performance comparison between the conven-tional three-bump (G-S-G) flip-chip interconnect structure and the proposed coaxial interconnect structure, there is actually no fair starting point to do the comparison because the proposed coaxial interconnect structure is completely different from the conventional one. Without compensation design, the return loss of the conventional flip chip interconnect was only about 18 dB from dc to 40 GHz [1], [2]. However, with high impedance compensation design at the transition, the return loss of the conventional one was further improved, which could be below 20 dB from dc to 40 GHz as indicated in [1]. In this study, the flip-chip interconnect structure using the proposed coaxial transition demonstrates an excellent reflection property below 20 dB from dc to 40 GHz as well. However, for the dimen-sional comparison with the conventional flip-chip structure, the coaxial approach requires a little more area in order to form the coaxial structure at the vertical transition.
After thermo-compression bonding, the designed parameters of the coaxial transition structure have changed. Therefore, we used the CST simulator to re-simulate the coaxial transition structure with the consideration of the reality. The coaxial tran-sition model data were then exported from the CST simulator and inserted into the Agilent ADS circuit simulation tool to simulate the full back-to-back flip-chip interconnect structure. Fig. 17 shows the modeling circuits of the flip-chip intercon-nect structure with the vertical coaxial transition for the case of the designed parameter . The same modeling circuits were also used to simulate the interconnect structures with the different designed ratios . The dimensions for the CPWs on the chip and the substrate are also shown in the figure.
The comparison between the simulated and the measured data is shown in Fig. 18. For the cases of , 4, and 5, the mod-eled and simulated curves show almost the same profiles. In the case of , the simulated and measured curves just show little difference. The simulated and measured results show ex-cellent agreement, which validates the accuracy of the transi-tion data exported from the EM wave simulatransi-tion tool. In this way, designers can predict the final performance of the assem-bled circuits in the system. It also means that one can take the vertical coaxial transitions and interconnects into consideration in advance at the design stage to anticipate the circuit perfor-mance after packaging and have beforehand optimization.
Fig. 18. The simulated and measured results of the flip chip interconnect structure with the different designed ratiosR of the coaxial transitions.
VI. CONCLUSION
The novel coaxial transitions for flip-chip interconnects have been proposed and demonstrated for the first time in this study. To realize the coaxial transition for the flip chip intercon-nects, the complete fabrication process has been successfully developed. By performing the full wave electromagnetic sim-ulation, the proposed coaxial transition has demonstrated the real coaxial properties. The physical parameters of the coaxial
transition structure are well indicated; their effects on the in-terconnect performance are also well investigated. The design parameters for the coaxial transition are the bump height, the C-shaped ground wall thickness, and the ratio of the radius of the outer conductor to the radius of the inner conductor. Based on the EM simulation results, several rules for the design of the coaxial transition are developed. Higher bump height and thinner C-shaped ground wall thickness show a small improvement in reflection property at the interconnect. The key
REFERENCES
[1] A. Jentzsch and W. Heinrich, “Theory and measurements of flip-chip interconnects for frequencies up to 100 GHz,” IEEE Trans. Microwave
Theory Tech., vol. 49, no. 5, pp. 871–878, May 2001.
[2] D. Staiculescu, J. Laskar, and E. M. Tentzeris, “Design rule develop-ment for microwave flip-chip applications,” IEEE Trans. Microwave
Theory Tech., vol. 48, no. 9, pp. 1476–1481, Sep. 2000.
[3] T. Hirose, K. Makiyama, K. Ono, T. M. Shimura, S. Aoki, Y. Ohashi, S. Yokokawa, and Y. Watanabe, “A flip-chip MMIC design with coplanar waveguide transmission line in the W-band,” IEEE Trans. Microwave
Theory Tech., vol. 46, no. 12, pp. 2276–2282, Dec. 1998.
[4] T. Krems, W. Haydl, H. Massler, and J. Rudiger, “Millimeter-wave per-formance of chip interconnections using wire bonding and flip chip,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 17–21, 1996, vol. 1, pp. 247–250.
[5] H. H. M. Ghouz and E.-B. El-Sharawy, “An accurate equivalent cir-cuit model of flip chip and via interconnects,” IEEE Trans. Microwave
Theory Tech., vol. 44, no. 12, pp. 2543–2554, Dec. 1996.
[6] W. Heinrich, A. Jentzsch, and G. Baumann, “Millimeterwave char-acteristics of flip-chip interconnects for multi-chip modules,” IEEE
Trans. Microwave Theory Tech., vol. 46, no. 12, pp. 2264–2268, Dec.
1998.
[7] A. Jentzsch and W. Heinrich, “Optimization of flip-chip interconnects for millimeter-wave frequencies,” in 1999 IEEE MTT-S Int. Microw.
Symp. Dig., Jun. 13–19, 1999, vol. 2, pp. 637–640.
[8] D. Staiculescu, J. Laskar, and M. Tentzeris, “Flip chip design rule de-velopment for multiple signal and ground bump configurations,” in
Asia-Pacific Microw. Conf., Dec. 3–6, 2000, pp. 136–139.
[9] W. C. Wu, R. B. Hwang, H. T. Hsu, E. Y. Chang, L. H. Hsu, C. H. Huang, and Y. C. Hu, “Design of flip-chip interconnects with vertical coaxial transitions and its fabrication,” in 2005 Asia-Pacific Microw.
Conf., Dec. 4–7, 2005, vol. 2, pp. 965–968.
Wei-Cheng Wu was born in Hsinchu, Taiwan, in
1979. He received the B.S. degree from the Depart-ment of Materials Science and Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2001. He is currently working toward the dual Ph.D. de-grees in materials science and engineering, National Chiao Tung University, Hsinchu, Taiwan, and the Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, Göte-borg, Sweden.
His research interests include fabrication, charac-terization, and packaging technologies of compound semiconductor devices and ICs for high frequency applications, especially flip chip interconnect and tran-sition design.
InP, GaAs based compound materials and devices (HEMT, HBT) for wireless communication, especially at milimeterwave range; GaN based materials (MBE, MOCVD) for optical (LED) and electronic (HEMT) applications; III-V/ Si integration (Ge, SiGe, GaAs, InP) for logic applications; advanced package (flip chip) for high frequency and LED applications.
Ruey-Bing Hwang (M’96–SM’06) was born in
Nantou, Taiwan, on January 20, 1967. He received the B.S. degree in communication engineering and the Ph.D. degree in electronics from National Chiao-Tung University, Hsinchu, Taiwan, in 1990 and 1996, respectively, and the M.S. degree in elec-trical engineering from National Taiwan University, Taipei, in 1992.
In 1996, he joined the National Center of High Per-formance Computing, Hsinchu, as an Associate Re-search Scientist. From 1999 to 2000, he was a Post-doctoral Research Fellow with the National Chiao-Tung University, where, from fall 2000 to spring 2002, he was a Research Associate Professor with the Mi-croelectronics and Information Systems Research Center. From spring 2002 to summer 2004, he was an Associate Professor with the Graduate Institute of Communication Engineering, National Chi Nan University, Nantou, Puli, Taiwan. In August 2004, he joined the faculty of the Department of Commu-nication Engineering, National Chiao Tung University. His research interests include the guiding and scattering characteristics of periodic structures (or pho-tonic crystals), meta-materials, waveguide antennas, array antennas design, and electromagnetic compatibility.
Dr. Hwang is a Member of Phi Tau Phi.
Li-Han Hsu was born in Tainan, Taiwan, in 1981.
He received the B.S. and M.S. degrees in materials science and engineering, from the National Chiao Tung University, Hsinchu, Taiwan, in 2003 and 2005, respectively. He is currently working toward the dual Ph.D. degrees in Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu, Taiwan and Department of Microtechnology and Nanoscience, MC2, Chalmers University of Technology, Göteborg, Sweden.
His main research interest is millimeter-wave packaging technology including flip-chip interconnect, hot-via interconnect, and integration of V-/E-band MCM transceiver modules.
Chen-Hua Huang received the B.S. and M.S.
degrees from the Materials Science and Engineering Department, National Chiao Tung University, Hsinchu, Taiwan, in 2004 and 2006, respectively.
She is currently with the Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan. Her research interests include high frequency packaging technology, microwave flip chip packaging, and coaxial transitions for CPW devices.
