氨電漿對下閘極多晶矽薄膜電晶體之影響

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國立交通大學

電子物理學系

碩士論文

氨電漿對下閘極多晶矽薄膜電晶體之影響

Effects of NH

3

Plasma Treatment on Bottom Gate

Poly-Silicon Thin-Film Transistors

研究生：陳儀儒

指導教授：趙天生博士

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氨電漿對下閘極多晶矽薄膜電晶體之影響

Effects of NH

3

Plasma Treatment on Bottom Gate

Poly-Silicon Thin-Film Transistors

指導教授：趙天生博士

Advisor : Dr. Tien-Sheng Chao

研究生：陳儀儒

Student : Yi-Ju Chen

國立交通大學

電子物理學系

碩士論文

A Thesis

Submitted to Department of Electrophysics

College of Science

National Chiao Tung University

in Partial Fulfillment of the Requirements

for the Degree of Master of Science

in Electrophysics

July 2013

Hsinchu, Taiwan, Republic of China.

中華民國一百零二年七月

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氨電漿對下閘極多晶矽薄膜電晶體之影響

指導教授：趙天生博士研究生：陳儀儒國立交通大學電子物理學系摘要首先，本研究深入探討氨電漿對於下閘極多晶矽薄膜電晶體鈍化效應之影響。這些元件經過數種條件的氨電漿製程，包括不同階段、不同製程時間長度，以及不同功率的電漿製程。相較於沒有經過電漿製程的元件，pre-SPC-treatment 會使元件電性變差，而 post-SPC-treatment 及 after-AA-treatment 會提升元件電性。經過 pre-SPC-treatment 的元件有最差的電性表現，而經過 after-AA-treatment 的元件則有最好的電性表現。雖然 after-AA-treatment 是鈍化缺陷最有效率的方式，但是相較於 post-SPC-treatment，經過 after-AA-treatment 的元件也受到最嚴重的離子轟擊傷害。此外，較長時間或是較高功率的電漿製程，可以較有效地提升元件電性、抑制電流突增效應(Kink Effect)。較高功率的電漿製程也可以較有效地提升閘極氧化層的品質。隨後，本研究探討退火製程對於已接受過電漿製程之多晶矽薄膜電晶體的影響。我們推測在氮氣的環境之下，退火或許可以消除乾蝕刻期間，在閘極氧化層中產生的電洞缺陷。此外，經過退火的元件，其電性表現主要受到幾個機制影響，分別是： (1)退火消除閘極氧化層中的電洞缺陷、(2)退火製程期間，氮自由基及氫自由基被釋出，並喪失鈍化效應、(3)退火製程後，殘餘的鈍化效應、(4)氨電漿製程中所造成的電漿傷害。

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Effects of NH

3

Plasma Treatment on Bottom Gate Poly-Silicon

Thin-Film Transistors

Advisor : Dr. Tien-Sheng Chao Student : Yi-Ju Chen

Department of Electrophysics National Chiao Tung University

Abstract

First, the passivation effect of NH3 plasma treatment on bottom gate poly-Si TFTs is thoroughly discussed. The poly-Si TFTs are exposed to NH3 plasma with several conditions, including diverse stages, various plasma treatment time, and different plasma power.

Compared with the sample without any plasma treatment, pre-SPC-treatment degrades device performance; however, post-SPC-treatment and after-AA-treatment improve device performance. The poly-Si TFTs with pre-SPC-treatment exhibit the worst performance, and those with after-AA-treatment ones exhibit the best performance than the counterparts. Although after-AA-treatment is the most efficient technique to passivate traps, the poly-Si TFTs with after-AA-treatment suffer from the heaviest ion bombardment damage than those with post-SPC-treatment ones. In addition, longer plasma treatment time or higher plasma power will enhance performance and alleviate kink effect more effectively. The plasma treatment with higher plasma power will also strengthen the bulk oxide quality more significantly.

Second, the impacts of post-metal-annealing on plasma-treated poly-Si TFTs are systematically investigated. We hypothesize that PMA in N2 ambient is a method to annihilate the hole traps in the gate oxide generated by plasma dry etching. Moreover,

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the performance of the poly-Si TFTs with PMA are mainly attributed to the combination of following mechanisms: 1) the elimination of the hole traps in the gate oxide by PMA, 2) the out-diffusion of nitrogen and hydrogen radicals during PMA processing, 3) the remaining passivation effect by NH3 plasma, and 4) the plasma-induced damage by NH3 plasma.

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誌謝

Time goes fast ~ 轉眼間，碩班生涯即將結束了。碩班的兩年期間，很幸運的遇到許多貴人，也受到許多人的幫助。首先要感謝指導老師─趙天生老師。無論是做研究的態度，或者是待人處事的學問，老師都是我的模範。謝謝老師提供良好的研究環境，讓學生有許多學習、成長的機會，並且在研究遇到瓶頸時，給予學生方向。能夠當您的學生真的很幸運，謝謝您！感謝廖家駿學長以及劉劭軒學長的指導。謝謝家駿學長即使在工作了，仍然在下班後專程回學校指導我。你總是很有耐心指導我許多理論及嚴謹的研究方法，並且鼓勵我閱讀各領域的文獻，讓我知道應該要時時充實自己，提升自己的視野。你對自己的高標準，以及實踐目標的能力，一直都是我的榜樣。沒有你的教導及督促，我不可能這麼順利的完成碩士學業，真的很謝謝你。感謝劭軒學長當初很有幹勁的完成這批元件，讓我可以在沒有壓力的情況下量測元件，完成碩論。謝謝你一大早陪我進NDL做實驗，以及在課業上給予協助，雖然有幾次我翹掉小咪，但我會一直記得你是一個熱心又很棒的學長！謝謝郭柏儀學長在實驗上的幫助，讓我學習到嚴謹的實驗態度。謝謝陳昱璇學姊總是很有耐心的替我解答疑惑，熱心的借給學弟妹們妳的精美筆記，並且給予我許多實驗及課業上的幫助。感謝林哲緯學長、呂侑倫學長、呂宜憲學長、吳翊鴻學長、嚴立丞學長、張添舜學長、林哲毅學長、卓大鈞學長、郭柔含學姊、唐明慈學姊、偉斌、阿孔、小小、樂樂、小崴、可立、品烝及方晴的陪伴，讓我的碩班回憶增添不少色彩。此外，謝謝十幾年的老友期蘭，細心的幫我修改論文文法，並時時給我鼓勵與支持，一起分享生活中的酸甜苦辣。感謝室友柔儀，幫我找了許多如何寫論文的資料，並且幫我修正文法。謝謝大學直屬學姊曼麗，到了碩班還是這麼的照顧我，認識妳真好。還要謝謝那些一路陪伴在我身邊的朋友們，因為有你們的陪伴，當我遇到挫折時，才有力量再站起來！最後，我要感謝我的父母─陳正昌先生與林素秋女士。謝謝你們給我一個無憂無慮的成長環境，給我很多自由，一路以來支持我所做的任何決定，讓我有機會去嘗試許多挑戰，並且在我低潮時，給我許多建議及陪伴。因為有你們如此堅強的後盾，我才可以心無旁騖的完成學業，邁入人生的下一段旅程。

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Chapter 1 Introduction

1.1 Background ... 1

1.1.1 Poly-Si TFTs ... 1

1.1.2 Plasma Treatment ... 2

1.1.3 Bottom Gate TFT Structure ... 4

1.2 Motivation ... 4

Chapter 2 Device Fabrication and Experimental Setup

2.1 Introduction ... 7

2.2 Experimental Procedure ... 7

2.3 Measurement and Equipment Setup ... 8

2.3 Extraction Methods of Device Parameters ... 9

2.3.1 Threshold Voltage ... 9

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Chapter 3 Effects of NH

3

Plasma Treatment on Bottom Gate Poly-Si

TFTs

3.2 Plasma Treatment Time Dependence ... 15

3.3 Plasma Power Dependence ... 20

3.4 Summary ... 22

Chapter

4 Impacts of Post-Metal-Annealing on Plasma-Treated

Bottom Gate Poly-Si TFTs

4.2 Plasma Treatment Time Dependence ... 39

4.3 Plasma Power Dependence ... 41

4.4 Post-Metal-Annealing Time Dependence ... 42

4.4.1 Plasma Treatment Time Dependence ... 42

4.4.2 Plasma Power Dependence ... 43

4.5 Summary ... 44

Chapter 5 Conclusion and Implications for Future Research

5.1 Conclusion ... 61

5.2 Implications for Future Research ... 62

References

... 65

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Table Caption

Chapter 5

Table 5-1 The comparison of different plasma treatment time. ... 64 Table 5-2 The comparison of different plasma power. ... 64

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Figure Caption

Chapter 1

Fig. 1-1 (a) Bottom gate TFTs. (b) Top gate TFTs. ... 6

Chapter 2

Fig. 2-1 The process flow of the poly-Si TFTs. ... 10

Fig. 2-2 Schematic of the fabrication processes for bottom gate poly-Si TFTs. ... 13

Fig. 2-3 The process splits for the poly-Si TFTs. ... 13

Fig. 2-4 The experimental setup of each apparatus. ... 14

Chapter 3

Fig. 3-1 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma pre-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 24

Fig. 3-2 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 24

Fig. 3-3 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 25

Fig. 3-4 Top-view of bottom gate poly-Si TFTs with plasma-induced hole traps in the gate oxide at the corner edge portions with (a) wide channel width and (b) narrow channel width. ... 26

Fig. 3-5 The transistor can be equivalent to flat plate transistor and corner edge transistor in parallel. ... 26

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Fig. 3-6 IDS–VGS characteristics of poly-Si TFTs for the samples with 2 μm channel width with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 27 Fig. 3-7 IDS–VGS characteristics of poly-Si TFTs for the samples with 2 μm channel width with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 27 Fig. 3-8 Threshold voltage (VTH) as a function of plasma treatment time. ... 28 Fig. 3-9 Maximum transconductance (Gm_max) as a function of plasma treatment

time. ... 28 Fig. 3-10 NH3 plasma after-AA-treatment passivates channel traps not only by

radicals diffusing vertically through the poly-Si channel, but also by radicals diffusing laterally through the gate oxide. ... 29 Fig. 3-11 The extra damage on the sidewall of the channel for the poly-Si TFTs with NH3 plasma after-AA-treatment. ... 29 Fig. 3-12 IDS–VDS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 30 Fig. 3-13 IDS–VDS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 30 Fig. 3-14 Slopes of IDS–VDS characteristics (post-SPC-treatment) as a function of

plasma treatment time (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 31 Fig. 3-15 Slopes of IDS–VDS characteristics (after-AA-treatment) as a function of

plasma treatment time (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 31

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Fig. 3-16 Gate-leakage current characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 32 Fig. 3-17 Gate-leakage current characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 32 Fig. 3-18 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma pre-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 33 Fig. 3-19 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 33 Fig. 3-20 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 34 Fig. 3-21 Threshold voltage (VTH) as a function of plasma power. ... 34 Fig. 3-22 Maximum transconductance (Gm_max) as a function of plasma power. ... 35 Fig. 3-23 IDS–VDS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 35 Fig. 3-24 IDS–VDS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 36 Fig. 3-25 Slopes of IDS–VDS characteristics (post-SPC-treatment) as a function of

plasma treatment time (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 36

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Fig. 3-26 Slopes of IDS–VDS characteristics (after-AA-treatment) as a function of plasma treatment time (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 37 Fig. 3-27 Gate-leakage current characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 37 Fig. 3-28 Gate-leakage current characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 38

Chapter 4

Fig. 4-1 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs (pre-SPC-treatment) (a) with and (b) without PMA (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 46 Fig. 4-2 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs (post-SPC-treatment) (a) with and (b) without PMA (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 47 Fig. 4-3 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs (after-AA-treatment)

(a) with and (b) without PMA (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 48 Fig. 4-4 IDS–VGS characteristics of poly-Si TFTs with 2 μm channel width

(post-SPC-treatment) (a) with and (b) without PMA (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 49 Fig. 4-5 IDS–VGS characteristics of poly-Si TFTs with 2 μm channel width

(after-AA-treatment) (a) with and (b) without PMA (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 50

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Fig. 4-6 Maximum transconductance (Gm_max) as a function of plasma treatment time for poly-Si TFTs with NH3 plasma pre-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 51 Fig. 4-7 Maximum transconductance (Gm_max) as a function of plasma treatment

time for poly-Si TFTs with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 51 Fig. 4-8 Maximum transconductance (Gm_max) as a function of plasma treatment

time for poly-Si TFTs with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min). ... 52 Fig. 4-9 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs (pre-SPC-treatment)

(a) with and (b) without PMA (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 53 Fig. 4-10 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs (post-SPC-treatment) (a) with and (b) without PMA (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 54 Fig. 4-11 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs (after-AA-treatment) (a)

with and (b) without PMA (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 55 Fig. 4-12 Maximum transconductance (Gm_max) as a function of plasma power for

poly-Si TFTs with NH3 plasma pre-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 56 Fig. 4-13 Maximum transconductance (Gm_max) as a function of plasma power for

poly-Si TFTs with NH3 plasma post-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 56

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Fig. 4-14 Maximum transconductance (Gm_max) as a function of plasma power for poly-Si TFTs with NH3 plasma after-AA-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 57 Fig. 4-15 Maximum transconductance (Gm_max) as a function of PMA time for poly-Si TFTs with NH3 plasma pre-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min or 120 min). ... 57 Fig. 4-16 Maximum transconductance (Gm_max) as a function of PMA time for poly-Si TFTs with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min or 120 min). ... 58 Fig. 4-17 Maximum transconductance (Gm_max) as a function of PMA time for poly-Si TFTs with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min or 120 min). ... 58 Fig. 4-18 Maximum transconductance (Gm_max) as a function of PMA time for poly-Si TFTs with NH3 plasma pre-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 59 Fig. 4-19 Maximum transconductance (Gm_max) as a function of PMA time for poly-Si TFTs with NH3 plasma post-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 59 Fig. 4-20 Maximum transconductance (Gm_max) as a function of PMA time for poly-Si TFTs with NH3 plasma after-AA-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min). ... 60

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Chapter 1 Introduction

1.1 Background

1.1.1 Poly-Si TFTs

Ongoing researches for polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted intense attention recently, due to their advantages over amorphous silicon thin-film transistors (a-Si TFTs), such as higher carrier mobility, lower leakage, and higher drive current. Thus, poly-Si TFTs have been widely used in large-area flat panel displays, for example, active-matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting displays (AMOLEDs) [1.1]-[1.2].

However, the grain boundaries and intra-grain defects degrade carrier transport [1.3]; therefore, they exert a profound influence on the device performance. For this reason, reducing defects inside the poly-Si layer plays a crucial role in optimizing the performance of poly-Si TFTs. It has been reported that poly-Si, formed by the crystallization of a-Si, results in larger grain size and better electronic properties than as-deposited poly-Si [1.4]. In order to improve the characteristics of poly-Si TFTs, there are various techniques in the fabrication which are aimed at two characteristics: 1) enlargement of grain size, and 2) removal of defects in poly-Si films.

Various techniques have been used to crystallize the a-Si into the poly-Si, for instance, solid phase crystallization (SPC), rapid thermal annealing (RTA), excimer laser crystallization (ELC), and metal-induced lateral crystallization (MILC). For SPC process, although it usually takes a long crystallization time of about 20-60 hours at 600℃, its advantages, such as low cost and superior uniformity, make it a commonly used technique [1.5]. RTA is a high temperature (>600℃) process that can complete

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crystallization in a short period of time, but this results in films with high defect density [1.6]-[1.7]. Compared with SPC and RTA, ELC can be considered a low temperature process. Even though it is capable of producing poly-Si films with low defect density, it suffers from high initial setup cost, high process complexity and poor uniformity [1.8]. Furthermore, MILC has the problem with metal residues which lead to unacceptable leakage current [1.9]-[1.10].

To passivate the grain boundaries and intra-grain defects, various passivation methods such as hydrogen plasma treatment, hydrogen implantation, and hydrogen-containing nitride film deposition have been applied [1.11]-[1.13]. Although hydrogen passivation eliminates defects and improves the performance of poly-Si TFTs effectively, the poly-Si TFTs after hydrogen passivation suffer from hot-carrier, which might degrade the reliability [1.14]. Because the formation of weak Si–H bonds after hydrogen passivation are easily-broken under hot-carrier stress, F, N2, NH3 plasma treatment are used to obtain a better hot-carrier reliability than H2 plasma treatment [1.14]-[1.16].

1.1.2 Plasma Treatment

Poly-Si thin film consists of different oriented grains, containing many grain boundaries and intra-grain defects. These defects act as trap centers and degrade carrier transport, resulting in unacceptable characteristics of poly-Si TFTs [1.17]. The deep states, which originate from the dangling bonds at grain boundaries, have a faster response to hydrogenation. These deep states degrade the threshold voltage and the subthreshold swing. The tail states, which originate from the strain-bond-related intra-grain defects, respond slower to hydrogenation with an onset period of 4 to 12 hours depending on the grain size. And these tail states degrade the field-effect mobility and minimum leakage current [1.3]. In order to obtain superior

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characteristics of poly-Si TFTs, numerous techniques have been used to enhance the device performance by reducing the trap density or increasing the grain size of the polysilicon [1.4].

H2 plasma treatment, also called hydrogenation, is an effective method to passivate defects and improve the performance of poly-Si TFTs. Unfortunately, poly-Si TFTs after hydrogen passivation suffer from hot-carrier issue because the formation of weak Si–H bonds are easily-broken during hot-carrier stressing [1.15]. Also, poly-Si TFTs with H2 plasma treatment loss their passivation effect after subjecting to high temperature (>500℃) annealing [1.16].

N2 plasma treatment can effectively improve device characteristics, such as field-effect mobility, subthreshold swing, minimum leakage current, and on/off current ratio [1.14]. Furthermore, N2 plasma treatment has been proposed to attenuate hot-carrier degradation. Poly-Si TFTs with N2 plasma treatment have better hot-carrier reliability than using H2 plasma treatment, due to strong Si–N bonds with higher bonding energy that would replace the weak Si–H bonds.

Because of the passivation effect of nitrogen and hydrogen radicals, NH3 plasma treatment has also been studied. Similar to N2 plasma treatment, NH3 plasma treatment can passivate defects, improve the performance and the hot-carrier reliability of poly-Si TFTs [1.18]-[1.19]. Besides, it is found that NH3 plasma pretreatment before SPC annealing significantly shortens the a-Si film crystallization time and simultaneously improves device performance and hot-carrier reliability [1.20]. These improvements can be attributed to the combination of following mechanisms: 1) hydrogen radicals that enhance the formation of seed nuclei which reduces crystallization time, and 2) nitrogen and hydrogen radicals pile-up at SiO2/poly-Si interface and terminate the dangling bonds at the grain boundaries, leading to improved performance.

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1.1.3 Bottom Gate TFT Structure

Bottom gate TFTs as shown in Fig. 1-1(a), have been widely used because of good match with process integration of conventional SRAMs. Their channel areas are good isolated from parasitic electric field caused by under layers [1.21]. Also, bottom gate TFTs are commonly used as the switching elements in AMLCDs fabrication. It has been reported that bottom gate TFTs can be easily fabricated by the laser annealing of a-Si film for the active layer [1.22], allowing higher circuit density and improving topography compared with top gate devices [1.23]. In addition, because the gate electrode is located under gate insulator for bottom gate structure, the channel is not damaged by the plasma radiation during gate insulator deposition. Therefore, bottom gate TFTs have larger on-state current (ION) than the top gate TFTs [1.24].

Unfortunately, compared with top gate devices as shown in Fig. 1-1(b), smaller grain size and irregular grains of the poly-Si channel result in unacceptable characteristics of bottom gate TFTs [1.25]. Besides, because the gate is located under the active layer, it is difficult to fabricate a bottom gate TFT with its gate edges self-aligned to its source/drain. Thus, bottom gate TFTs suffer from significant performance variation, large parasitic capacitance and poor scalability owing to the misalignment effect [1.23]. Although some self-aligned bottom gate TFTs processes have been proposed, the device processes were too complicated to be utilized [1.26].

1.2 Motivation

It is known that NH3 plasma treatment is an effective method to passivate defects that will improve the performance and the hot-carrier reliability of poly-Si TFTs. Moreover, it has been proposed that NH3 plasma pretreatment before SPC annealing not only shortens the a-Si film crystallization time significantly, but also improves device performance and hot-carrier reliability simultaneously. In fact, hydrogen

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radicals enhance the formation of seed nuclei, which reduces crystallization time. Meanwhile, nitrogen and hydrogen radicals terminate the dangling bonds at the grain boundaries. It is because of these two events that strong Si–N bonds are formed and then the trap density is decreased.

Although there are several literatures discussing the passivation effect of NH3 plasma treatment for top gate devices, there are few for bottom gate poly-Si TFTs. In addition, because the channel is located over the gate electrode for bottom gate structure, the poly-Si channel is directly exposed to NH3 plasma. The passivation effect of bottom gate structure may be different to top gate structure. Thus, the passivation effect of NH3 plasma treatment for bottom gate poly-Si TFTs will be thoroughly studied in this study. The poly-Si TFTs will be exposed to NH3 plasma with several conditions, including diverse stages, various plasma treatment time, and different plasma power. The influences of NH3 plasma with different conditions on bottom gate poly-Si TFTs will also be systematically investigated.

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(b)

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Chapter 2 Device Fabrication and Experimental Setup

2.1 Introduction

The process flow, experimental procedure, measurement, and equipment setup will be introduced in detail. In addition, the methods to extract the important electrical parameters will also be proposed.

2.2 Experimental Procedure

Fig. 2-1 shows the process flow of the poly-Si TFTs in this study, and the fabrication processes are shown in Fig. 2-2 (a)-(e). It is important to emphasize that each wafer was exposed to NH3 plasma only once. The NH3 plasma treatments were performed by plasma-enhanced chemical vapor deposition (PECVD), using pure NH3 gas of 200 sccm, substrate temperature of 300℃, RF power of 50 W or 200 W, and the plasma treatment time varied from 15 to 120 min.

First, the thermal oxide of 5000 Å was grown on the 6 inch silicon wafer by horizontal furnace. The poly-Si film of 1500 Å was deposited as the gate electrode by low-pressure chemical vapor deposition (LPCVD) and implanted with phosphorous (50 keV at 5×1015 cm-2) (Fig. 2-2 (a)). After gate electrode patterning, a 200 Å thick tetraethyl orthosilicate (TEOS) oxide was deposited as the gate insulator. Then, the a-Si film of 500 Å was deposited. Some wafers were exposed to NH3 plasma, which was defined as “pre-SPC-treatment”, and the other wafers were skipped in this step (Fig. 2-2 (b)).

The a-Si was crystallized by solid phase crystallization (SPC) at 600℃ for 24 hr to transform the a-Si into poly-Si. The source/drain were implanted with phosphorous

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(15 keV at 5×1015 cm-2) and activated by annealing at 600℃ for 24 hr in N2 ambient.

Some wafers were exposed to NH3 plasma, which was defined as

“post-SPC-treatment”, and the other wafers were skipped in this step (Fig. 2-2 (c)).

After defining the active area, some wafers were exposed to NH3 plasma, which was defined as “after-AA-treatment”, and the other wafers were skipped in this step

(Fig. 2-2 (d)). Then, the 5000 Å thick SiO2 by PECVD was deposited as the passivation layer. After patterning of the contact holes, the 6000 Å thick Al-Si-Cu pad was deposited by physical vapor deposition (PVD) and patterned to finish the processes of poly-Si TFTs fabrication (Fig. 2-2 (e)). All process splits are illustrated in Fig. 2-3. The poly-Si TFTs were exposed to NH3 plasma with several conditions, including diverse stages, various plasma treatment time, and different plasma power.

2.3 Measurement and Equipment Setup

Measurement setup of the poly-Si TFTs is presented in Fig. 2-4, including semiconductor characterization system (KEITHLEY 4200), pulse pattern generator (Agilent 81110A), low leakage current switch mainframe (KEITHLEY 708A), and probe station.

KEITHLEY 4200 is equipped with programmable source-monitor units (SMU) which provides high resolution to measure DC I-V, pulse characterization and reliability testing of semiconductor devices.

Agilent 81110A with two pulse channels supplies high timing resolution pulse. When the devise is measured in probe station, KEITHLEY 708A, which is configured a 10-input × 12-output switching matrix, switching the signals from KEITHLEY 4200 and Agilent 81110A. Moreover, the C++ language is used for controlling the devise measurement instruments.

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2.3 Extraction Methods of Device Parameters

The extraction methods of electrical parameters, including threshold voltage (VTH) and transconductance (Gm), will be introduced in the following sections.

2.3.1 Threshold Voltage

In this thesis, threshold voltage (VTH) is determined by constant drain current method. VTH is defined as the gate voltage that yields a drain current (IDS) of 100 nA , where IDS = 100 nA × (W/L). W and L are channel width and channel length, respectively. This method is utilized in most of the studies of TFTs.

2.3.2 Transconductance

Transconductance (Gm) is the guide to extract the field-effect mobility (μFE). Field-effect mobility is calculated from the maximum transconductance (Gm_max) at low drain bias (VDS = 0.1 V). The drain current in linear region (VDS < VGS െ VTH) can be approximated as





1 2 2 DS FE OX GS TH DS DS W I C V V V V L     _   _  ... (2-1)

where COX is the gate oxide capacitance per unit area and VDS is the drain-source voltage. The transconductance (in linear region) is defined as

_ max DS ( ) m EF OX DS GS I W G C V V  L     ... (2-2)

However, KEITHLEY 4200 is automatic to extract Gm_max from the transfer characteristics (IDS–VGS). By finding out the Gm_max, we can calculate the field-effect mobility of all samples.

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Wafers (wafer 1st~ 16th) 5000 Å wet oxide 1500 Å poly-Si Gate implantation (phosphorous, 50 keV at 5×1015_cm-2₎

Gate electrode patterning 200 Å TEOS oxide

500 Å a-Si

SPC at 600 for 24 hr S/D implantation (phosphorous, 15 keV at 5×1015cm-2)

Active area (AA) definition

5000 Å SiO2passivation 6000 Å Al-Si-Cu pad

Pre-SPC-Treatment

(wafer 1st_{~ 5}th₎

Post-SPC-Treatment

(wafer 6th~ 10th)

After-AA-Treatment

(wafer 11th~ 15th) (wafer 6th_{~ 16}th₎ (wafer 1st~ 5th, 11th~ 16th) (wafer 1st~ 10th, 16th)

Gate & S/D activation (600 for 24 hr in N2ambient)

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(a) The thermal oxide of 5000 Å was grown. The poly-Si film of 1500 Å was deposited and implanted with phosphorous (50 keV at 5×1015 cm-2).

(b) After gate electrode patterning, a 200 Å thick TEOS oxide was deposited as the gate insulator. Then, the a-Si film of 500 Å was deposited. Some wafers were exposed to NH3 plasma, which was defined as “pre-SPC-treatment”.

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(c) SPC at 600℃ for 24 hr to transform the a-Si into poly-Si. The S/D were implanted with phosphorous (15 keV at 5×1015 cm-2) and activated by annealing at 600℃ for 24 hr in N2 ambient. Some wafers were exposed to NH3 plasma, which was defined as “post-SPC-treatment”.

(d) After defining the active area, some wafers were exposed to NH3 plasma, which was defined as “after-AA-treatment”.

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oxide

Poly-Si

N

+

N

+

SiO

2

Passivation

Al-Si-Cu Al-Si-Cu

Si Substrate

Wet Oxide

N

+ Poly-Si Gate

(e) The 5000 Å thick SiO2 was deposited as the passivation layer. After patterning of the contact holes, the 6000 Å thick Al-Si-Cu pad was deposited and patterned to finish the process of poly-Si TFTs fabrication.

Fig. 2-2 Schematic of the fabrication processes for bottom gate poly-Si TFTs.

Fig. 2-3 The process splits for the poly-Si TFTs.

Plasma

Treatment

Pre-SPC

50 W

15~120 min

200 W

15 min

Post-SPC

50 W

15~120 min

200 W

15 min

After-AA

50 W

15~120 min

200 W

15 min

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Chapter 3 Effects of NH

3

Plasma Treatment on Bottom Gate

Poly-Si TFTs

3.1 Introduction

NH3 plasma treatment is an effective method to passivate defects that will improve the performance and the hot-carrier reliability of poly-Si TFTs [3.1]-[3.2]. During NH3 plasma treatment, radicals pile-up at SiO2/poly-Si interface and passivate the dangling bonds at grain boundaries (deep states) as well as the intra-grain traps (tail states), leading to improved performance. [3.3]. In this chapter, the passivation effect of NH3 plasma treatment on bottom gate poly-Si TFTs will be thoroughly studied. First, the influences of different NH3 plasma treatment time will be discussed. Second, the influences of different NH3 plasma power will also be systematically investigated.

3.2 Plasma Treatment Time Dependence

Fig. 3-1 – Fig. 3-3 illustrate IDS–VGS and Gm–VGS characteristics of n-channel poly-Si TFTs for control sample and the samples with NH3 plasma pre-SPC-treatment, post-SPC-treatment, and after-AA-treatment at VDS of 0.1 V, respectively. These poly-Si TFTs were exposed to NH3 plasma with power of 50 W, and the plasma treatment time varied from 15 min to 120 min. The subthreshold double-hump phenomenon has been measured in these poly-Si TFTs. The subthreshold double-hump phenomenon indicates that there are two conduction paths for the device [3.4]. During plasma dry etching processing, especially in active area patterning, high energy photons may cause various types of damage, such as a shift in the threshold

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voltage and the formation of crystalline defects [3.5]-[3.8]. It has been reported that plasma-induced charging stress produces the generation of hole traps and interface states in the gate oxide. The generation of hole traps will lead to negative VTH shift [3.9]-[3.10]. The top-view of bottom gate poly-Si TFTs with different channel width are shown in Fig. 3-4 (a) and (b). For the poly-Si TFT in the width direction, the equivalent channel width can be divided into the flat plate and corner edge portions. During active area patterning, plasma may cause damage on the sidewall of the oxide, and the plasma-induced charging will generate new hole traps at the corner edge portions. These hole traps in the gate oxide lead to negative VTH shift at the corner edge portions, and the corner edge portions will have lower VTH than the flat plate portion. As shown in Fig. 3-5, this transistor can be equivalent to flat plate transistor and corner edge transistor in parallel. At low VGS region, corner edge transistor which has low VTH will be turned on first, then the flat plate transistor which has high VTH will be turned on as VGS is further increased [3.11]. Moreover, the non-uniform VTH exhibits the early turn-on phenomena.

Once the channel width decreases from 10 μm to 2 μm, the corner edge portions will gradually dominate the device characteristics as shown in Fig. 3-4 (b). The IDS– VGS characteristics for the samples with 2 μm channel width are shown in Fig. 3-6 and Fig. 3-7. The poly-Si TFTs with 2 μm channel width have large off-state leakage current (IOFF) due to the impacts of the corner edge portions. The hole traps generated by plasma dry etching at the corner edge portions construct a leakage path and lead to a large IOFF. In addition, for the poly-Si TFTs with NH3 plasma after-AA-treatment as shown in Fig. 3-7, the IOFF become smaller with longer NH3 plasma treatment time. We hypothesize NH3 plasma after-AA-treatment may eliminate some of the hole traps generated by active area patterning, and after-AA-treatment may decrease the IOFF.

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of plasma treatment time are shown in Fig. 3-8 – Fig. 3-9. VTH is defined as the gate voltage that yields a drain current (IDS) of 100 nA , where IDS = 100 nA × (W/L). As shown in Fig. 3-8, the poly-Si TFTs with NH3 plasma pre-SPC-treatment have the largest VTH and the lowest Gm_max. Besides, the poly-Si TFTs with NH3 plasma pre-SPC-treatment have even larger VTH and lower Gm_max than control sample without any NH3 plasma treatment. It has been revealed that although NH3 plasma pre-SPC-treatment before SPC annealing significantly shortens the a-Si film crystallization time, the average grain size of the device with NH3 plasma pre-SPC-treatment is smaller than that of the device without any plasma treatment [3.3]. In general, the smaller grain size usually leads to the worse device performance because of the larger amount of grain boundaries defects. Furthermore, even though some nitrogen and hydrogen radicals terminate the dangling bonds at the grain boundaries during plasma pre-SPC-treatment processing, the following SPC annealing at high temperature (600℃) will lead to the out-diffusion of nitrogen and hydrogen radicals. The passivation effect breaks since the nitrogen and hydrogen radicals release from the defect sites [3.1]. Hence, due to 1) the smaller grain size of the device with NH3 plasma pre-SPC-treatment, and 2) the out-diffusion of nitrogen and hydrogen radicals during high temperature SPC annealing, the poly-Si TFTs with NH3 plasma pre-SPC-treatment will have worse performance than control sample without any NH3 plasma treatment.

Moreover, the poly-Si TFTs with post-SPC-treatment or after-AA-treatment have substantial improvements of performance compared with control sample. The poly-Si TFTs have the smallest VTH with NH3 plasma after-AA-treatment. In addition, the poly-Si TFTs with NH3 plasma after-AA-treatment have higher Gm_max than those with post-SPC-treatment ones for plasma treatment time ≤ 30 min. I. W. Wu et al. demonstrated that the deep states, which originate from the dangling bonds at grain

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boundaries, degrade the threshold voltage and the subthreshold swing. The tail states, which originate from the strain-bond-related intra-grain defects, degrade the field-effect mobility and minimum leakage current [3.12]. According to the literature, we presume the improvements, including smaller VTH and higher Gm_max of the poly-Si TFTs come from the passivation effect by after-AA-treatment. Moreover, it has been revealed that gate oxide is the major diffusion path for plasma radicals, because radicals diffuse rapidly in SiO2. In contrast to SiO2, for the poly-Si thin film, Si dangling bonds in the gain boundaries act as traps rather than as paths of enhanced diffusion [3.13]. Even though the cross-sectional area of the SiO2 is small, radicals are directly guided along the SiO2 to the SiO2/poly-Si interface. By diffusing laterally within the SiO2, radicals effectively passivate the traps in the middle of the channel. Therefore, after-AA-treatment passivates channel traps not only by radicals diffusing vertically through the poly-Si channel, but also by radicals diffusing laterally through the gate oxide as shown in Fig. 3-10. Because After-AA-treatment additionally passivates traps by radicals diffusing laterally through the gate oxide, it has higher passivation efficiency than post-SPC-treatment. As a result, NH3 plasma after-AA-treatment is indeed a technique to effectively passivate the dangling bonds at grain boundaries (deep states) as well as the intra-grain traps (tail states).

For plasma treatment time > 30 min, the poly-Si TFTs with NH3 after-AA-treatment have smaller VTH but lower Gm_max compared with the samples with post-SPC-treatment. The degraded Gm_max may be attributed to the following mechanisms. Although after-AA-treatment passivates traps much more efficiently than post-SPC-treatment, the poly-Si TFTs with NH3 plasma after-AA-treatment suffer from heavier ion bombardment damage. During plasma treatment processing, bombardment by energetic ions may cause breakage of chemical bonds and damage the poly-Si channel [3.8]. Furthermore, ion bombardment may also lead to the

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generation of interface traps, degrade carrier transport and decrease the Gm_max. Due to the extra damage on the sidewall of the channel as shown in Fig. 3-11, after-AA-treatment results in heavier damage than post-SPC-treatment. Therefore, for plasma treatment time > 30 min, ion bombardment damage becomes the non-negligible mechanism for performance degradation for the samples with after-AA-treatment. For these reasons, the poly-Si TFTs with after-AA-treatment have lower Gm_max than those with post-SPC-treatment ones for plasma treatment time > 30 min. Since the poly-Si TFTs with NH3 plasma pre-SPC-treatment have even worse performance than control sample without any NH3 plasma treatment, we do not take results of the poly-Si TFTs with pre-SPC-treatment into account in the following discussions.

Fig. 3-12 and Fig. 3-13 illustrate IDS–VDS characteristics of n-channel poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment, and after-AA-treatment, respectively. At low VDS region, both of the poly-Si TFTs with post-SPC-treatment and after-AA-treatment exhibit better performance than control sample. As VDS is further increased, the kink effect has been measured in these poly-Si TFTs, and the kink effect is more significant for control sample than the samples with NH3 plasma post-SPC-treatment or after-AA-treatment. The slopes of IDS–VDS characteristics for VDS from 3 V to 6 V are shown in Fig. 3-14 and Fig. 3-15. The steeper slope indicates the kink effect more obviously. According to these results, the longer NH3 plasma treatment time can alleviate kink effect more effectively. Hence, we hypothesize that kink effect can be suppressed by NH3 plasma treatment because of the reduction of traps. There are several explanations for kink effect, which is related to traps, have been reported. M. Hack et al. claimed that it is the presence of grain boundaries or traps in the poly-Si that causes kink effect to be much more significant than in comparable single-crystal silicon counterparts [3.14].A. K. K.

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P. et al. demonstrated that due to grain boundaries, the local electric field near the irregular surface might be appreciably greater than the average electric field, which might initiate additional impact ionization [3.15]. Besides, B. Kim et al. indicated that the kink effect exists at the non-treated poly-Si TFTs do not appear at the surface-treated ones because the kink effect has been known to depend on the nature of surface states [3.16]. Thus, the reduction of traps by NH3 plasma treatment is a reasonable explanation for the suppression of the kink effect.

During processing of plasma, such as thin film deposition, plasma etching and plasma treatment, gate oxides are also subjected to plasma-induced damage. Due to the electron, ion and particle bombardment, the gate oxide may be weakened by plasma related processes [3.17]. On the contrary, H. C. Cheng et al. claimed that after NH3 plasma treatment, the oxide quality is improved because the nitrogen and hydrogen radicals in the oxide may strengthen the strained bonds and passivate the trap-states [3.2]. Nevertheless, the samples of the above-mentioned literatures were top gate structure, not bottom gate structure. In order to clarify the influences on bulk oxide quality for bottom gate poly-Si TFTs by NH3 plasma treatment, Fig. 3-16 and Fig. 3-17 show gate-leakage current characteristics of poly-Si TFTs. All samples with different plasma treatment time exhibit comparable gate-leakage current characteristics, which indicate the bulk oxide quality for bottom gate poly-Si TFTs are insensitive to NH3 plasma treatment with plasma power of 50 W.

3.3 Plasma Power Dependence

Fig. 3-18 – Fig. 3-20 illustrate IDS–VGS and Gm–VGS characteristics of n-channel poly-Si TFTs for control sample and the samples with NH3 plasma pre-SPC-treatment, post-SPC-treatment, and after-AA-treatment at VDS of 0.1 V, respectively. These poly-Si TFTs were exposed to NH3 plasma with power of 50 W or 200 W, and the

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plasma treatment time was 15 min. Threshold voltage (VTH) and maximum transconductance (Gm_max) as a function of plasma power are shown in Fig. 3-21 and Fig. 3-22. Compared with plasma power of 50 W, the poly-Si TFTs with plasma power of 200 W have lower VTH and higher Gm_max. The higher the plasma power, the better the performance of these poly-Si TFTs. Because nitrogen and hydrogen radicals have higher kinetic energy with plasma power of 200 W than those with 50 W ones, they reach poly-Si/SiO2 interface more easily. Consequently, plasma treatment with higher power passivates traps more efficiently compared with the lower one. Moreover, the poly-Si TFTs with NH3 plasma pre-SPC-treatment for both power of 50 W and 200 W have even worse performance than control sample. For plasma power of 50 W, due to higher passivation efficiency of after-AA-treatment, the poly-Si TFT with NH3 plasma after-AA-treatment has smaller VTH and higher Gm_max than that with post-SPC-treatment one. However, for plasma power of 200 W, the performance of the poly-Si TFTs are exactly the opposite to plasma power of 50 W ones. For plasma power of 200 W, although after-AA-treatment passivates traps much more efficiently than post-SPC-treatment, the poly-Si TFT with NH3 plasma after-AA-treatment suffers from heavier ion bombardment damage. Furthermore, ion bombardment damage becomes the non-negligible mechanism for the sample with NH3 plasma after-AA-treatment with plasma power of 200 W. Thus, for plasma power of 200 W, the poly-Si TFT with NH3 plasma after-AA-treatment has worse performance than that with post-SPC-treatment one.

Fig. 3-23 and Fig. 3-24 illustrate IDS–VDS characteristics of n-channel poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment, and after-AA-treatment, respectively. Both of the poly-Si TFTs with post-SPC-treatment and after-AA-treatment exhibit better performance than control sample at low VDS region. And the poly-Si TFTs with plasma power of 200 W have better performance

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than those with 50 W ones. The kink effect has been measured in these poly-Si TFTs as VDS is further increased. The slopes of IDS–VDS characteristics for VDS from 3 V to 6 V are shown in Fig. 3-25 and Fig. 3-26. The steeper slope indicates the kink effect more obviously. According to these results, the higher NH3 plasma power can alleviate kink effect more effectively. The suppression of the kink effect is more efficient for the samples with plasma power of 200 W than those with 50 W ones because of the reduction of traps.

Fig. 3-27 and Fig. 3-28 show the gate-leakage current characteristics of n-channel poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment, and after-AA-treatment, respectively. The poly-Si TFTs with plasma power of 200 W have lower gate-leakage compared with those with plasma of 50 W ones. Because radicals have higher kinetic energy with plasma power of 200 W than those with 50 W ones, they reach SiO2 and passivate traps more easily. In consequence, better bulk oxide quality for bottom gate poly-Si TFTs can be obtained by NH3 plasma treatment with higher plasma power. In other words, NH3 plasma treatment with plasma power of 200 W is a method to improve bulk oxide quality more effectively than the plasma treatment with power of 50 W.

3.4 Summary

In this chapter, the passivation effect of NH3 plasma treatment for bottom gate poly-Si TFTs is thoroughly studied. In section 3.2, the influences of different NH3 plasma treatment time are discussed. Compared with the control sample without any plasma treatment, pre-SPC-treatment degrades device performance; however, post-SPC-treatment and after-AA-treatment improve device performance. The poly-Si TFTs with NH3 plasma pre-SPC-treatment have even worse performance than control sample owing to the smaller grain size and the out-diffusion of radicals during high

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temperature SPC annealing. On the other hand, the poly-Si TFTs with after-AA-treatment ones exhibit the best performance than the counterparts. After-AA-treatment is the most efficient technique to passivate traps since after-AA-treatment additionally passivates traps by radicals diffusing laterally through the gate oxide. Unfortunately, the poly-Si TFTs with after-AA-treatment suffer from the heaviest ion bombardment damage than those with post-SPC-treatment ones. Thus, for plasma treatment time > 30 min, the samples with after-AA-treatment have lower Gm_max compared with the samples with post-SPC-treatment. In addition, longer plasma treatment time enhance performance and alleviate kink effect more effectively. And the bulk oxide quality is insensitive to the plasma with power of 50 W, because all samples with different plasma treatment time exhibit comparable gate-leakage current.

In section 3.3, the influences of different NH3 plasma power are systematically investigated. The higher the plasma power, the better the performance of these poly-Si TFTs. Higher plasma power enhance performance and alleviate kink effect more effectively. Because nitrogen and hydrogen radicals have higher kinetic energy with plasma power of 200 W than those with 50 W ones, they reach poly-Si/SiO2 interface more easily. However, plasma treatment with power of 200 W results in heavier ion bombardment damage than 50 W one. Thus, for plasma power of 200 W, the sample with after-AA-treatment has lower Gm_max than the sample with post-SPC-treatment. Moreover, the bulk oxide quality for the sample with plasma power of 200 W is better than the sample with 50 W based on the gate-leakage comparison.

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-10

-5

0

5

10

15

10

-11

10

-9

10

-7

10

-5 W/L = 10 m/10m V_DS = 0.1V Plasma Power = 50W control 15min 30min 60min 120min

V

_GS

(V)

I

DS

(A)

Pre-SPC

0

40

80

120

160 G

m

(nS)

Fig. 3-1 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma pre-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

-10

-5

0

5

10

15

10

-11

10

-9

10

-7

10

-5 W/L = 10m/10m V_DS = 0.1V Plasma Power = 50W control 15min 30min 60min 120min

V

_GS

(V)

I

DS

(A)

0

40

80

120

160 Post-SPC

G

m

(nS)

Fig. 3-2 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

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-5

0

5

10

15

10

-11

10

-9

10

-7

10

-5 W/L = 10m/10m V_DS = 0.1V Plasma Power = 50W control 15min 30min 60min 120min

V

_GS

(V)

I

DS

(A)

0

40

80

120

160 After-AA

G

m

(nS)

Fig. 3-3 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

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(a)

(b)

Fig. 3-4 Top-view of bottom gate poly-Si TFTs with plasma-induced hole traps in the gate oxide at the corner edge portions with (a) wide channel width and (b) narrow channel width.

Fig. 3-5 The transistor can be equivalent to flat plate transistor and corner edge transistor in parallel.

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-5

0

5

10

15

10

-11

10

-9

10

-7

10

-5

Post-SPC

W/L = 2V_DS = 0.1Vm/10m Plasma Power = 50W

I

DS

(A

)

V_GS (V) control 15min 30min 60min 120min

Fig. 3-6 IDS–VGS characteristics of poly-Si TFTs for the samples with 2 μm channel width with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

-10

-5

0

5

10

15

10

-11

10

-9

10

-7

10

-5

After-AA

W/L = 2V_DS = 0.1Vm/10m Plasma Power = 50W

I

DS

(A

)

V_GS (V) control 15min 30min 60min 120min Plasma Treatment Time 

Fig. 3-7 IDS–VGS characteristics of poly-Si TFTs for the samples with 2 μm channel width with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

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0

30

60

90

120

4

6

8

10

W/L = 10m/10m V_DS = 0.1V Plasma Power = 50W

V

TH

(V)

Plasma Treatment Time (min)

Pre-SPC Post-SPC After-AA

Fig. 3-8 Threshold voltage (VTH) as a function of plasma treatment time.

0

30

60

90

120

60

90

120

W/L = 10m/10m V_DS = 0.1V Plasma Power = 50W

G

m_ ma x

(nS)

Plasma Treatment Time (min)

Pre-SPC Post-SPC After-AA

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Fig. 3-10 NH3 plasma after-AA-treatment passivates channel traps not only by radicals diffusing vertically through the poly-Si channel, but also by radicals diffusing laterally through the gate oxide.

Ion Bombardment

Damage

Fig. 3-11 The extra damage on the sidewall of the channel for the poly-Si TFTs with NH3 plasma after-AA-treatment.

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0

2

4

6

0

4

8

12

16 Post-SPC

V_GS-V_TH=1V V_GS-V_TH=2V V_GS-V_TH=3V V_GS-V_TH=4V W/L = 10m/10m Plasma Power = 50W

I

DS

(



A)

V

_DS

(V)

control 15min 30min 60min 120min

Fig. 3-12 IDS–VDS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

0

2

4

6

0

4

8

12

16 After-AA

V_GS-V_TH=1V V_GS-V_TH=2V V_GS-V_TH=4V V_GS-V_TH=3V W/L = 10m/10m Plasma Power = 50W

I

DS

(



A)

V

_DS

(V)

Fig. 3-13 IDS–VDS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

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0

30

60

90

120

0.2

0.4

0.6

0.8 Post-SPC

Sl

op

e (



A/V)

Plasma Treatment Time (min)

V_GS-V_TH=1V V_GS-V_TH=2V V_GS-V_TH=3V

Fig. 3-14 Slopes of IDS–VDS characteristics (post-SPC-treatment) as a function of plasma treatment time (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

0

30

60

90

120

0.2

0.4

0.6

0.8 After-AA

Sl

op

e (



A/

V)

Plasma Treatment Time (min)

Fig. 3-15 Slopes of IDS–VDS characteristics (after-AA-treatment) as a function of plasma treatment time (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

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10

-9

10

-7

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-3 W/L = 10m/10m V_D = V_S = 0V Plasma Power = 50W

Post-SPC

I

G

(V)

V

_GS

-V

_TH

(V)

Fig. 3-16 Gate-leakage current characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

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10

-13

10

-11

10

-9

10

-7

10

-5

10

-3 W/L = 10m/10m V_D = V_S = 0V Plasma Power = 50W

After-AA

I

G

(V)

V

_GS

-V

_TH

(V)

Fig. 3-17 Gate-leakage current characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W, plasma treatment time = 15 min to 120 min).

(48)

-10

-5

0

5

10

15

10

-11

10

-9

10

-7

10

-5 control 50W 200W

V

_GS

(V)

I

DS

(A)

0

50

100

150

200

W/L = 10m/10m V_DS = 0.1V

Plasma Time = 15min

Pre-SPC

G

m

(nS)

Fig. 3-18 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma pre-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min).

-10

-5

0

5

10

15

10

-11

10

-9

10

-7

10

-5 W/L = 10m/10m V_DS = 0.1V

Post-SPC

control_50W 200W

V

_GS

(V)

I

DS

(A)

0

50

100

150

200 G

m

(nS)

Fig. 3-19 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min).

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-5

0

5

10

15

10

-11

10

-9

10

-7

10

-5 W/L = 10m/10m V_DS = 0.1V

After-AA

control_50W 200W

V

_GS

(V)

I

DS

(A)

0

50

100

150

200 G

m

(nS)

Fig. 3-20 IDS–VGS and Gm–VGS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min).

0

50

100

150

200

4

6

8

10

W/L = 10m/10m V_DS = 0.1V

V

TH

(V)

Plasma Power (W)

Pre-SPC Post-SPC After-AA Fig. 3-21 Threshold voltage (VTH) as a function of plasma power.

(50)

0

50

100

150

200

60

90

120

150

W/L = 10m/10m V_DS = 0.1V

G

m_m ax

(n

S)

Plasma Power (W)

Pre-SPC Post-SPC After-AA Fig. 3-22 Maximum transconductance (Gm_max) as a function of plasma power.

0

2

4

6

0

4

8

12

16 Post-SPC

V_GS-V_TH=1V V_GS-V_TH=2V V_GS-V_TH=3V W/L = 10m/10m

I

DS

(



A)

V

_DS

(V)

control 50W 200W V_GS-V_TH=4V

Fig. 3-23 IDS–VDS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min).

(51)

0

2

4

6

0

4

8

12

16 After-AA

V_GS-V_TH=1V V_GS-V_TH=2V V_GS-V_TH=3V V_GS-V_TH=4V W/L = 10m/10m

I

DS

(



A)

V

_DS

(V)

control 50W 200W

Fig. 3-24 IDS–VDS characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min).

0

50

100

150

200

0.2

0.4

0.6

0.8 Post-SPC

Sl

op

e (



A/V)

Plasma Power

Fig. 3-25 Slopes of IDS–VDS characteristics (post-SPC-treatment) as a function of plasma treatment time (plasma power = 50 W or 200 W, plasma treatment time = 15 min).

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0

50

100

150

200

0.2

0.4

0.6

0.8 After-AA

Sl

op

e (



A/

V)

Plasma Power

Fig. 3-26 Slopes of IDS–VDS characteristics (after-AA-treatment) as a function of plasma treatment time (plasma power = 50 W or 200 W, plasma treatment time = 15 min).

-5

0

5

10

15

20

25

10

-13

10

-11

10

-9

10

-7

10

-5

10

-3 W/L = 10m/10m V_D = V_S = 0V

Post-SPC

I

GS

(V)

V

_GS

-V

_TH

(V)

control 50W 200W

Fig. 3-27 Gate-leakage current characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma post-SPC-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min).

(53)

-5

0

5

10

15

20

25

10

-13

10

-11

10

-9

10

-7

10

-5

10

-3

After-AA

W/L = 10m/10m V_D = V_S = 0V

I

GS

(V)

V

_GS

-V

_TH

(V)

control 50W 200W

Fig. 3-28 Gate-leakage current characteristics of poly-Si TFTs for control sample and the samples with NH3 plasma after-AA-treatment (plasma power = 50 W or 200 W, plasma treatment time = 15 min).