MIXED-SCALING-ROTATION CORDIC (MSR-CORDIC) ALGORITHM AND
ARCHITECTURE FOR SCALING-FREE HIGH-PERFORANCE ROTATIOAL
OPERATIONS
Zhi-Xiu (Phil)
Lin andAn-Yeu (Andy)
Wu
Graduate Institute of Electronics Engineerin, and Departmentof
Electncal Engineering, National Taiwan UniversityTaipei, 106, Taiwan, R.O.C.
Contact people: Prof. An-Yeu (Andy) Wu, E-mail:
[email protected]
Abstract
In this paper, we' propose the Mrred-Scaling-Roiaiion CORDIC (MSR-CORDIC) algorithm which merges micro-rotation operation and scaling operation in conventional CORDIC algorithms to eliminate the overhead of the scaling operation. At the system architecture level, we propose the
Dora-Path-Seleciion (DPS) strategy for the tradeoff between hardware complexity and quantization error performance. In general, the CORDIC algorithms will suffer from the roundoff noise in fixed-wordlength implementations. We propose two schemes to control and reduce the impairment. Our simulation results show that MSR-CORDIC enhances the SQNR performance, computing speed (reducing the iteration number), and reduces the hardware complexity when compared with the newly proposed EEAS-CORDIC [4] Algorithm.
1. Introduction
The Coordinate Roiaiional Digital Compuier (CORDIC) algorithm is a well-known hardware-efficient iterative algorithm for the computation of elementary arithmetic functions such as trigonometric, hyperbolic, exponential, and logarithmic operations [I]. The CORDIC algorithm can be also applied to the rotation-based arithmetic functions, for example fast Fourier transformation (FFT), QRD-RLS filtering, Eigenvalue Decomposition (EVD), and Singular Value Decomposition (SVD).
In this paper, we propose a new scheme to enhance the CORDIC at both algorithmic and architectural levels. The proposed generalized MSR-CORDIC with N = 3 (total iteration number) and Nrpl = 3 (Number of Signed of Power Two terms) design has 21.98 dB improvements compared with EEAS-CORDIC with RT = 3 (total iteration number) [4]. Furthermore, we can save up 33.3% hardware complexity and speed up the computation hy 1.5 times than the EEAS-CORDIC,
while with better error performance.
The rest of the paper is organized as follows. We propose the MSR-CORDIC algorithm in Section 2 and show its system architecture in Section 3. The Data-Path-Selection strategy is
applied to tradeoff behueen the hardware consumption and SQNR performance. Then, in Section 4, we make some simulations and compare system performance. Finally, Section 5 concludes our work.
2. The Proposed MSR-CORDIC Algorithm In conventional CORDIC algorithms, the scaling factor is always greater than 1. Therefore, it is necessary to scale down the norm ofthe input vector to its initial value (say, unit circle), after the rotation mode is finished. Furthermore, the SQNR will be reduced due to the growth of the scaling factor. To alleviate the disadvantage of the SQNR reduction, the input vector has to keep as close as to unit circle in each iteration. Additionally, to avoid the overhead of the scaling operation, the product of the scaling factors must be equal to I ; equivalently,
np"
= I . To overcome these problems, the range of the scaling facton must be greater and less than I . Based on the idea, we reformulate the iterative arithmetic asF o r n = O , l , ...,
N
I. Rotation phase-
Elementory angle- Accumulotion angle z(n + I ) = z(n)+
on+,
11. Scalingphose - Scaling foctor (3) (4)- Product of the scaling factor
( 5 )
_ _
P",, = P. x P"4
End
Where p 8 , p ~ { - l , O , l } ; I and J denote the number of SPT terms of x(n) and y(n), referred to as the Extending Factor. NSp, is the sum of I and J;
6,
is the elementary angle and the initial value. pn+, denotes the product of the scaling factors in the n-th iteration. The initial value of is 1. N denotes the total number of iteration. 8, E {&I,..., S},
and S denotes the number ofmaximum shift.The proposed modified CORDIC algorithm is called
Mired-Scaling-Rotation CORDIC (MSR-CORDIC). The reason is that we now need not to perform the micro-rotation operation and scaling operations separately. Eqs. ( 1 - 5 ) show that the x(n+l) and y(n+l) are mrated and scaled simultaneously in one iteration. In the conventional CORDIC and EEAS-CORDIC algorithms, the norms of both schemes are enlarged after the micro-rotation operations. On the c o n t r a g in the proposed MSR-CORIDC algorithm, the factor
Pn
can be either greater or less than 1. By taking the advantage of the property ofP,,
two schemes are proposed to control the dynamic range efficiently. Some other interesting features ofthe proposed scheme are discussed below:I.
According toEq.
(2), the angles in MSR-CORDIC is much denser than conventional CORDIC and EEAS-CORDIC, hence, the MSR-CORDIC can reach the target angle with fewer iteration. We illustrate in Fig. I(d) by using two iterations. Furthermore, if we design the parameters, si, pi, appropriately so that both the quantization error of rotation angles and norms meet the system performance requirement at the same time; then the scaling operation can be avoid. Since we do not need the extra scaling operations, the MSR-CORDIC is faster in computational speed and the corresponding hardware cost is reduced.2 . In some applications, the rotation angles are larger than a/4, such as the twiddle factors in FFT. It is difficult for the conventional CORDIC to perform such the rotation angle. In MVR-CORDIC [Z], the authors utilize the pre-rotation strategy
to overcome the problem and have the improvement of error performance. However, extra hardware COSIS and also the
-
(SJ (dl
Fig. I Constellation of reachable points under the rotation process. ( 8 )
Conventional CORDIC with N = R, = 4. (b) EEAS-CORDIC with
maximum shifl m g e S = 4 and R, = 2. (c) MSR-CORDIC with I = 2, J =
I,andN= l . ( d ) M S R - C O R D I C w i t h I = 2 , J = I , a n d N = 2 f o r I i i S P . $ 3 with maximum shifl range S = 4 .
computing speed decreases. On the contrary, in the proposed MSR-CORDIC algorithm, the reachable angles are distributed from 0 to 2
a
3. VLSI Architecture of MSR-CORDIC
In this section, we will illustrate the generalized structure for the MSR-CORDIC algorithm and proposed the idea of Data-Path-Selection schemes 10 enhance the SQNR performance by using switches.
3. I Normal MSR-CORDIC Structure
Firstly, we reformulate the Iteration Equations of ( I ) as
x ( n + l ) = i f l , 2 - , , ,=, *(E+& /=I 2-<, y ( . ) ; ( 6 )
(7)
y ( n + I)=
ip,*-..&)+
&i-i I,2-" y(m). ,=,Both of x ( n t 1 ) and
? @ + I )
are linear combination of their prior x(n) and ?in). All the coefficients of x(n) and y(n) are power of two numbers with the signU ,
and U,, respectively. Hence, two Barrel %$er Arrays (BSAs) are used to perform shifting operations. The number of the output signal is NSp, in each BSA. To sum the outputs, 2(Nrp,-l) addisubtract operations must be performed. Take N,,, = 3 for example, all cascs are listed in Table 1. The architecture of Case 2 are shown in Fiq. 2(a).EEAS-CORDIC need hardware cost more 413 times than MSR-CORDIC. In other words, our design has less iteration number so as that the computing speed of the MSR-CORDIC is faster than EEAS-CORDIC.
C. SQNR Perforniance Analysis among the MSR-CORDIC Family with Nspt = 4
In this simulation, we compare the generalized and normal MSR-CORDIC with Nip, = 4. As expected (see Fiq. 5), the generalized MSR-CORDIC has best error performance at the penalty of the extra 4 switches. In normal MSR-CORDIC, the guidelines below will lead better SQNR performance.
a.
b.
Take both l a n d J a r e equal to Nsp,l 2, when Nrp, is even. Take I = (N+,,+I) 1 2, and J = I- I , when Ns9, is old.
D.
I'ariance Comparisonof SQNR, in our analysis. The variance are normalized as We investigate the 2"d-order statistical property, the variance
The simulation result shows that the error distribution is more compact as the mean of SQNR becomes higher. Furrhermore,
MSR-CORDIC algorithm is less sensitive to the kinds of
MSR-CORDIC architecture wirh the similar SQNR perjormance,
illustrated by Fiq. 6 .
5. Conclusions
In this paper, we proposed a novel CORLXC scheme, MSR-CORDIC algorithm. The key idea in this algorithm is to merge two operation modes to eliminate the scaling operation (scaling-free). In practical implementation, the proposed MSR-CORDIC can be appropriately applied to various DSP
systems, which require the high computational speed and angles are known in advance. In summary, based on our proposed algorithm, Dofa-Path-Seleclion strategy, and two searching schemes, OUI design can enhance SQNR performance of either
1"-order or 2"d-order statistical propenier.
References
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[3]
141
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