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國立交通大學

電子工程學系 電子研究所

碩 士 論 文

利用實驗驗證場效電晶體之汲極與源極之

遠距庫倫效應

Experimental Evidence for MOSFET S/D

Long-Range Coulomb Effects

研究生: 李致葳 Chih-Wei Lee

指導教授: 陳明哲 博士 Prof. Ming-Jer Chen

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利用實驗驗證場效電晶體之汲極與源極之

遠距庫倫效應

Experimental Evidence for MOSFET S/D

Long-Range Coulomb Effects

研究生: 李致葳 Chih-Wei Lee

指導教授: 陳明哲 博士 Prof. Ming-Jer Chen

國立交通大學

電子工程學系 電子研究所

碩士論文

A Thesis

Submitted to Department of Electronics Engineering & Institute of Electronics

College of Electrical and Computer Engineering National Chiao Tung University

in Partial Fulfillment of the Requirements for the Degree of

Master of Science in

Electronics Engineering October 2012

Hsinchu, Taiwan, Republic of China

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I

利用實驗驗證場效電晶體之汲極與源極之

遠距庫倫效應

研究生: 李致葳 指導教授: 陳明哲 博士

國立交通大學

電子工程學系 電子研究所碩士班

摘要

由近年研究得知,元件尺寸縮減時電子遷移率會伴隨遞減,這也指出了有 額外的碰撞機制存在,並且此機制會對下一世代的元件造成很大的影響。因此本 篇論文主旨係利用實驗萃取額外遷移率之溫度係數,進而探討N型超短通道場效 電晶體下的散射機制。研究內容主要為我們第一次提出實驗證據對於當元件實際 通道長度小於 40 奈米會被存在於高濃度的源極與汲極的電漿電子所造成的遠距 庫倫散射機制所影響。這一系列的的研究方法為透過載子遷移率的溫度效應以及 利用二維模擬器對元件建立的模型來取得重要參數。此外,我們也提供了另一項 證據,是我們在大汲極電壓下量測到的轉導值與文獻中考慮遠距庫倫效應下的模 擬值相符。

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II

Experimental Evidence for MOSFET S/D

Long-Range Coulomb Effects

Student: Chih-Wei Lee Advisor: Dr. Ming-Jer Chen

Department of Electronics Engineering and Institute of Electronics

National Chiao Tung University

Abstract

Electron mobility degradation is currently encountered in highly scaled devices. This means that additional scattering mechanisms exist and will become profoundly important in next generation of devices. The aim of this work is to, for first time, present experimental evidence for the existence of long-range Coulomb effects due to plasmons (collective behaviors of fluctuating dipoles) in high-density source/drain (S/D) of MOSFETs, particularly for the metallurgical channel length less than about 40 nm. This is obtained through temperature-dependent mobilities via TCAD-based inverse modeling. Other evidence is further produced in terms of the measured transconductance at high drain voltage, which is comparable with that of sophisticated simulations in the literature taking into account long-range Coulomb interactions.

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III

Acknowledgements

感謝所有曾經幫助我的所有人。

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IV

Contents

Chinese Abstract ... I Abstract ... II Acknowledgements ... III Contents ... IV Figure Captions ... VI Table Captions ... IX

Chapter 1 Introduction

... 1

Chapter 2 Experiment

... 3 2.1 C-V Fitting ... 3

2.2 Measurement Method and Experimentally Assessed Effective Inversion-Layer Mobility... 4

Chapter 3 Inverse Modeling

... 6

3.1 Drift-diffusion Model ... 6

3.2 Calculation of Inversion Layer Charge Density ... 8

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V

Chapter 4 Analysis and Discussion

... 12

4.1 Additional Mobilities ... 12

4.2 Main Source of Mobility Degradation in Short-channel Device ... 13

4.3 Evidence of Long-range Coulomb Interactions ... 15

Chapter 5 Conclusion

... 16

References

... 17

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VI

Figure Captions

Figure 1.1 Schematic of electron transport under long-range Coulomb interactions with S/D plasmons. ... 19 Figure 1.2 Flowchart of inverse modeling in this work. ... 20

Figure 2.1 Temperature-dependent terminal currents at Vd=0.05V versus Vg for

Lg=1μm. ... 21

Figure 2.2 Temperature-dependent terminal currents at Vd=0.05V versus Vg for

Lg=65nm. ... 22

Figure 2.3 Temperature-dependent terminal currents at Vd=0.05V versus Vg for

Lg=50nm. ... 23

Figure 2.4 Comparison of the measured and simulated gate capacitance versus gate voltage. ... 24 Figure 2. 5 TEM image of the sample. ... 25 Figure 2.6 The schematic diagram for current flow of nMOSFETs with large gate

tunneling current. Besides, IS<0 and Id>0. ... 26

Figure 3.1 Measured and simulated Ich versus Vg at T=292K and Vd=0.05 and 1V. ... 27

Figure 3.2 Measured and simulated Ich versus Vg at T=330K and Vd=0.05 and 1V. .... 28

Figure 3.3 Measured and simulated Ich versus Vg at T=360K and Vd=0.05 and 1V. ... 29

Figure 3.4 Measured and simulated Ich versus Vg at T=380K and Vd=0.05 and 1V. ... 30

Figure 3.5 Calibrated 2D simulation structure for Lg=1μm and hence Lm=1μm. WD is

the width of the mid-channel depletion region. ... 31

Figure 3.6 Calibrated 2D simulation structure for Lg=65nm and hence Lm=48nm. WD is

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VII

Figure 3.7 Calibrated 2D simulation structure for Lg=50nm and hence Lm=33nm. WD is

the width of the mid-channel depletion region. ... 33

Figure 3.8 The free electron density under the surface 30nm at one position of the channel region. ... 34

Figure 3.9 The schematic diagram for inversion layer charge density of metallurgical length Lm=1μ m. ... 35

Figure 3.10 The schematic diagram for inversion layer charge density of metallurgical length Lm=48nm. ... 36

Figure 3.11 The schematic diagram for inversion layer charge density of metallurgical length Lm=33nm. ... 37

Figure 3.12 The calculated Ninv along the channel direction under interface 30nm for Lm = 1μm at T= (a) 292K, (b) 330K, (c) 360K, and (d) 380K. ... 38

Figure 3.13 The calculated Ninv along the channel direction under interface 30nm for Lm = 48nm at T= (a) 292K, (b) 330K, (c) 360K, and (d) 380K. ... 40

Figure 3.14 The calculated Ninv along the channel direction under interface 30nm for Lm = 33nm at T= (a) 292K, (b) 330K, (c) 360K, and (d) 380K. ... 42

Figure 3.15 Simulated Ninv versus gate voltage. ... 44

Figure 3.16 Simulation structure for Rsd assessment. ... 45

Figure 3.17 Simulated Rsd versus Vg at T=292K. ... 46

Figure 3.18 Terminal currents for short-channel device versus Vg at (a)Vb=0V and (b)Vb=-0.4V. ... 47

Figure 3.19 The extracted Rsd by using the experimental method [13]. ... 48

Figure 3.20 Extracted temperature-dependent effective mobility versus Ninv for different Lm with Rsd = (a) 100Ω-μm and (b) 120Ω-μm. ... 49

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VIII

and 33nm with Rsd = (a) 100Ω-μm and (b) 120Ω-μm. ... 50

Figure 4.2 Extracted additional mobility at Ninv=1x1013cm-2 versus temperature with

Rsd as a parameter. The power-law coefficient γ is obtained by data fitting.

... 51

Figure 4.3 Extracted temperature-dependent μadd, extra versus Ninv with Rsd as a

parameter. ... 52

Figure 4.4 Extracted μadd, extra at Ninv=1x1013cm-2 versus temperature, along with

corresponding power-law coefficient γ. ... 53 Figure 4.5 Simulated conduction-band edge, subband levels, and Fermi level versus

position for Lm = 1μm at Vg = (a) 1V, (b) 1.2V, and (c) 1.5V. ... 54

Figure 4.6 Simulated conduction-band edge, subband levels, and Fermi level versus

position for Lm = 48nm at Vg = (a) 1V, (b) 1.2V, and (c) 1.5V. ... 55

Figure 4.7 Simulated conduction-band edge, subband levels, and Fermi level versus

position for Lm = 33nm at Vg = (a) 1V, (b) 1.2V, and (c) 1.5V. ... 56

Figure 4.8 Comparison of temperature power-law exponent of extracted μadd, extra and

simulated bulk phonon-limited mobility, plotted versus Ninv. ... 57

Figure 4.9 Comparison of measured transconductance in this work and simulated ones with and without Coulomb effects [1]. ... 58

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IX

Table Captions

Table 1 The length of the overlap region for different Lgate, and the metallurgical

channel length (Lm=Lgate-ΔL). ... 59

Table 2 The subband population for different metallurgical channel length at gate voltages of (a) 1V, (b) 1.2V, and (c) 1.5V. ... 60

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1

Chapter 1

Introduction

It is well known that the inversion layer mobility of nMOSFETs can be limited to three primary scattering mechanisms: (1) Coulomb impurity scattering due to ionized impurity atoms in substrate depletion region; (2) acoustic and optical phonon scattering in inversion channel region; and (3) surface roughness scattering at the

SiO2/Si interface. However, owing to the measured effective mobility degradation in

highly scaled devices, this means that additional scattering mechanisms exist. Additional scatterings can be generalized in terms of remote surface roughness, fixed oxide charge, remote Coulomb scattering, short-range Coulomb centers due to halo implant or pockets and/or defects near S/D, and remote phonon scattering due to surface optical (SO) phonons. In spite of so many additional scattering mechanisms, we only need to consider specific scattering mechanisms in short-channel device, which are absent in long-channel device since scattering coming from gate dielectrics above channel should be all the same for both devices.

So far, in the open literature dedicated to short-channelnMOSFETs, the origins of

mobility degradation remained controversial. While channel length is shrunk into the region of Thomas-Fermi screening length (like sub-40 nm device), electron interactions near highly doped source/drain (S/D) - channel interface can be viewed as the dynamic screening, resulting in the excitation plasmons emission or absorption, which in turn transfer the momentum to affect the current indirectly according to the published simulation results [1],[2]. In addition, since the channel doping concentration is significantly higher in deep submicron devices compared to long-channel devices due to the presence of halo doping, it is expected to result in higher transversal fields and degraded mobility in short-channel devices [3]. Besides,

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2

the mobility degradation of short-channel device is also attributed to process-induced defects located near the source and drain junctions [4],[5]. Moreover, 2D charge sharing from S/D is also not neglected in short-channel device [3],[6], but it can be excluded in this work because the halo implant is used in our device sample under study.

Of degradation mechanisms mentioned above, the most challenging stems from long-range Coulomb interactions between electrons in channel and plasmons in such high-density regions as gate, source, and drain [1],[7]. However, in the past, the understanding of such long-range effects was primarily through sophisticated simulations [1],[7]. Only recently, we experimentally separated gate-plasmon-limited mobility [8], which can provide evidence for the interaction between channel electrons and gate plasmons.

In this work, we further present experimental evidence for another interaction between channel electrons and S/D plasmons (see Figure 1.1). The methodology is shown in Figure 1.2.

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3

Chapter 2

Experiment

N-channel devices under study were fabricated in a conventional manufacturing process with different channel width (W) and length (L) of W/L=1/1 μm,

W/L=1/0.065 μm and W/L=1/0.05 μm. In this process, SiO2 film was thermally

grown on (001) surface, followed by NO annealing. Figure 2.1 to Figure 2.3 show I-V

characteristics of device measured at Vd=0.05V for different temperatures (T = 292,

330, 360, and 380K).

2.1 C-V Fitting

We used ICS software to control HP4284 while measuring C-V characteristics. The

C-V measurement was performed on a 10μm 1μm device. Corresponding process parameters can essentially be obtained by fitting the measured gate capacitance versus

gate voltage (Cg-Vg) as shown in Figure 2.4. This was realized with the use of a

self-consistent Schrödinger and Poisson’s equations solver. Two such solvers were cited: one named Schred [9] and the other in the team’s work [10]. Obviously, the two

sources [9],[10] are consistent each other in the data fitting. Although Cg-Vg data at

high gate voltages were seriously distorted due to the use of ultrathin gate oxide where the direct tunneling current is pronouncedly large, the fitting was successfully

done in the remaining regions, leading to n+ polysilicon doping concentration =

11020 cm-3, gate oxide (SiO2) physical thickness = 1.27 nm, and p-type substrate

doping concentration = 41017 cm-3. In addition, the TEM of the device also shows

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4

2.2 Measurement Method and Experimentally

Assessed Effective Inversion-Layer Mobility

In the measurement method, the conventional inversion-layer mobility is usually extracted according to

 

 

 

g inv d g d g eff V qN I V V I W L V     (2.1)

 

d g d d V V I G (2.2)

where Gd is drain conductance. When Ig is small sufficiently, Gd can be presented by

c h d

I V

, and the channel current (Ich) should be the same as drain current (Id) and source

current (Is). However, while gate oxides are thin enough to encounter direct tunneling

current in long channel device, high gate leakage current would affect the accurate

determination of drain conductance (Gd ). Hence, the Gd is difficult to define simply

by s d I V or d d I V .

By following the experimental work by Takagi, et al. [11], we can know that while

gate oxide thicknesses are quite thin, the amount of gate current (Ig) affects source

current (Is) and drain current (Id), giving rise to the opposite sign. The schematic

diagram of current flow in MOSFETs with high gate leakage current is shown in

Figure 2.6 and Is and Id can be written as

GS channel S

I

I

I

(2.3) GD channel D

I

I

I

(2.4)

where IGS and IGD are the current from the source to the gate and the current from the

drain to gate, besides Is<0 and Id>0. Figure 2.6 illustrated that Is is larger than the

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5

gate(IGS), but Id is smaller than the current from channel to gate (Ich) because the

current tunnels from drain into gate (IGD). When Vd is sufficiently small, the IGS must

be the same as the IGD, hence the channel current can be defined as

2 s d channel I I I   .

Therefore, inversion layer (channel) mobility is measured by

 

 

 

 

g inv d g s g d g eff V qN I V V I V I W L V     2 ) (  (2.5)

Considering the difference between Lmask and the metallurgical channel length Lm, as

well as the issue about the parasitic source/drain resistance (Rsd), Eq.(2.5) could be

defined more accurately by

 

 

g inv mask ch g eff V qN L L R V  1     (2.6) sd s d ds ch R I I V R    2 (2.7)

where Lmask is the gate length on the polysilicon etch mask: Lmask Lgate. Lm=

Lmask-ΔL, where ΔL is the length of the overlap region between the source/drain

implant straggle and diffusion. Table 1 shows the overlap length for different Lgate.

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6

Chapter 3

Inverse Modeling

In this section, we make use of a TCAD tool named Sentaurus to reproduce Ich-Vg,

especially for the subthreshold conduction. This procedure is so-called inverse

modeling. First, we use the parameters which is got from C-V fitting: n+ polysilicon

doping concentration Npoly (= 11020 cm-3), gate oxide (SiO2) physical thickness tox (=

1.27 nm), and p-type substrate doping concentration Psub (= 41017 cm-3). Second, we

add two extra peak doping impurities: the source/drain extension Nsde and the halo

implant Phalo. Remarkably, a fairly good fitting was achieved for different gate lengths,

different temperatures, and different drain voltages, all with the same source/drain

extension doping concentration Nsde (= 4.95 1020 cm-3) and halo implant Phalo (=

2.5 1019

cm-3). Figure 3.1 to Figure 3.4 show Ich-Vg fitting results. Ich-Vg calibration

leads to device doping profiles for Lm=1μm, 48nm and 33nm as shown in Figure 3.5

to Figure 3.7. Corresponding extension overlap and hence the metallurgical channel

length Lm can be drawn.

TCAD further delivers the inversion-layer charge density qNinv as well as the

source/drain series resistance Rsd . The method we extracted those parameters will be

illustrated clearly as follows. Also, we will introduce the physical model (drift-diffusion) we used in above calibration.

3.1 Drift-diffusion Model

The drift-diffusion model is widely used for the simulation of carrier transport in semiconductors and is defined by the Poisson equation and continuity equations. The

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7

three governing equations for charge transport in semiconductor devices are Poisson equation and the electron and hole continuity equations. Poisson equation is:

trap A D

N

N

n

p

q

(

)

(3.1)

Where  is the permittivity, q is the elementary electronic charge, n and p

are the electron and hole densities, ND is the concentration of ionized donors, NA

is the concentration of ionized acceptors, and trap is the charge density contributed

by traps and fixed charges.

The electron and hole continuity equations are

t n q qR jn net        (3.2) t p q qR jp net         (3.3)

where Rnet is the net electron–hole recombination rate, jn

is the electron current

density, and jp

is the hole current density.

Combining equation 3.1~ equation 3.3, we can derive current densities for electrons and holes as given by:

n n n

nq

j

(3.4) p p p

pq

j

(3.5)

where n and p are the electron and hole mobilities, and n and  p are the

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8

3.2 Calculation of Inversion Layer Charge

Density

In this section, we will introduce the method we calculated inversion layer density from TCAD calibration model. However, we want to explain why we don’t use the same method as we used in extraction for additional mobility from gate plasmons in long-channel device [8]. From Figure 3.5 to Figure 3.7, we can observe that when

channel length is shrunk, the substrate doping concentration under the SiO2/Si

interface is obviously larger. This is due to the halo implant Phalo in short-channel

device. The altered substrate doping concentration may influence the inversion layer density directly and further bring about mobility degradation [3]. Consequently, 1D simulator [10] is not enough in this work. Instead, we use 2D simulator TCAD [12] to calculate inversion charge layer density involving the halo implant effect.

First, we use the calibration model to see the free electron density in vertical direction as shown in Figure 3.8. Then we integrate the electron density vertically under the oxide/substrate interface to 30nm deep, which is the quantum confinement

region. So, the area under the e-density curve in Figure 3.8 is the Ninv at this x position.

Then we cut Lm=1μm, 48nm and 33nm devices into many pieces to do the integration,

and in order not to contact the source/drain extension in the calculation, we only counted the channel between them. The region we made the calculation is between two dashed lines which is depicted in Figure 3.9 to Figure 3.11. After that, we did the same calculation for different gate voltages from 0V to 1.8V and temperatures from 292K to 380K. Corresponding inversion layer charge density results are shown in

Figure 3.12 for Lm=1μm, Figure 3.13 for Lm=48nm and Figure 3.14.for Lm=33nm.

Since the Ninv for short-channel device is not a constant value, unlike the long-channel

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9

integrated the Ninv along the channel and then divided the channel length. Finally, we

get the Ninv for Lm=1μm ,48nm and 33nm versus gate voltage as shown in Figure 3.15,

which is the Ninv mentioned in the mobility calculation in Euation 2.6.

3.3

Extraction of Parasitic

Source/Drain

Resistance

Since the parasitic resistance cannot be neglected in short channel device, we will explain the method we use in this work. First, we used the calibration model from TCAD simulation as shown in Figure 3.5 to Figure 3.7. Then, we only retained the drain region and constructed a metal contact beneath the oxide/substrate interface to 1 and 3nm deep. For this metal contact, one side connects the device and the other side is grounded as shown in Figure 3.16. After that, device is operated at drain voltage of 0.05V. Hence, we can get the current flow into the metal contact when we applied

gate voltage. Therefore, we can derive Rsd as below:

I V Rsd

2 . (3.6)

Figure 3.17 shows the Rsd under various bias conditions from 0.8V to 1.8V with the

values of around 100~110Ω -μ m.

Besides, we also provide another calculation method for Rsd extraction. The

method of extracting parasitic source/drain resistance ( Rsd ) is well described

elsewhere [13]. The Rsd can be derived as follows. For the intrinsic MOSFET

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10 ) )( 2 ( gs th ds ds sd d m ox d V V V V R I L W C I       (3.7)

The constant mobility can be achieved with two sets of bias conditions:( Vbs1

gs V , Vbs1 th V ) and ( Vbs2 gs V , Vbs2 th V ), where Vbs2 gs V = Vbs1 gs V +(1/ana -1)( Vbs1 th V - Vbs2 th V ). We can get Rsd as below ) ( ) ( 2 1 1 2 bs bs bs bs V th V th ds ana V d V d sd V V V I A I B R     (3.8) where ds V th V gs V V V A bs bs

5 . 0 1 1    , and ds ana V th V th ana V gs V V V V B bs bs bs    1) 0.5 1 ( 2 1 1      .

In modern MOSFET with thin oxide, α is close to 1, and Vbs1 and Vbs2 represent two

different back biases. Hence, mobility ana andEeff _ana can be analytical written

as ) )( 5 . 0 ( gs th ds ds sd d d ox m ana I R V V V V I WC L       (3.9) OX ana B ana FB ana th ana gs ana eff T V V V E     3 2 1 ) 1 1 ( _       (3.10)

While minimizing the error between μ ana and μ universal as described in [13]. Herein,

ana

 is approximated through iteration to minimize its error. Figure 3.18 shows the

I-V curves for short-channel devices where Vbs1 =0V and Vbs2 = -0.4V. The result for

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11 ana

 = 0.33, which is reasonable and consistent with the value (ana 1/2~1/3) used

in [13]. Also, the Rsd value obtained by using this method is reasonably consistent

with the extracted one (Rsd =120Ω-μm) in [14]. Thus, we use Rsd =100~120Ω-μm to

calculate the mobility for short-channel device.

According to inverse modeling, the extension overlap and hence the metallurgical

channel length Lm are easy to obtain. Combining the inversion layer charge density

Ninv and source/drain resistance Rsd , the measured effective mobility (μ eff) are

obtained as demonstrated in Figure 3.20 versus inversion layer density Ninv for

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12

Chapter 4

Analysis and Discussion

With the inverse modeling in Chapter 3, we extracted the mobility with Rsd

=100~120Ω -μ m for different metallurgical channel length Lm of 1μ m, 48nm and

33nm. In Figure 3.20 we found the mobility degradation in short-channel device. Due to the controversial mechanism for the mobility degradation in short-channel device, we want to use the temperature-dependent experimental method as in [8] to determine

the main source of degradation. First, we extracted additional mobility add (48nm )

and add (33nm) of short-channel device with respect to long-channel one (Lm=

m), and further obtained their temperature dependencies at high Ninv (= 1x1013 cm-2).

Besides, we also extracted the extra additional mobility add ,extra and decided the

main source of this scattering mechanism. Moreover, we further provided an important evidence to verify our hypothesis about this additional scattering mechanism.

4.1 Additional Mobilities

While comparing measured effective electron mobility ( eff ) between the

long-channel and short-channel device shown in Figure 3.20, additional scattering in short-channel device can be dealt with using Matthiessen’s rule which essentially is

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13 ) ( 1 ) ( 1 ) ( 1 LC SC SC eff eff add      (4.1)

where SC and LC mean short-channel and long-channel, respectively. Figure 4.1

shows the extracted temperature-dependent additional mobility versus Ninv for Lm=48

and 33nm with Rsd = 100 to 120 Ω-μm. Note that the devices under study are all

characterized by the same oxide thickness, so it is expected that scattering coming

from above channel should be the same. It can be seen that additional mobility for Lm

= 48 nm add (48nm ) increases with Ninv, whereas for Lm = 33nm add (33nm )

exhibits a saturating trend which dominates in both cases of Rsd . We further

extracted additional mobility at Ninv=1x1013cm-2 versus temperature with Rsd as a

parameter. In addition, we also provided a temperature-coefficient γ to clarify the temperature-oriented trend, there is a relationship between the additional mobility and temperature as follows:

add

T

(4.2)

Apparently, corresponding temperature dependencies are also opposite to each other:

γ = 0.37~0.55 for Lm = 48nm and γ = -0.13~-0.17 for Lm = 33nm as shown in Figure

4.2 for varying Rsd .

4.2 Main Source of Mobility Degradation in

Short-Channel Device

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14

degradation for short-channel device. Among them, S/D plasmons, bandgap narrowing, short-range Coulomb scattering due to halo implant or pockets and defects near S/D are believed to be the most probable culprits to degrade the performance

[1]-[5]. Additional mobility of Lm = 48 nm increases with temperature, consistent with

the result of [3] about mobility degradation in short-channel device, indicating that the responsible mechanisms are those of short-range Coulomb centers (due to halo implant or pockets [3] and/or defects near S/D [4],[5]).

As to Lm = 33 nm, it exhibits a slight decrease with temperature (Figure 4.2),

suggesting other mechanisms. The corresponding mobility component can be written as: ) 48 ( 1 ) 33 ( 1 1

, extra add nm add nm

add

  (4.3)

The resulting add ,extra is plotted in Figure 4.3 versus Ninv. And in Figure 4.4 we

present the power-law relation of add ,extra versus temperature at Ninv = 1x10

13

cm-2.

Surprisingly, temperature-dependent add ,extra in Figure 4.4 is satisfactorily close to

that of gate-plasmon-limited ones [8]. The corresponding γ has a value of –0.69 to -0.83. Here, we have to rule out the mechanism of 2D charge sharing from S/D [3],[6].

The reasons are twofold. First, although the width WD of simulated substrate

depletion region increases with decreasing Lm (Figure 3.5 to Figure 3.7), which may

act as a signature of 2D charge sharing, the subband separation does not appear to decrease but increase (see Table 2), greatly contrary to [3],[6]. Here, we consider two lowest subbands as an estimation of population distribution versus energy. Meanwhile, this calculation is done for population for 1nm below surface. Figure 4.5 to Figure 4.7 show the subband energy below surface 1nm for gate voltage from 1.0V~1.5V. This obvious difference is simply because in our work, the halo implant is used and its

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15

effect is enhanced with decreasing Lm. Second, we conducted bulk-phonon-limited

mobility simulation using the simulation program [7],[10]. The resulting γ lies at a

value from -1.5 to -1.6, which is much more negative than that of add ,extra (Figure

4.8). It is therefore argued that only for Lm less than about 40 nm can long-range

Coulomb effects become noticeable.

4.3

Evidence

of

Long-Range

Coulomb

Interactions

Finally, in Figure 4.9 we quote simulated transconductance at Vd = 1.0 V and Vg of

0.75 and 1.0 V above threshold [1] versus Lm, for comparison with measured

transconductance at Vd = 0.8 and 1.0 V in this work. Evidently, the dimension of our

devices, which is carefully chosen to meet the criterion, lies across the activation point of long-range Coulomb effects. With above evidence, we further argue that the long-range Coulomb interactions would be the main factor for performance degradation in ultra-short devices.

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16

Chapter 5

Conclusion

In this work, TCAD-based inverse modeling has been carried out with aim reconstruct the process parameters. Consequently, interesting and useful results have been created. First, the overlap region for short-channel device can be accurately

determined. Also the halo implant Phalo, which has a significant impact on the

substrate doping concentration and further affect the inversion layer charge density, is also solved by calculating the free electron density in the channel region from 2D

simulation. Moreover, the parasitic source/drain resistance (Rsd ) is also extracted

from the calibration model. In addition, we also provide experimental method to

estimate the Rsd for the comprehensive analysis.

Second, the resulting temperature power-law exponent (γ) as extracted from our experimentally-determined additional mobility data points out that the long-range Coulomb interactions exist in the metallurgical channel length less than about 40 nm. Thus, experimental evidence of long-range Coulomb interactions has been drawn. Furthermore, underlying physical origins have all been distinguished for short channel device. Therefore, long-range Coulomb effect, which is not to be ignored in ultra-short devices, has been for the first time experimentally corroborated in the device samples under study.

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17

References

[1] M. V. Fischetti , S. Jin , T.-W. Tang , P. Asbeck , Y. Taur , S. E. Laux , M. Rodwell and N. Sano, “Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model,” J. Comput. Electron., vol. 8, p.60 , 2009.

[2] M. V. Fischetti and S.E. Laux, “Long-range Coulomb interactions in small Si devices. Part Ⅰ: Performance and reliability,” J. Appl. Phys., vol. 89, no. 2, pp. 1232-1248, January 2001.

[3] K. Rim, S. Naeasimha, M. Longstreet, A. Mocuta, and J. Cai, “Low field Mobility characteristics of sub-100 nm unstrained and strained si MOSFETs,” in IEDM

Tech. Dig. , pp. 43-46, 2002.

[4] Antoine Cros, Krunoslav Romanjek, Dominique Fleury, Samuel Harrison, Robin Cerutti, Philippe Coronel, Benjamin Dumont, Arnaud Pouydebasque, Romain Wacquez, Blandine Duriez, Romain Gwoziecki, Frederic Boeuf, Hugues Brut, Gerard Ghibaudo and Thomas Skotnicki, “Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling,” in IEDM Tech. Dig., pp. 663-666, 2006.

[5] Vincent Barral, Thierry Poiroux, Daniela Munteanu, Jean-Luc Autran, and Simon Deleonibus, ‘Experimental investigation on the quasi-ballistic transport: part II—backscattering coefficient extraction and link with the mobility,” IEEE Trans.

Electron Devices, vol. 56, no. 3, pp. 420-430, March. 2009.

[6] P.Packan, S.Cea, H.Deshpande, T.Ghani, M.Giles, O.Golonzka, M.Hattendorf, R.Kotlyar, K.Kuhn, A.Murthy, P.Ranade, L.Shifren, C.Weber and K.Zawadzki, “High performance Hi-K + metal gate strain enhanced transistors on (110) Silicon,” in IEDM Tech. Dig., pp. 63-66, 2008.

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18

Effective electron mobility in thin-oxide structures,” J. Appl.Phys., vol. 89, no. 2, pp. 1232–1250, Jan. 2001.

[8] Ming-Jer Chen, Li-Ming Chang, Shin-Jiun Kuang, Chih-Wei Lee, Shang-Hsun

Hsieh, Chi-An Wang, Sou-Chi Chang, and Chien-Chih Lee,

“Temperature-oriented mobility measurement and simulation to assess surface roughness in ultrathin-gate-oxide ( ~1 nm) nMOSFETs and Its TEM evidence,”

IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 949-955, April. 2012.

[9] Schred, http://nanohub.org/resources/schred.

[10] M. J. Chen, C. C. Lee, and K. H. Cheng, “Hole effective masses as a booster of self-consistent six-band k‧p simulation in inversion layers of pMOSFETs,”

IEEE Trans. Electron Devices, vol. 58, pp. 931-937, April 2011.

[11] S. Takagi and M. Takayanagi, “Experimental evidence of inversion-layer mobility lowering in ultrathin gate oxide metal-oxide-semiconductor field-effect-transistors with direct tunneling current,” Jpn. J. Appl. Phys., vol. 41, pt. 1, no. 4B, pp. 2348-2352, Apr. 2002.

[12] TCAD. http://www.synopsys.com/Tools/TCAD/Pages/default.aspx.

[13] D.W. Lin, M. L. Cheng, S.W.Wang, C. C.Wu, and M. J. Chen, “A novel method of MOSFET series resistance extraction featuring constant mobility criteria and mobility universality,” IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 890–897, Apr. 2010.

[14] K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, "Improved split C-V method for effective mobility extraction in sub-0.1-μm Si MOSFETs," IEEE

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19

Figure 1.1 Schematic of electron transport under long-range Coulomb interactions

with S/D plasmons.

oxide

N

+

N

+

S/D plasmons

(31)

20

Figure 1.2 Flowchart of inverse modeling in this work.

CV & IV fitting

Evidence for Long-range

Coulomb Interactions

from S/D

Inverse Modeling

Doping Profile, Ninv,

Rsd

Effective Mobility

Additional Mobility and

Temperature Dependence

Power-Law

To Determine Main

Source of Mobility

Degradation for Short

(32)

21 0.0 0.5 1.0 1.5 2.0 -5.0x10-6 0.0 5.0x10-6 1.0x10-5 1.5x10-5 2.0x10-5 2.5x10-5 3.0x10-5 3.5x10-5 4.0x10-5

I

b

I

g

I

d C u rr e n t (A ) Gate Voltage (V) T=292K T=330K T=360K T=380K

I

s Vd=0.05V

L

g

=1

m

Figure 2.1 Temperature-dependent terminal currents at Vd=0.05V versus Vg for

(33)

22 0.0 0.5 1.0 1.5 2.0 0.0 5.0x10-5 1.0x10-4 1.5x10-4 2.0x10-4 2.5x10-4 Vd=0.05V

L

g

=65nm

I

g

&I

b

I

s

&I

d C u rr e n t (A ) Gate Voltage (V) T=292K T=330K T=360K T=380K

Figure 2.2 Temperature-dependent terminal currents at Vd=0.05V versus Vg for

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23 0.0 0.5 1.0 1.5 2.0 0.0 5.0x10-5 1.0x10-4 1.5x10-4 2.0x10-4 2.5x10-4 V d=0.05V L g=50nm

Cu

rr

en

t (

A)

Gate Voltage (V) T=292K T=330K T=360K T=380K

I

s

&I

d

I

g

&I

b

Figure 2.3 Temperature-dependent terminal currents at Vd=0.05V versus Vg for

(35)

24 -3 -2 -1 0 1 0.0 0.4 0.8 1.2 1.6 2.0 C ap ac ita nc e (F/ cm 2 ) Gate Voltage (V) Experiment Schred [9] Simulation [10] W/L=10/1m N poly=1e20cm -3 P sub=4e17cm -3 t ox=1.27nm

Figure 2.4 Comparison of the measured and simulated gate capacitance versus gate voltage.

(36)

25

Figure 2. 5 TEM image of the sample.

<001>

(37)

26

Figure 2.6 The schematic diagram for current flow of nMOSFETs with large gate

(38)

27 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 Lm (nm) 1000 48 33 Exp TCAD

C

ha

nn

el

C

ur

re

nt

(A

)

T=292K Gate Voltage (V) W=1m tox=1.27nm Nsde=4.95e20cm-3 Phalo=2.5e19cm-3 Psub=4e17cm-3 V d=1.0V V d=0.05V

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28 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 L m (nm) 1000 48 33 Exp TCAD

C

ha

nn

el

C

ur

re

nt

(A

)

T=330K Gate Voltage (V) W=1m tox=1.27nm Nsde=4.95e20cm-3 Phalo=2.5e19cm-3 Psub=4e17cm-3 V d=1.0V V d=0.05V

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29 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 L g (nm) 1000 65 50 Exp TCAD

C

ha

nn

el

C

ur

re

nt

(A

)

T=360K Gate Voltage (V) W=1m tox=1.27nm Nsde=4.95e20cm-3 Phalo=2.5e19cm-3 Psub=4e17cm-3 V d=1.0V V d=0.05V

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30 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 Lm (nm) 1000 48 33 Exp TCAD C ha nn el C ur re nt (A ) T=380K Gate Voltage (V) W=1m tox=1.27nm Nsde=4.95e20cm-3 Phalo=2.5e19cm-3 Psub=4e17cm-3 V d=1.0V V d=0.05V

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31

Figure 3.5 Calibrated 2D simulation structure for Lg=1μm and hence Lm=1μm. WD is

the width of the mid-channel depletion region.

W

D

=45.53nm

P-type substrate

Depletion edge

Spac er Spac er

Drain

Silicide

Silicide

Halo

Halo

Con t act Con t act

N

+

-Poly Gate

Source

Doping

Conc. (cm

-3

)

L

g

=1µm

L

m

≈1µm

(43)

32

Figure 3.6 Calibrated 2D simulation structure for Lg=65nm and hence Lm=48nm. WD

is the width of the mid-channel depletion region.

N

+

-Poly

Gate

W

D

=

57.27nm

Depletion edge

P-type substrate

Spacer

Spacer

Con

tact

Con

tact

Silicide

Silicide

Source

Drain

Halo

L

g

=65nm

Doping

Conc. (cm

-3

)

L

m

=48nm

(44)

33

Figure 3.7 Calibrated 2D simulation structure for Lg=50nm and hence Lm=33nm. WD

is the width of the mid-channel depletion region.

N

+

-Poly

Gate

W

D

=

65.75nm

Depletion edge

P-type substrate

Spacer

Space

r

Con

tact

Con

tact

Silicide

Silicide

Source

Drain

Halo

L

g

=50nm

Doping

Conc. (cm

-3

)

L

m

=33nm

(45)

34 -5.0x10-7 0.0 5.0x10-71.0x10-61.5x10-62.0x10-62.5x10-6 0.0 5.0x1019 1.0x1020 1.5x1020 2.0x1020 2.5x1020 L=65nm e D e n s it y ( cm -3 ) Y (cm) area=Ninv

Figure 3.8 The free electron density under the surface 30nm at one position of the channel region.

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35

Figure 3.9 The schematic diagram for inversion layer charge density of metallurgical

(47)

36

Figure 3.10 The schematic diagram for inversion layer charge density of metallurgical

(48)

37

Figure 3.11 The schematic diagram for inversion layer charge density of metallurgical

(49)

38 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013

Psub=4x1017cm-3 NSDE=4.95x1020cm-3Phalo=2.5x1019cm-3

N in v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V T=292K L m=1m (a) -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3P halo=2.5x10 19 cm-3 T=330K L m=1m N in v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (b)

Figure 3.12 The calculated Ninv along the channel direction under interface 30nm for

(50)

39 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3P halo=2.5x10 19 cm-3 T=360K L m=1m N in v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (c) -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3P halo=2.5x10 19 cm-3 T=380K L m=1m Nin v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (d)

Figure 3.12 The calculated Ninv along the channel direction under interface 30nm for

(51)

40 -0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 2.8x1013 P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3 P halo=2.5x10 19 cm-3 T=292K L m=48nm Nin v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (a) -0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 2.8x1013 T=330K L m=48nm P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3 P halo=2.5x10 19 cm-3 N in v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (b)

Figure 3.13 The calculated Ninv along the channel direction under interface 30nm for

(52)

41 -0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 2.8x1013 T=360K L m=48nm P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3 P halo=2.5x10 19 cm-3 N in v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (c) -0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 2.8x1013 T=380K L m=48nm P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3 P halo=2.5x10 19 cm-3 Nin v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (d)

Figure 3.13 The calculated Ninv along the channel direction under interface 30nm for

(53)

42 -0.02 -0.01 0.00 0.01 0.02 0.03 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 2.8x1013 T=292K L m=33nm P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3 P halo=2.5x10 19 cm-3 Nin v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (a) -0.02 -0.01 0.00 0.01 0.02 0.03 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 2.8x1013 Psub=4x1017cm-3 N SDE=4.95x10 20 cm-3 P halo=2.5x10 19 cm-3 T=330K Lm=33nm Nin v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (b)

Figure 3.14 The calculated Ninv along the channel direction under interface 30nm for

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43 -0.02 -0.01 0.00 0.01 0.02 0.03 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 2.8x1013 P sub=4x10 17 cm-3 N SDE=4.95x10 20 cm-3 P halo=2.5x10 19 cm-3 T=360K L m=33nm Nin v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (c) -0.02 -0.01 0.00 0.01 0.02 0.03 0.0 4.0x1012 8.0x1012 1.2x1013 1.6x1013 2.0x1013 2.4x1013 2.8x1013 T=380K Lm=33nm Psub=4x1017cm-3 N SDE=4.95x10 20 cm-3 P halo=2.5x10 19 cm-3 Nin v ( cm -2 ) X (m) Vg=0V Vg=0.3V Vg=0.6V Vg=0.9V Vg=1.2V Vg=1.5V Vg=1.8V (d)

Figure 3.14 The calculated Ninv along the channel direction under interface 30nm for

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44 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.0 5.0x1012 1.0x1013 1.5x1013 2.0x1013 2.5x1013

N

in v (

cm

-2 ) Gate Voltage (V) T=292K T=330K T=360K T=380K L m=1m L m=48nm L m=33nm

(56)

45

(57)

46 0.8 1.0 1.2 1.4 1.6 1.8 80 90 100 110 120 130

R

sd

(

 

m

)

Gate Voltage (V) V d=0.05V R

sd calculated by TCAD simulation

(58)

47 -2 -1 0 1 2 3 -2.0x10-5 0.0 2.0x10-5 4.0x10-5 6.0x10-5 8.0x10-5 1.0x10-4 1.2x10-4 1.4x10-4 Vd=0.05V Vbs1=0V C u rr e n t (A ) Gate Voltage (V) Ig Id Is Ib (a) -2 -1 0 1 2 3 -2.0x10-5 0.0 2.0x10-5 4.0x10-5 6.0x10-5 8.0x10-5 1.0x10-4 1.2x10-4 1.4x10-4 C ur re nt (A ) Gate Voltage (V) I g I d I s I b Vd=0.05V Vbs2=-0.4V (b)

Figure 3.18 Terminal currents for short-channel device versus Vg at (a)Vb=0V and

(59)

48 0.0 0.2 0.4 0.6 0.8 1.0 0 20000 40000 60000 80000 100000 Er r ([ cm 2 /(V *s ) ] 2 )R sd=123.1-m=0.330=700cm 2 /V*s

(60)

49

(a)

(b)

Figure 3.20 Extracted temperature-dependent effective mobility versus Ninv for

different Lm with Rsd = (a) 100Ω-μm and (b) 120Ω-μm.

sd S d ds ch g inv m ch g eff R I I V R V qWN L R V     2 ) ( ) ( ) 1 ( ) (  5 10 15 20 25 0 50 100 150 200 250 300 350 400 Vd=0.05V Rsd=100-m 1m 33nm 48nm E ff e c ti v e M o b il it y ( cm 2 /V s ) Ninv (x1012 cm-2) T=292K T=330K T=360K T=380K sd S d ds ch g inv m ch g eff R I I V R V qWN L R V     2 ) ( ) ( ) 1 ( ) (  5 10 15 20 25 0 50 100 150 200 250 300 350 400 Ef fe ct iv e M ob ili ty ( cm 2 /V s ) N inv (x10 12 cm-2) T=292K T=330K T=360K T=380K V d=0.05V R sd=120-m 1m 33nm 48nm

(61)

50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 0 100 200 300 400 500 600 700 R sd=100-madd(48nm)add(33nm) A dd iti on al M ob ili tyadd ( cm 2 /V s ) N inv(X10 12 cm-2) T=292K T=330K T=360K T=380K 1/add(SC)= 1/eff(SC)-1/eff(LC) SC:short channel LC:long channel (a) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 0 200 400 600 800 1000 1200 1400 SC:short channel LC:long channel R sd=120-madd(33nm)add(48nm) 1/add(SC)= 1/eff(SC)-1/eff(LC) Ad di tio na l M ob ili tyad d ( cm 2 /V s ) N inv(X10 12 cm-2) T=292K T=330K T=360K T=380K (b)

Figure 4.1 Extracted temperature-dependent additional mobility versus Ninv for Lm=48

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51 240 280 320 360 400 440 480 200 300 400 500 600 700 800 900 1000 1100 33nm device 48nm device       R sd=120-m R sd=120-m R sd=100-m R sd=100-m N inv=1x10 13 cm-2

add

T

A

dd

iti

on

al

M

ob

ili

ty

ad d (

cm

2

/V

s

) Temperature (K)

Figure 4.2 Extracted additional mobility at Ninv=1x1013cm-2 versus temperature with

(63)

52 5 10 15 20 25 300 400 500 600 700 800 900 1000 

add, extra=1/add(33nm)-1/add(48nm)

R sd=120-m R sd=100-m

add, e xt ra (

cm

2

/V

s

) N inv (x10 12 cm-2) T=292K T=330K T=360K T=380K

Figure 4.3 Extracted temperature-dependent μadd, extra versus Ninv with Rsd as a

(64)

53 240 280 320 360 400 440 480 450 500 550 600 650 700 750 800 850

add

T

N inv=1x10 13 cm-2 

add, extra=1/add(33nm)-1/add(48nm)

R sd=120-m R sd=100-m    

ad d , e xt ra ( cm 2 /V s ) Temperature (K)

Figure 4.4 Extracted μadd, extra at Ninv=1x1013cm-2 versus temperature, along with

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54 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 E21 S/D Extension S/D Extension B an d En er gy (e V) X (m) T=292K V g=1V Vd=0.05V EC EF E 11 E12 E13 E21 E22 Lm=1000nm E11 (a) -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 E11 S/D Extension Lm=1000nm T=292K Vg=1.2V Vd=0.05V EC EF E11 E12 E13 E21 E22 E21 S/D Extension Ba nd E ne rg y (e V) X (m) (b) -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 B an d En er gy (e V) X (m) T=292K Vg=1.5V Vd=0.05V EC EF E11 E12 E13 E21 E22 E 21 S/D Extension S/D Extension Lm=1000nm E 11 (c)

Figure 4.5 Simulated conduction-band edge, subband levels, and Fermi level versus

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55 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 E 21S/D Extension B an d En er gy (e V) X (m) T=292K Vg=1V Vd=0.05V EC EF E11 E12 E13 E21 E22 Spacer Spacer S/D Extension Lm=48nm E11 (a) -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 Ba nd E ne rg y (e V) X (m) T=292K V g=1.2V Vd=0.05V EC EF E 11 E12 E13 E21 E22 E21 S/D Extension Spacer Spacer S/D Extension Lm=48nm E11 (b) -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 B an d En er gy (e V) X (m) T=292K V g=1.5V Vd=0.05V E C EF E11 E12 E13 E21 E22 E 21S/D Extension Spacer Spacer S/D Extension Lm=48nm E11 (c)

Figure 4.6 Simulated conduction-band edge, subband levels, and Fermi level versus

數據

Figure  1.1  Schematic  of  electron  transport  under  long-range  Coulomb  interactions  with S/D plasmons
Figure  2.1  Temperature-dependent  terminal  currents  at  V d =0.05V  versus  V g   for  L g =1μm
Figure  2.3  Temperature-dependent  terminal  currents  at  V d =0.05V  versus  V g   for  L g =50nm
Figure  2.4  Comparison  of  the  measured  and  simulated  gate  capacitance  versus  gate  voltage
+7

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