Int J Adv Manuf Technol (2006) 31: 135–144 DOI 10.1007/s00170-005-0144-4
O R I G I N A L A RT I C L E
Chien-Wei Wu . W. L. Pearn
Bayesian approach for measuring EEPROM process capability
based on the one-sided indices C
PU
and C
PL
Received: 22 November 2003 / Accepted: 26 April 2005 / Published online: 16 March 2006
# Springer-Verlag London Limited 2006
Abstract The purpose of process capability analysis is to provide numerical measures on whether a process is capable of reproducing items meeting the manufacturing specifications. Capability analyses have received consider-able recent research attention and increased usage in process assessments and purchasing decisions. Most ex-isting research works on capability analysis focus on estimating and testing process capability based on the tra-ditional distribution frequency approach. In this paper, we propose a Bayesian approach based on the indices CPUand CPLto measure EEPROM process capability, in which the specifications are one-sided rather than two-sided. We obtain the credible intervals of CPUand CPLand develop a Bayesian procedure for capability testing. The posterior probability p, for which the process under investigation is capable, is derived. The credible interval is a Bayesian analog of the classical lower confidence interval. A process satisfies the manufacturing capability requirements if all the points in the credible interval are greater than the pre-specified capability level w. To make this Bayesian pro-cedure practical for in-plant applications, a real example of an EEPROM manufacturing process is investigated, demonstrating how the Bayesian procedure can be applied to actual data collected in the factories.
Keywords Bayesian approach . Credible interval . Process capability indices . Posterior probability
1 Introduction
In recent years, numerous process capability indices (PCIs), including Cp, Ca, CPU, CPL, Cpk, Cpm, and Cpmk, have received substantial research attention in quality assurance as well as statistical literatures. These indices have been popularly used in the manufacturing industry, providing measures on whether a process is capable of reproducing items meeting the quality requirements preset by the product designer. The use of PCIs in industry began in the United States in the early 1980s. Soon after, this explosion of use expanded into various industries, includ-ing automotive, semiconductor, and IC manufacturinclud-ing industries, to measure product qualities meeting the man-ufacturing specification. Examples include [6,10,12,21] and many others. These capability indices are convenient tools to the manufacturer for monitoring process quality, and a production department can trace and improve a poor process so that the quality level can be enhanced and the requirements of the customers can be satisfied. These indices are defined in the following (see [8,3,15]):
Cp ¼ USL LSL 6 ; Ca¼ 1 m j j d CPU¼ USL 3 ; CPL¼ LSL 3 ; Cpk¼ min USL 3 ; LSL 3 ; Cpm¼ USL LSL 6 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2þ Tð Þ2 q ; Cpmk ¼ min USL 3 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2þ Tð Þ2 q ; LSL 3 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2þ Tð Þ2 q 8 > < > : 9 > = > ;; where USL is the upper specification limit, LSL is the lower specification limit,μ is the process mean, σ is the process standard deviation (overall process variation), m=(USL+ C.-W. Wu (*)
Department of Industrial Engineering & Systems Management, Feng Chia University,
Taichung, Taiwan, R. O. C. e-mail: cweiwu@fcu.edu.tw W. L. Pearn
Department of Industrial Engineering & Management, National Chiao Tung University,
LSL)/2, d=(USL-LSL)/2, and T is the target value. While Cp, Ca, Cpk, Cpm, and Cpmk are appropriate measures for normal processes with two-sided manufacturing spec-ifications (which require both USL and LSL), CPU and CPLhave been designed particularly for processes with one-sided manufacturing specifications (which require only USL or LSL, but not both). In practice, the process mean and process standard deviation are usually unknown, but they can be estimated from a sample of n measurements {x1, x2,..., xn}. The most common estimates ofμ and σ are: x ¼1 n Xn i¼1 xi; s ¼ n 11 Xn i¼1 xi x ð Þ2 " #1=2 :
The current practice of measuring production quality by evaluating the point estimates of the capability indices have been criticized, since there is no sampling error assessment of these estimates. The sample estimate of the index calcu-lated from sample data has never been accurate. Therefore, the decisions made in concluding the capability measures directly from the sample estimate are unreliable. Existing methods for measuring production quality have focused on the traditional distribution frequency approaches. However, the sampling distributions are usually complicated, and this makes establishing the exact confidence interval difficult. An alternative approach for measuring process capability is to use the Bayesian method, by specifying a prior distri-bution for the parameter of interest, to obtain the posterior distribution of the parameter. Then, one makes inference to the parameter using its posterior distribution given the sample observations. It is not difficult to obtain the pos-terior distribution when a prior distribution is given, even in the case where the form of the posterior distribution is complicated, as one could always use numerical methods or Monte Carlo methods [7] to obtain an approximate point estimate or interval estimate. This is the advantage of the Bayesian approach over the traditional distribution frequen-cy approach. In this paper, we propose a Bayesian approach using the capability indices CPU and CPL, for measuring EEPROM manufacturing quality where the specifications are one-sided rather than two-sided. We obtain the credible interval of CPUand CPL, and propose, accordingly, a Bayesian procedure for capability testing. The posterior probability p, for which the process under investigation is capable, is derived in Sect.4. In Sect. 5, to make this Bayesian pro-cedure practical for in-plant applications, we tabulate the minimum values of C*(p), for which the posterior proba-bility p reaches various desirable confidence levels. Based on the test, we also develop a simple but practical step-by-step procedure. Practitioners can use the proposed proce-dure to determine whether their manufacturing processes are capable of reproducing product items satisfying the preset manufacturing quality.
2 EEPROM process capability requirement
An electrically erasable programmable read-only memory (EEPROM) chip is a user-modifiable read-only memory chip that can be erased and reprogrammed (written onto) repeatedly through the application of a higher electrical voltage. It is usually used in portable phones, PHS phones, compact portable terminals, consumer products (such as cordless phones and audio systems), industrial equipment, including measuring instruments and PLCs, OA products, such as printers and scanners, in-house telephone switches, and other communications equipment. The product inves-tigated here is a 128-bit EEPROM organized as a 16×8 configuration with a 2-wire serial interface, as depicted in Fig.1. The low-voltage design permits operations down to 1.8 volts, which maintains a maximum standby current of only 1μA, with a typical active current of only 500 μA. This EEPROM is available in 8-pin PDIP, 8-pin SOIC (150 mil), 8-pin TSSOP, and 5-pin SOT-23 packages. This EEPROM supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data is defined as a receiver.
2.1 Process capability requirement for OLC
The output leakage current (OLC) is an essential product quality characteristic which has a significant impact on the product quality. For the OLC of a particular model of EEPROM, the upper specification limit, USL, is set to 5 μA. For processes with one-sided specifications, some minimum capability requirements have been recommended
[11], as specific process types must run under some des-ignated quality conditions. Those recommendations are summarized in Table 1. For existing manufacturing pro-cesses, the capability must be no less than 1.25, and for new manufacturing processes, the capability must be no less than 1.45. For existing manufacturing processes, regarding safety, strength, or critical parameters, the capability must be no less than 1.45, and for new manufacturing processes, regarding safety, strength, or critical parameters, the ca-pability must be no less than 1.60.
For normally distributed processes with one-sided spec-ification limit USL, the process yield P(X< USL) is:
P X 3 < USL 3 ¼ P 1 3Z < CPU ¼ P Z < 3Cð PUÞ ¼ 3Cð PUÞ; where Z is the standard normal distribution N(0, 1). Therefore, the corresponding non-conforming units in parts per million (NCPPM) for a well-controlled normally dis-tributed process can be calculated, exactly, as NCPPM¼ 106 1 3C½ ð PUÞ: Consequently, the production yield for the usual existing processes should target no more than 88 PPM, noting that NCPPM≤200 PPM is the common standard used in most microelectronic industries for prod-ucts with two-sided specifications. The production yield for newly set up processes on safety, strength, or with critical parameters, however, should target no more than 0.8 PPM, a more stringent requirement set for possible mean shift or variation change.
3 Sample calculations of CPU and CPL
To estimate the indices CPU and CPL, we consider the natural estimators, which are defined as the following:
bCPU¼
USL x
3s ; bCPL¼ x LSL
3s ;
where x¼Pni¼1xi=n and s¼ ðn1Þ1Pni¼1ðxixÞ2
h i1 2=
are conventional estimators of μ and σ, which may be obtained from a process that is demonstrably stable (in control). Chou and Owen [5] investigated the natural estimators bCPUand bCPL; and showed that, under the
normality assumption, the estimators bCPUand bCPL are distributed as ctn−1(δ), where c ¼ 3 ffiffiffin
p
ð Þ1 and tn−1(δ) is a non-central t distribution with n−1 degrees of freedom and non-centrality parameter ¼ 3pffiffiffinCPUand ¼ 3
ffiffiffi n p
CPL; respectively. Both estimators are biased, but Pearn et al. [15] showed that, by adding the well-known bias correction factor bf¼ð2=fÞ1=2 f=2ð Þ=½ f 1Þ=2ð to bCPUand bCPL; then the unbiased estimatorsbn1bCPUandbn1bCPL can be obtained, which have been denoted as eCPUand eCPL: That is, EðeCPUÞ ¼ CPU and EðeCPLÞ ¼ CPL: Since bf<1 (n > 2), then VarðeCPUÞ < VarðeCPUÞ and VarðeCPLÞ < VarðbCPLÞ: Further, since both estimators depend only on the sufficient and complete statisticsðx; s2Þ; eCPUand eCPL are uniformly minimum variance unbiased estimators (UMVUE) of CPU and CPL, respectively.
Based on the two UMVUEs, eCPUand eCPL; Pearn and Chen [14] implemented the statistical theory of hypotheses testing, and developed a simple but practical procedure accompanied with convenient tabulated critical values for engineers/practitioners to use in decision making for their factory applications. Formulas for computing the power of the corresponding test are also obtained based on the following probability density function, putting CPU=Y and ¼ 3pffiffiffinCPU; then: f yð Þ ¼3 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi nðn 1Þ q 2n=2 bn1pffiffiffi n 1ð Þ2 Z1 0 tðn2Þ=2exp 1 2 t þ 3ypffiffiffiffiffint bn1 ffiffiffiffiffiffiffiffiffiffiffin 1 p 2 " # ( ) dt; wherebn1¼ n12 1=2 n12 n22 1:
Lin and Pearn [9] developed efficient SAS computer programs to calculate the critical values and p values needed based on the cumulative distribution function for the capability testing. An illustrative application of capability testing to the voltage level translator was also given. Pearn and Shu [16, 19] further developed an ef-ficient algorithm with the Matlab computer program to find the lower confidence bounds conveying critical informa-tion regarding the minimal true process capability. How-ever, their investigations are all based on traditional distribution frequency approaches.
4 A Bayesian approach for capability testing
Cheng and Spiring [4] proposed a Bayesian procedure for assessing process capability index Cp. Shiau et al. [20] applied a similar Bayesian approach to index Cpmand index Cpk, but under the restriction that the process meanμ equals the midpoint of the two specification limits, m (a rather impractical assumption for most factory applications, since, in this case, Cpk reduces to Cp). In the following, we
Table 1 Some minimum capability requirements based on CPUfor new and special processes
CPU value
Production process types
1.25 Existing processes
1.45 New processes or existing processes regarding safety, strength, or critical parameters
consider a Bayesian procedure for the one-sided capability indices CPUand CPL, derive a Bayesian interval estimate for CPU and CPL, and propose, accordingly, a Bayesian pro-cedure for testing process capability. A 100p% credible interval is the Bayesian analog of the classical 100p% confidence interval, where p is the confidence level for the interval. The credible interval covers 100p% of the pos-terior distribution of the parameter [1]. Assuming that the measures x={x1, x2,..., xn} are a random sample taken from independent and identically distributed (i.i.d.) N(μ, σ2), a normal distribution with meanμ and variance σ2. Then, the likelihood function forμ and σ is:
L ; jxð Þ ¼ 2π 2n=2 exp Pn i¼1ðxi Þ2 22 ( ) : The first step for the Bayesian approach is to find an appropriate prior. If prior information about the parameters
is available, it should be incorporated in the prior density. When there is little or no prior information, we want a prior with minimal influence on the inference. One of the most widely used non-informative priors is the so-called ref-erence prior, which is a non-informative prior that max-imizes the difference between the information (entropy) on the parameter provided by the prior and by the posterior. In other words, the reference prior allows the prior to provide as little information as possibly about the parameter (see [2] for more details). Therefore, in this paper, we adopt the following non-informative reference prior:
π ; ð Þ ¼ 1=; 0 < < 1:
The posterior probability density function (PDF), f (μ, σ|x) of (μ, σ) may be expressed as the following:
f ; jxð Þ / L ; jxð Þ ; ð Þ / nþ1ð Þ exp Pn i¼1ðxi Þ 2 22 0 B B @ 1 C C A; Since: Z 1 0 Z 1 1 nþ1ð Þ exp Pn i¼1ðxi Þ 2 22 0 B B @ 1 C C Ad d ¼ Z 1 0 nþ1ð Þexp 1 2 Z 1 1exp n xð Þ2 22 ! d " # d ¼ ffiffiffiffiffiffi 2n r ð Þ:
And in order to satisfy the integration property, that the probability over the PDF is 1, so that:
f ; jxð Þ ¼ 2 ffiffiffi n p ffiffiffiffiffiffi 2 p ð Þ nþ1ð Þ exp Pn i¼1ðxi Þ 2 22 0 B B @ 1 C C A (1) where ¼ n 1ð Þ=2; ¼ Pni¼1ðxi xÞ2=2 h i1 ¼ n 1 ð Þs2=2 1
: As mentioned before, it is natural to consider the quantity Pr{process is capable | x} in the Bayesian approach. Since the indices CPUand CPLare our major concern in this paper, so we are interested in finding the posterior probability p = Pr{CPU>w | x} or Pr{ CPL>w | x} for some fixed positive number w. Therefore, given a
pre-specified capability level w>0, the posterior probability based on index CPUthat a process is capable is given as:
p ¼ Pr Cf PU> wjxg ¼Pr USL 3 > wjx ¼ Pr þ 3w < USLjxf g ¼ Z 1 0 Z USL3w 1 2pffiffiffin ffiffiffiffiffiffi 2 p ð Þ nþ1ð Þ exp Pn i¼1ðxi Þ 2 22 0 B B @ 1 C C Ad d ¼ Z 1 0 2pffiffiffin ffiffiffiffiffiffi 2 p ð Þ nþ1 ð Þ exp 1 2 Z USL3w 1 exp n xð Þ2 22 ! d d ¼ Z 1 0 2n ð Þ exp 1 2 USL 3w x ffiffiffinp ! d ¼ Z 1 0 2n ð Þexp 1 2 3pffiffiffin bCPU s w d
By changing variable, let y = βσ2. Then, dy = 2βσdσ and s ¼ ffiffiffiffiffiffiffiffiffiffiffi 2 n1 ð Þy q
. Therefore, the posterior probability p may be rewritten as: p ¼ Pr Cf PU> wjxg ¼ Z 1 0 1 ð Þyþ1 exp 1 y 3pffiffiffin eCPU bn1 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 n 1 ð Þy s w !! dy (2) where ¼ n 1ð Þ2; ¼ P n i¼1ðxi xÞ 2=2 1 ¼ n 1 ð Þs2=2 ½ 1; 1 < < 1; 0 < < 1; bn1¼ 2= n 1ð Þ
½ 1=2 n 1½ð Þ=2= n 2½ð Þ=2 and Φ is the cu-mulative distribution function of the standard normal distribution.
On the other hand, the posterior probability based on the index CPLthat a process is capable is given as:
p ¼ Pr Cf PL> wjxg ¼Pr LSL 3 > w
j
x ¼ Pr 3w > LSLjxf g ¼ Z 1 0 Z 1 LSLþ3w 2pffiffiffin ffiffiffiffiffiffi 2 p ð Þ nþ1 ð Þ exp Pn i¼1ðxi Þ 2 22 0 B B @ 1 C C Ad d ¼ Z 1 0 2n ð Þexp 1 2 1 LSLþ 3w x ffiffiffinp ! " # d ¼ Z 1 0 2n ð Þexp 1 2 3pffiffiffin bCPL s w d ¼ Z 1 0 1 ð Þyþ1exp 1 y 3pffiffiffin eCPL bn1 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 n 1 ð Þy s w !! dy (3)(3)
5 Procedure for testing process capability
For the convenience of presentation, we let CIbe either CPU or CPL, bCI denote either bCPUor bCPL; and eCI denote either eCPUor eCPL; then, from Eqs.2 and3, the posterior prob-ability based on the one-sided indices CPUand CPLcan be rewritten as:
p ¼ Pr the process is capablejxf g ¼Pr Cf I> wjxg ¼ Z 1 0 1 ð Þyþ1 exp 1 y 3pffiffiffin eCI bn1 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 n 1 ð Þy s w !! dy where ¼ n 1ð Þ=2; bn1¼ 2 n 1½ ð Þ1=2 n 1½ð Þ=2= n 2½ð Þ=2; and Φ is the cumulative distribution function of the standard normal distribution. Note that the posterior probability p depends on n, w, and eCI: From Eq. 4, by noticing that there is a one-to-one correspondence between p and C* when n and w are given, and by the fact that eCI can be calculated from the process data, we find that the minimum value of C*(p) required to ensure that the posterior
probability p reaches a certain desirable level can be useful in assessing process capability. Thus, the value w, denoted by LCIð Þ, satisfies:p
p ¼ Pr Cf I> wjxg ¼Pr Cf I> LCIð Þjxp g (5) Fig. 2 Probabilityp versus C*(p) for n=10(30)100, w=1.25
Fig. 3 Probabilityp versus C*(p) for n=10(30)100, w=1.45
Fig. 4 Probabilityp versus C*(p) for n=10(30)100, w=1.60
Table 2a Critical values C*(p) for w=1.25, n=10(10)300, and p=0.99, 0.975, and 0.95 n p=0.99 p=0.975 p=0.95 10 2.420 2.124 1.910 20 1.927 1.780 1.667 30 1.763 1.659 1.576 40 1.677 1.593 1.526 50 1.622 1.551 1.493 60 1.584 1.521 1.470 70 1.555 1.498 1.452 80 1.532 1.480 1.438 90 1.513 1.465 1.426 100 1.498 1.453 1.416 110 1.485 1.443 1.408 120 1.474 1.434 1.401 130 1.464 1.426 1.394 140 1.455 1.419 1.389 150 1.448 1.413 1.384 160 1.441 1.407 1.379 170 1.434 1.402 1.375 180 1.429 1.398 1.372 190 1.424 1.393 1.368 200 1.419 1.389 1.365 210 1.414 1.386 1.362 220 1.410 1.383 1.359 230 1.406 1.379 1.357 240 1.403 1.377 1.355 250 1.400 1.374 1.352 260 1.396 1.371 1.350 270 1.393 1.369 1.348 280 1.391 1.367 1.346 290 1.388 1.365 1.345 300 1.386 1.362 1.343
(4)
A 100p% credible interval for CIis L½ CIð Þ; 1p ; where p
is a number between 0 and 1, say, 0.95 for a 95% confidence interval, which means that the posterior probability that the credible interval contains CIis p. Figures2,3, and4plot the probability p versus C*(p) from Eq.5for n=10(30)100 with w=1.25, 1.45, 1.60, respectively. From these figures, we can see that the larger the sample size, the steeper the curve. That is, the larger is the sample size, the smaller the critical value C*(p).
In our Bayesian approach, we say that the process is capable in a Bayesian sense if all the points in this credible interval are greater than a pre-specified value of w, say 1.00 or 1.25. When this happens, we have p=Pr{CI>w | x}. In other words, to see if a process is capable (with capability level w and confidence level p), we only need to check if eCI> Cð Þ: Throughout this paper, it is assumed that thep process measurements are independent and identically dis-tributed (i.i.d.) from a normal distribution, and the process is under statistical control. We remark that the estimation of these capability indices is meaningful only when the pro-cess is under statistical control. Table 2a,b,c tabulates the
values of C*(p) for w=1.25, 1.45, and 1.60, n=10(10)300, for p=0.95, 0.975, and 0.99, respectively. For example, if w=1.25 is the minimum capability requirement, then for p=0.95, n=50, C*(p)=1.493. Thus, the value of eCI calcu-lated from sample data must satisfy eCI 1:493 to con-clude that CPU(or CPL)≥1.25 (process is capable).
As a result, to judge if a given process meets the ca-pability requirements, we first determine the pre-specified value w, the capability requirement, and the α-risk or the confidence level p for the interval. Checking the appro-priate table or solving Eq.4(the program is available from the authors), we may obtain the critical value C*(p) based on given values of p, sample size n, and, next, to calculate eCI from samples. If the estimated value eCI is greater than the critical value C*(p), then we may conclude that the process meets the capability requirements (CI> w). Other-wise, we do not have sufficient information to conclude that the process meets the present capability requirements. In this case, we would believe that CI≤ w. In the following section, we present a simple step-by-step procedure for
Table 2c Critical values C*(p) for w=1.60, n=10(10)300, and p=0.99, 0.975, and 0.95 n p=0.99 p=0.975 p=0.95 10 3.074 2.700 2.430 20 2.450 2.265 1.122 30 2.244 2.112 2.009 40 2.135 2.030 1.946 50 2.066 1.977 1.904 60 2.018 1.939 1.875 70 1.981 1.910 1.852 80 1.953 1.888 1.835 90 1.930 1.870 1.820 100 1.910 1.854 1.808 110 1.894 1.841 1.798 120 1.880 1.830 1.789 130 1.868 1.820 1.781 140 1.857 1.811 1.774 150 1.847 1.804 1.767 160 1.839 1.797 1.762 170 1.831 1.790 1.757 180 1.824 1.785 1.752 190 1.817 1.779 1.748 200 1.811 1.774 1.744 210 1.805 1.770 1.740 220 1.800 1.766 1.737 230 1.796 1.762 1.734 240 1.791 1.758 1.731 250 1.787 1.755 1.728 260 1.783 1.752 1.725 270 1.779 1.749 1.723 280 1.776 1.746 1.721 290 1.773 1.743 1.718 300 1.769 1.741 1.716
Table 2b Critical values C*(p) for w=1.45, n=10(10)300, and p=0.99, 0.975, and 0.95 n p=0.99 p=0.975 p=0.95 10 2.793 2.452 2.206 20 2.225 2.057 1.927 30 2.038 1.918 1.823 40 1.939 1.843 1.766 50 1.876 1.794 1.728 60 1.832 1.760 1.701 70 1.798 1.734 1.681 80 1.772 1.713 1.664 90 1.751 1.696 1.651 100 1.734 1.682 1.640 110 1.719 1.670 1.630 120 1.706 1.660 1.622 130 1.695 1.651 1.615 140 1.685 1.634 1.609 150 1.676 1.636 1.603 160 1.668 1.630 1.598 170 1.661 1.624 1.593 180 1.654 1.619 1.589 190 1.648 1.614 1.585 200 1.643 1.609 1.581 210 1.638 1.605 1.578 220 1.633 1.601 1.575 230 1.629 1.598 1.572 240 1.625 1.595 1.569 250 1.621 1.591 1.567 260 1.617 1.589 1.565 270 1.614 1.586 1.562 280 1.611 1.583 1.560 290 1.608 1.581 1.558 300 1.605 1.578 1.556
testing the process capability. The practitioners can apply the procedure to their in-plant applications to obtain reliable decisions.
5.1 Test procedure
Step 1
Decide the definition of“capable” (w, normally set to 1.00, 1.25, 1.45, or 1.60), and the confidence level p for
the interval (normally set to 0.99, 0.975, or 0.95). The chance of the true CPUor CPLlying in this interval is p. Step 2
Calculate the value of bn−1and the estimator bCI from the collected sample, then eCI¼ bn1 eCI can be obtained. Step 3
Check the appropriate table to find the critical value C* (p) based on given values of p, sample size n, and w. Step 4
Conclude that the process is capable (CI > w) if eCI value is greater than the critical value C*(p). Other-wise, we do not have enough information to conclude that the process is capable.
6 Measuring EEPROM process capability
We consider the following example taken from a company located on the Hsinchu Science-Based Industrial Park (HSIP) in Taiwan, which designs and manufactures stan-dard flash memory EEPROM and mixed-signal products, such as PLL, ADC DAC, and many others. The man-ufacturing specifications for a 128-bit EEPROM chip has an upper specification limit USL=5μA for the output leakage current (OLC), as mentioned before. If the OLC is
Table 3 A total of 100 observations
2.74 2.25 2.98 3.14 3.08 2.85 3.21 2.51 3.19 2.75 3.68 3.23 2.90 3.05 2.58 3.31 2.52 3.16 2.62 2.95 2.85 2.80 3.03 3.05 2.54 2.44 2.82 3.01 2.93 3.39 2.47 3.08 2.40 3.22 2.77 3.05 4.15 2.59 3.28 3.56 2.75 3.38 3.49 2.54 2.28 2.93 3.54 3.49 3.09 3.17 3.17 2.66 3.35 2.77 2.68 3.15 3.23 2.77 2.30 2.17 3.35 2.76 2.20 2.75 3.58 2.70 2.78 2.99 3.63 3.44 2.91 2.67 3.56 2.73 2.90 2.41 3.20 3.86 3.02 3.39 3.26 3.60 2.89 3.18 3.03 2.60 2.70 3.25 3.32 2.67 2.61 3.09 3.07 2.89 3.49 3.14 2.96 2.87 2.97 3.26
Fig. 5 a X control chart of the process. b S control chart of the process
greater than 5μA, then the EEPROM chip is considered to be a nonconforming product, and will not be used to make the EEPROM chip of that particular model. The capability requirement for this particular model of EEPROM chip was defined as“capable” if CPU>1.45.
And, as mentioned before, in order to make the esti-mation of these capability indices meaningful, it is neces-sary to check whether the manufacturing process is under statistical control. We use the X and S charts for retro-spectively testing whether the process is in control. A partial historical data, including a group of 30 samples of size 10, and the correspondingX S charts are displayed in Fig.5a,b. The X S control charts show that all the sample points are within the control limits without any special pattern, and the process is justified to be in well control. Therefore, we could consider the process to be stable, so we could proceed with the capability measure.
A total of 100 observations collected from a stable process in the factory are displayed in Table 3. Figure 6 displays the histogram of the sample data. Figure7displays the stem-and-leaf plot of the sample data. Figure8displays the box-whisker plot of these data, and the normal prob-ability plot of the 100 sample data is plotted in Fig.9. The data analysis results justify that the process is fairly close to the normal distribution.
From Figs.6,7,8, and9, and the Shapiro-Wilk test for normality confirming this with p-value>0.1, it is evident to
take into consideration that the data collected from the fac-tory are normal distributed. The sample mean X¼ 2:987 and the sample standard deviation s=0.382 are first cal-culated. For n=100, we calculate the value of the estimator bCPU¼ USL X
3s ¼ 1:757 and bn−1=0.992 based on the sample size of n. We assume that the α-risk is 0.05, the critical value is found to be C*(p)=1.640 from Table 3, based on w=1.45, p=0.95, and n=100. Since eCPU¼ bn1 bCPU¼ 1:743 is larger than the critical value C*(p)=1.640 in this case, we, therefore, conclude that, with a 95% level of confidence, the 128-bit EEPROM chip manufacturing process satisfies the requirement “CPU>1.45.” Thus, at least 99.99863% of the produced EEPROM chips conformed to the manufacturing speci-fications, with a fraction of nonconformities at 13.614 PPM, which is considered a satisfactory figure and reliable in terms of product quality (originally set by the product designers or the manufacturing engineers).
7 Conclusion
Process capability indices have been proposed in the man-ufacturing industry to provide numerical measures on process capability, which are effective tools for quality as-surance. Usual practices in measuring production quality have focused on the traditional distribution frequency ap-proach. In this paper, we considered estimating and testing the one-sided capability indices CPU and CPL using a Bayesian approach. We obtained the credible intervals of CPUand CPL, and proposed, accordingly, a Bayesian pro-cedure for capability testing. The posterior probability p for which the process under investigation is capable is derived. The credible interval, a Bayesian analog of the classical lower confidence interval, is obtained. To make this Bayesian procedure practical for in-plant applications, we tabulate the minimum values of C*(p) for which the posterior probability p reaches various desirable confidence levels. A factory example of the manufacture of EEPROM chips was investigated, showing how the Bayesian procedure can be applied to in-plant applications.
Fig. 8 Box-whisker plot
Fig. 9 Normal probability plot Fig. 7 Stem-and-leaf plot
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