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Low Frequency Noise in Nanoscale pMOSFETs with Strain Induced Mobility Enhancement and Dynamic Body Biases

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Low Frequency Noise in Nanoscale pMOSFETs with Strain Induced

Mobility Enhancement and Dynamic Body Biases

Kuo-Liang Yeh, Chih-You Ku, Wei-Lun Hong, and Jyh-Chyurn Guo

Institute of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan

Tel: +886-3-5131368, Fax: +886-3-5724361, E-mail: jcguo@mail.nctu.edu.tw

Abstract —Local strain effect on low frequency noise (LFN) of

pMOSFETs with gate length down to 60 nm was investigated in this paper. Novel and interesting results were identified from the pMOSFETs adopting embedded SiGe (e-SiGe) in source/drain for uni-axial compressive stress. This local compressive strain can realize significant mobility enhancement and desired current boost in nanoscale pMOSFETs. However, the dramatic increase of LFN emerges as a penalty traded off with mobility enhancement. The escalated LFN may become a critical killer to analog and RF circuits. Forward body biases (FBB) can improve the effective mobility (Peff) and reduce LFN attributed to reduced normal field (Eeff). However, the benefit from FBB becomes insignificant in strained pMOSFETs with sub-100 nm gate length.

Index Terms–Low frequency noise, strain, mobility, pMOSFET

I. INTRODUCTION

Strain engineering has evolved as an indispensable technology in high speed CMOS platform at 65 nm node and beyond [1]. Both local and global strain engineering can realize an effective mobility enhancement and current boost. The gate speed improvement driven by the mobility and current indeed makes a contribution to fT and fmax, the key

parameters determining RF and analog circuits performance [2-3]. However, the potential impact from the strain on noise, particularly the low frequency noise (LFN) or namely flicker noise brings a critical challenge to both RF and analog circuits/systems design. Consequently, the strain engineering effect on noise becomes an important subject and attracts increasing research effort in recent years. Many literatures were published with a discussion on strain effect on LFN [4-6]. Unfortunately, there exist lot of debates in the experimental results and proposed mechanisms. Maeda et al. reported flicker noise increase in pMOSFETs under both compressive and tensile stress, namely bi-directional noise degradation [5]. Stress induced excess traps and dipoles were proposed as the possible cause responsible for flicker noise degradation. Ueno

et al. published results just in contradiction to the previous one

[6]. They claimed improved 1/f noise in pMOSFEs with e-SiGe for local compressive stress, and controverted Maeda’s results as inclusive owing to side effects other than stress. Unfortunately, there remain couple of open questions deserving an extensive investigation, such as the excess noise introduced by Ge-implant for stress relaxation, the abnormally

large LFN revealed in pMOS compared to nMOS with stress free liner, and number fluctuation model assumed for pMOSFETs.

Meanwhile, the lower supply voltage for matching device scaling and lower active power generally degrades the headroom for signal to noise margin (SNM) and raises more crucial demand on low noise design. Dynamic threshold voltage CMOS (DTMOS) technique is considered the most promising method to facilitate low power design in nanoscale CMOS platform, and dynamic body biases scheme is an effective way to realize DTMOS [7-8]. As a result, strain engineering cooperating with dynamic body biases is proposed as a viable approach in nanoscale CMOS for high speed, low power, and low noise design.

In this paper, pMOSFETs adopting e-SiGe S/D for uni-axial compressive strain were fabricated for mobility enhancement. A comprehensive characterization was carried out to investigate the local strain effect on mobility, current, short channel integrity, and most importantly LFN. Dynamic body biases scheme consisting of forward body bias (FBB), zero body bias (ZBB), and reverse body bias (RBB) was employed to explore the influence on LFN. Through the extensive characterization and theoretical analysis, the mechanism responsible for LFN in pMOSFETs can be extracted, and the results suggest that mobility fluctuation model plays a dominant role.

II. DEVICE FABRICATION AND CHARACTERIZATION

Strained pMOSFETs adopting e-SiGe in S/D for local compressive strain were fabricated in 65 nm process. The standard devices free from strain engineering, namely control pMOSFETs were fabricated simultaneously as the reference. Four-terminal device layout was implemented with 4 individual pads for 4 electrodes (G/D/S/B) to enable a freedom of body biases. The gate width (W) was fixed at 10Pm while the gate lengths drawn on layout (Ldrawn) varied in a wide range

from 10 Pm to 0.08Pm. An etching bias of 0.02Pm leads to physical gate length Lg=Ldrawn-0.02Pm, i.e. the minimal Lg

down to 0.06Pm (60 nm).

The drain current noise was measured by LFN system consisting of Agilent dynamic signal analyzer (DSA 35670) and low noise amplifier (LNA SR570). The measured noise

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was represented as power spectral density (PSD) in frequency

domain, denoted as SId. The LFN measurement generally

covers a wide frequency range from 10 to 100 KHz. III. RESULTS AND DISCUSSION

A. Local Strain Effect on Current and Mobility

Firstly, local strain effect on current drivability was investigated on 60 nm pMOSFETs. Fig. 1(a) and (b) present the measured drain current IDS and transconductance Gm under

varying VGS. Note that gate overdrive VGT= VGS–VT was

specified to replace VGS for eliminating VT offset due to strain

engineering. The comparison between strained and control devices reveals a remarkable increase of both IDS and Gm in the

60 nm devices, due to the uni-axial compressive strain. The

improvement can reach around 80% increase in IDS and

maximum Gm. The experimental proves the local strain an

effective technique for performance boost in nanoscale devices. 0.2 0.0 -0.2 -0.4 -0.6 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 Control Strained (a) PMOS W10L006 VDS= -50mV IDS (mA) VGT (V) 0.2 0.0 -0.2 -0.4 -0.6 0.0 0.2 0.4 0.6 0.8 1.0 Control Strained (b) Gm (m A/V) PMOS W10L006 VDS= -50mV VGT (V)

Fig. 1 (a) Drain current IDS vs. VGT (b) transconductance Gm vs. VGT

measured in linear region at VDS=-50mV and varying VGS

(VGT=VGS-VT) for control and strained pMOSFETs with Lg=60 nm.

0.1 1 10 35 40 45 50 55 60 65 70 75 80 Control Strained W=10 Pm, VBS=0 VGT= -0.4V, VDS= -50mV Gate length, L ʻPmʼ Peff ʻ cm 2 /V -s ʼ

Fig. 2 The effective mobility Peff extracted from linear I-V

characteristics for strained and control pMOSFETs over various gate lengths, Lg=10~0.06Pm.

Fig. 2 exhibits the effective mobility Peff extracted from

linear I-V characteristics. Interestingly, the extracted Peff

indicates a significant dependence on Lg for both strained and

control pMOSFETs but going the opposite directions. For strained pMOS, the shorter Lg gains higher Peff whereas for

control pMOS, the shorter Lg suffers degradation in Peff. As a

result, the Peff enhancement realized by strained over control

pMOSFETs can attain around 74%, which exactly contributes the improvement of IDS and Gm. The Peff enhancement realized

in strained pMOS with sufficiently short Lg manifests the local

compressive strain effect from e-SiGe S/D. On the other hand,

the dramatic Peff degradation with Lg reduction revealed in

control pMOS suggests an aggravated impurity scattering due to halo implantation located near channel region in sufficiently short devices.

B. Local Strain Effect on VT and Body Bias Sensitivity

Local strain effect on VT and its sensitivity to body biases

emerges as one major concern for the deployment of dynamic body biases. Fig. 3(a) shows the linear VT measured over

various Lg (10~0.06 Pm). The control pMOS indicates a

significant |VT| increase with Lg scaling, namely reverse short

channel effect (RSCE) over the full range of Lg. Halo

implantation introduced lateral non-uniform profile is the major cause responsible for RSCE. As for strained pMOS, RSCE is demonstrated in Lg scaling to 0.13 Pm but followed

with a VT roll-off for Lg reduction to 60 nm. The occurrence of

VT roll-off in 60 nm device suggests that short channel effect

(SCE) becomes strong and dominates RSCE. Strain induced bandgap narrowing (or valence band offset for holes) and S/D recess for e-SiGe are two potential factors for the worse SCE and VT roll-off. Note that the VT lowering in this uni-axially

strained pMOS is relatively much smaller than those with bi-axial strain [9]. Fig. 3(b) presents VT shift ('VT) under FBB

(VBS=-0.6V) and RBB (VBS=0.6V) over various Lg. The FBB

enables a positive VT shift toward lower |VT| whereas RBB

leads to a negative VT shift toward higher |VT|. The comparison

indicates that strained pMOSFETs have a smaller VT shift

under both FBB and RBB, particularly for Lg scaling to 60 nm.

The results can be self-consistently explained with the causes proposed for VT lowering identified from strained devices. The

potential impact is the degraded sensitivity and VT tunability

under dynamic body biases.

0.1 1 10 -0.28 -0.30 -0.32 -0.34 -0.36 -0.38 -0.40 Control Strained (a) W=10 Pm VDS=- 50mV, VBS=0 Gate Length, L ʻPmʼ VT (V) 0.1 1 -25 0 25 50 (b) 'V T ʻ VBS ʼ /|V T ʻ VBS =0 ʼ | (%) RBB FBB W=10 Pm, VDS= -50mV 'VTʻVBSʼ=VTʻVBSʼ-VTʻVBS=0ʼ Control VBS=0.6V Strain VBS=0.6V Control VBS= -0.6V Strain VBS= -0.6V Gate Length, L ʻPmʼ

Fig. 3 (a) Linear VT measured at VDS=-50mV, VBS=0 for strained and

control pMOS (b) VT shift due to VBS, normalized to VT(VBS=0) :

'VT(VBS)/VT(VBS=0),'VT(VBS)=VT(VBS)-VT(VBS=0) measured under

FBB (VBS=-0.6V) and RBB (VBS=0.6V) for strained and control

pMOS with Lg =1 ~0.06 Pm.

C. Low Frequency Noise –Local Strain and Dynamic Body Biases Effect

Local compressive strain has been proven as an effective performance booster in nanoscale pMOS but its impact on LFN becomes a critical concern for analog and RF circuit design. To explore local strain and gate length scaling effect on LFN, SId

in the strained devices with the shortest Lg and largest Peff

enhancement was investigated. Fig.4 shows the LFN measured

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from 60 nm pMOS and represented as SId/IDS2 in the frequency

domain. Unfortunately, the strained pMOS reveal significantly higher SId/IDS2 than control pMOS over the full range of

frequencies in 10 ~ 100 kHz. 101 102 103 104 105 10-14 10-13 10-12 10-11 10-10 10-9 Control Strained pMOS W10L006 V DS=-50 mV VGT=-0.4V, VBS=0 SId /IDS 2 (1 /H z ) Freq. (Hz)

Fig. 4 The SId measured for 60 nm pMOS under VGT =-0.4V and

VBS=0. The LFN is represented as SId/IDS 2

for a fair comparison between strained and control devices with different IDS.

0.1 1 0.5 1.0 1.5 Control Strained VDS=-50mV, VBS=0 Eeff = 0.65MV/cm WL*S Id /IDS 2 ʻ 1o -1 0/Hz* P m 2ʼ (b) W=10 Pm Gate length, L ʻPmʼ 0.1 1 5 10 15 20 25 Control Strained (a) W=10 Pm VDS=-50mV, VBS=0 Eeff = 0.65MV/cm SId /IDS 2 ʻ 1/ H Z * 1 0 -10 ʼ Gate length, L ʻPmʼ

Fig. 5 The SId measured under a specified Eeff of 0.65MV/cm and

normalized to IDS2for strained and control pMOSFETs with various Lg

(0.98 ~0.06Pm) (a) SId/IDS 2

(b) SId/IDS 2

xWLg

Fig. 5(a) shows SId normalized to IDS2 under a specified Eeff

(0.65MV/cm) for strained and control pMOS with various Lg

(0.98~0.06 Pm). For long devices with Lg=0.98Pm, LFN in

terms of SId/IDS2 keeps nearly the same for strained and control

pMOS. Unfortunately, the strained pMOS suffer obviously higher SId/IDS2 for shorter Lg. Fig. 5(b) presents SId/IDS2

multiplied with device gate dimensions WxLg. Interestingly,

opposite trends are demonstrated for strained and control devices in SId/IDS2xWLg against Lg scaling. Strained pMOS

indicate an increasing trend versus Lg scaling whereas control

pMOS reveal a decreasing function. This result cannot be explained by number fluctuation model and actually is in contradiction to what was published for nMOS [10]. Referring to Fig. 3(a), the dramatic RSCE revealed in control pMOS indicates a highly non-uniform channel doping profile due to halo implantation and suggests an aggravated impact on LFN based on the number fluctuation model [10]. However, the experimental for pMOS exhibits an opposite trend that is the control pMOS with apparently worse RSCE than strained pMOS have much lower LFN. Regarding other potential reasons responsible for the worse LFN in strained devices, like stress induced excess traps or dipoles [5], they cannot be justified due to a contraction with the measured gate leakage currents Jg in which the strain pMOS presents a lower Jg than

control pMOS (not shown). The mentioned argument

motivates our interest in exploring an appropriate model for an accurate prediction of LFN in pMOS. Fig. 6 presents an analysis of LFN in terms of SId/IDS2under varying IDS(VGT,VBS)

for strained and control pMOS with Lg in 0.98 ~ 0.06 Pm. The

SId/IDS2 follows a function proportional to 1/IDS over the whole

range of bias conditions from low VGT to high VGT. The result

indicates that mobility fluctuation model derived according to Hooge empirical formula and given by (1) or (2) is the dominant mechanism governing pMOS’s LFN [11].

2 2 2 1 (1) 1 , ( ) (2) : d d I DS H eff DS DS I H GT GS T DS ox GT H S qV I f I L S q V V V I f WLC V where

the Hooge parameter

D P D D u  10-6 10-5 10-4 10-3 10-12 10-11 10-10 10-9 L=0.06,0.13Pm L=0.98Pm VDS= -50mV, VGT= -0.2~-0.6V VBS= -0.6 ~0.6V Strain pMOS L098 L013 L006 Control pMOS L098 L013 L006 Sid /IDS 2 (1 /Hz)

Drain Current IDS (A)

1/I

DS

Fig. 6 The SId/IDS2 versus IDS, measured under varying VGT(VGT=

-0.2~ -0.6V) and body biases (VBS=-0.6, 0, 0.6V) for strained and

control PMOS with various Lg (0.98 ~0.06 Pm).

Note that SId/IDS2 exhibits a dramatic increase with Lg

scaling in both strained and control devices, and strained

pMOS suffer much higher LFN in terms of SId/IDS2 for

aggressively scaled dimensions at 0.13 Pm and 0.06 Pm. The mobility fluctuation model with an expression of (1) for varying IDS or (2) for varying VGT can predict the dramatic

increase of SId/IDS2 with L scaling and more importantly help

explore the origins responsible for the worse LFN in strained

pMOS. The increase of effective mobility Peff or Hooge

parameter DH will lead to higher LFN in terms of SId/IDS2 under

a specified IDS. It explains why the strained pMOS with short

Lg (0.13, 0.06 Pm) indeed gain the benefit of higher Peff but

pay the penalty of increased LFN, as shown in Fig. 5 and 6. According to (2), the effective ways to suppressing LFN can be classified as the increase of device dimensions (W, L), the increase of VGT, and the reduction of DH. The local strain

cooperating with body biases effect on the Hooge parameter DH emerges as an interesting topic. Fig. 7 makes a comparison

in DH between strained and control pMOSFETs over various Lg,

and exhibits a remarkable increase of DH with Lg in strained

devices but a decrease in control devices. It suggests the local strain will increase DH and makes LFN worse. Note that the

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larger DH in strained pMOS may be due to accelerated phonon

scattering in the strained lattice [12]. The enlarged difference in DH with Lg scaling is the major factor responsible for the

dramatic difference in LFN, i.e. SId/IDS2 between strained and

control pMOS with Lg scaled to 60 nm (Figs.5 and 6).

0.1 1 2.0x10-4 4.0x10-4 6.0x10-4 8.0x10-4 1.0x10-3 Strained Control W=10 Pm VDS=-50mV, VBS=0 VGT= -0.4V H o o g e Parameter, DH Gate length, L ʻP

Fig. 7 The Hooge parameter DH extracted from SId/IDS2 measured

under VGT=-0.4V and VBS=0 for strained and control pMOS with

various Lg (0.98 ~0.06 Pm)

Dynamic body biases method proven in DTMOS platform for low power design is considered a potential solution for low noise. Fig. 8 displays dynamic body biases effect on LFN in terms of Sid variation under FBB (VBS=-0.6V) as well as RBB

(VBS=0.6V) and normalized to the reference Sid at ZBB

(VBS=0), denoted as 'Sid(VBS)/Sid(VBS=0). For both strained

and control pMOS, FBB can suppress Sid given with

'Sid(VBS)< 0, attributed to reduced normal effective field Eeff.

On the other hand, RBB makes Sid worse with 'Sid(VBS)> 0.

However, the dynamic body bias effect on LFN is degraded in strained pMOS with a smaller amount in 'Sid(VBS)/Sid(VBS=0),

particularly worse for the shortest devices with Lg=60 nm. The

significant VT lowering and degraded body bias effect shown

in Fig. 3 for strained devices explains the diminishing benefit from FBB on LFN. 0.1 1 -50 -25 0 25 50 75 FBB RBB W=10 Pm,V GT= -0.4~-0.6V 'SIdʻVBSʼ=SIdʻVBSʼ-SIdʻVBS=0ʼ ' SId ʻ VBS ʼ /S Id ʻ VBS =0 ʼ (%) Strained VBS=0.6V V BS=-0.6V Control V BS=0.6V VBS=-0.6V Gate length, L ʻPmʼ

Fig. 8 The change of Sid under FBB (VBS=-0.6V) as well as RBB (VBS=0.6V)

and normalized to the reference Sid at ZBB (VBS=0), denoted as

'Sid(VBS)/Sid(VBS=0) measured for strained and control pMOS with various Lg

(0.98 ~0.06 Pm).

IV. CONCLUSION

Local compressive strain can realize hole mobility enhancement above 70% in 60 nm pMOSFETs. The

remarkable increase in Gm and IDS can boost gate speed and

RF/analog circuit performance in terms of fT and fmax. However,

the local strain leads to worse LFN with much higher SId/IDS2

in nanoscale devices. The number fluctuation model widely used for nMOSFETs is no longer valid and cannot explain the local strain as well as scaling effects on LFN measured from pMOSFETs. Mobility fluctuation model can predict the novel LFN characteristics in the dependence on local strain, geometry scaling, and bias conditions. The increase of Hooge parameter DH due to local strain is identified as the major

factor responsible for worse LFN in strained pMOSFETs. FBB can help suppress LFN but the advantage provided by FBB is degraded in strained pMOSFETs with nanoscale gate lengths.

ACKNOWLEDGEMENT

This work is supported in part by NSC 97-2221-E009-175. Besides, the authors acknowledge the support from NDL for noise measurement and UMC R&D for device fabrication.

REFERENCES

[1] P. Bai, et al., “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57Pm2 SRAM Cells,” in IEDM Tech. Digest, Dec. 2004, pp. 657-660

[2] S. Decoutere, et. al., “Technologies for sub-45nm Analog/RF CMOS – Circuit Design Opportunities and Challenges,” in IEEE CiCC Proc., 2006, pp. 679-686

[3] H. Li, et al., “Technology Scaling and Device Design for 350GHz RF Performance in 45nm Bulk CMOS Process,” in VLSI Tech. Symp. Proc., June 2007, pp. 56-57

[4] T. Ohguro, et al.,“The Impact of Oxynitride Process, Deuterium Annealing and STI Stress to 1/f Noise of 0.11mm CMOS,” in VLSI Tech. Symp. Proc., June 2003, pp.37-38

[5] S. Maeda, et al. “ Impact of Mechanical Stress Engineering on Flicker Noise Characteristics,” in VLSI Tech. Symp. Proc., June 2004, pp.102-103

[6] T. Ueno, et al., “ Improved 1/f Noise Characteristics in Locally Strained Si CMOS using Hydrogen-Controlled Stress Liners and Embedded SiGe,” in VLSI Tech. Symp. Proc., June 2006, pp.104-105

[7] F. Assaderaghi, et al.,”A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation,” in IEDM Tech. Digest, Dec. 1994, pp. 809-812

[8] T. Sakurai, “Reducing power consumption of CMOS VLSI's through VDD and VTH control,” in ISQED Proc., Mar. 2000, pp.

417-423

[9] W. Zhang, et al., “ On the Threshold Voltage of Strained-Si-Si1-xGex MOSFETs,” IEEE TED-52, no.2,

pp.263-268, Feb. 2005

[10] Jun-Wei Wu, et al., “Pocket Implant Effect on Drain Current Flicker Noise in Analog n-MOSFET Devices,” IEEE TED-51 , no.8, pp.1262 – 1266, Aug. 2004

[11] F. N. Hooge, et. al. “Lattice scattering causes 1/f noise,” Phys.

Lett. A, vol. 66, pp. 315-316, 1978.

[12] R. P. Jindal, et al. “ Phonon fluctuation model for flicker noise in elemental semiconductors,” J. Appl. Phys. vol.52, no. 4, pp. 2884-2888, Apr. 1981.

數據

Fig. 1 (a) Drain current I DS  vs. V GT  (b) transconductance G m  vs. V GT
Fig. 5 The S Id  measured under a specified E eff  of 0.65MV/cm and
Fig. 7 The Hooge parameter  D H  extracted from  S Id /I DS 2  measured

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