filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.
Index Terms—Gate-tunneling leakage, loop filter, MOS capaci-tor, phase-locked loop (PLL).
I. INTRODUCTION
T
HE REDUCTION of power consumption is very impor-tant to the portable microelectronic products. In general, the most common and efficient way to reduce the power con-sumption in CMOS very large scale integrated circuits is to reduce the power-supply voltage. The standard supply voltage has been scaled down from 2.5 V to 1 V or even lower. The gate-oxide thickness of the MOS transistor becomes thinner to reduce its normal operation voltage (power-supply voltage). The thinner gate-oxide thickness causes large gate-tunneling leakage (gate leakage current) in the nanoscale CMOS tech-nology. In digital circuits, the gate-tunneling leakage results in the high standby power consumption [1]. Therefore, to suppress the impact of gate-tunneling leakage is a very important circuit-design issue in the nanoscale CMOS processes [2], [3].Recently, clock synthesizers have been widely used in the high-speed data-processing devices such as microprocessors, DSPs, and communication systems. A clock synthesizer gen-erates several sets of clock signals with different frequencies or phases from a reference clock signal. Clock synthesizers
Manuscript received December 10, 2008; revised April 19, 2009. First published June 19, 2009; current version published July 22, 2009. This work was supported in part by the National Science Council (NSC), Taiwan, under Contract NSC 97-2221-E-009-170 and by “Aim for the Top University Plan” of the National Chiao Tung University and Ministry of Education, Hsinchu, Taiwan. The review of this brief was arranged by Editor C.-Y. Lu.
J.-S. Chen is with the Power Conversion Taiwan, Fairchild Semiconductor Corporation, Hsinchu 300, Taiwan.
M.-D. Ker is with the Institute of Electronics, National Chiao-Tung Uni-versity, Hsinchu 300, Taiwan, and also with the Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan (e-mail: mdker@ieee.org).
Digital Object Identifier 10.1109/TED.2009.2022696
improve the PLL performance, the loop filter is added into the PLL to make it stable and to filter out the noise. The loop filter was usually formed with resistor and capacitor. The capacitor of the loop filter needs a large capacitance to make the PLL stable, which is often realized with MOSFET (MOS capaci-tor) to reduce the occupied silicon area. However, the MOS capacitor with thinner gate-oxide thickness in the loop filter will also have a larger gate-tunneling leakage in the advanced CMOS technology, which will influence the PLL performance. Recently, some compensation techniques, such as the modified capacitor structure [4], [5], opamp-based compensation [6]–[8], nonopamp-based compensation [9], capacitor multiplier [10]– [12], and digital filter techniques [13], have been developed to compensate the gate-tunneling current of the MOS capacitor used in the loop filter of the PLL. However, the impact from the gate-tunneling leakage of the MOS capacitor in the loop filter on the PLL performance was not clearly investigated and reported in the literature.
In this brief, the influence of the gate-tunneling leakage on the performance of the PLL is investigated and analyzed in a 90-nm CMOS process [14]. The normal operating voltage of the MOSFET device is only 1 V in such a 90-nm CMOS process. The gate-tunneling leakage of the MOS capacitor is simulated by SPICE with BSIM4 model. The BSIM4 model was included with the gate-tunneling leakage [15]–[17]. The MOS capacitors realized with thick or thin gate oxides in the loop filter are used to investigate the impact of gate-tunneling leakage on the PLL performance.
II. PLL
A PLL is basically an oscillator whose frequency is locked onto some frequency component of an input signal. Fig. 1 shows the basic PLL with a second-order low-pass loop filter [18]. PLL is a second-order negative-feedback system similar to the RLC circuit. PLL may be stable or unstable, depending on its phase margin. Stability affects PLL performance, such as settling time, static phase error, and jitter. The capacitor of the loop filter is used to integrate the charge-pump (CP) current and to generate an averaged control voltage, which ensures the proper output frequency for the PLL. The loop filter is also used to generate the pole and zero to adjust the bandwidth and the phase margin of the PLL. In general, the bandwidth of
Fig. 1. Basic PLL with a second-order low-pass loop filter.
the PLL is usually designed about only 1/10–1/20 of the input reference frequency for system stability. A PLL consists of a phase/frequency detector (PFD), a CP, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider (divided by an integer N ). The negative feedback synchronizes the inter-nal siginter-nal (FBACK), which is from the frequency divider, to the external reference signal (FREF) by comparing their phases. The PFD develops two output signals, which are proportional to the phase errors. The CP is used to convert the logic states of PFD into analog signals for controlling the VCO, where the frequency of the output signal will be changed by charging or discharging the loop filter. In the loop filter, extra poles and zeros should be introduced to filter out high-frequency signals from the PFD and the CP. The PLL will be “locked” when the phase difference between FREF and FBACK is kept constant. Therefore, the phases of FREFand FBACKare aligned, and the frequency of the output signal (FOUT) is N -times of the input reference signal (FREF). The loop filter realized with a second-order low-pass filter has been widely used in the PLL design to improve the stability and to suppress the high-frequency noise. The on-chip capacitor in the second-order loop filter can be realized by PMOS and NMOS transistors, respectively, as shown in Fig. 2(a) and (b). In general, the filter capacitor C1has a typical range from 50 to 400 pF. The capacitor C2smoothes the large IR ripple on the signal of VCTRL. The resistor R1 provides the instantaneous phase correction without affecting the averaged frequency of the VCO.
The capacitor of the loop filter needs a large capacitance to make the PLL stable, but it also has a large gate-tunneling leakage through the MOS capacitor in the loop filter to degrade the PLL performance in the nanoscale CMOS technology. The gate-tunneling leakage of the MOSFET has been modeled as [15]–[17] Jg= A Toxref tox ntox VgVaux T2 ox e−B(α−β|Vox|)(1+γ|Vox|)tox (1) where A = q2/8πhφB, B = 8π √
2qmoxφ3/2B /3h, mox is the effective carrier mass in oxide, φB is the tunneling barrier
height, toxis the oxide thickness, Toxrefis the reference oxide thickness, and Vauxis an auxiliary function which approximates the density of the tunneling carriers. α, β, and γ are the physical
Fig. 2. Second-order loop filter realized with (a) PMOS and (b) NMOS capacitors.
parameters defined by device technology. Vgis the gate voltage
of the MOSFET device, ntox is a fitting parameter, and Voxis the voltage across the oxide of the MOSFET device.
The MOS capacitor of the loop filter is operated in the strong-inversion region in the PLL. In (1), the gate-tunneling-leakage density strongly depends on the oxide thickness, device size, and voltage across the oxide of the MOSFET. Fig. 3 shows the dependence of the gate-tunneling leakage on the NMOS and PMOS capacitors with different threshold voltages under differ-ent gate voltages in a 90-nm 1-V CMOS technology. The nor-mal operating voltage of the MOSFET device is only 1 V, and the typical oxide thickness of the MOSFET device is 2.33 nm in the given 90-nm CMOS process. The NMOS capacitor has larger gate-tunneling leakage than that of the PMOS capacitor. The electron conduction-band (ECB) tunneling is the dominant component of the gate-tunneling leakage in the NMOS device, whereas it is the hole valance-band (HVB) tunneling in the PMOS device. Because the barrier height for HVB (4.5 eV) is significantly greater than that of ECB (3.1 eV), this results in the much lower gate-tunneling leakage in the PMOS device [15]. The summary of gate-tunneling leakage per unit area of the
Fig. 3. Simulated gate-tunneling leakage on the different threshold-voltage NMOS and PMOS capacitors under the different gate voltages in a 90-nm 1-V CMOS technology.
TABLE I
GATE-TUNNELINGLEAKAGE PERUNITAREA OFNMOSAND
PMOS CAPACITORSWITHDIFFERENTTHRESHOLD
VOLTAGES IN A90-NMCMOS PROCESS
NMOS and PMOS capacitors with different threshold voltages in the given 90-nm CMOS process is shown in Table I. The gate voltage VGis set to 0.492 V in the loop filter of the PLL in
this study. The thin-oxide NMOS device with the low threshold voltage has larger gate-tunneling leakage than the other devices in the same 90-nm CMOS process.
III. EFFECT OFGATE-TUNNELINGLEAKAGE INMOS CAPACITOR ON THEPERFORMANCE OF THEPLL CIRCUIT
The static phase error, settling time, and jitter are the key factors in the PLL design and application, which will cause the time-skew problem to induce system malfunction. In this work, the PLL with a second-order low-pass loop filter is used to investigate the impact from gate-tunneling leakage of the MOS capacitor on the PLL performance. The design parameters and simulated results of the second-order PLL in a 90-nm CMOS process are shown in Table II. To compare the impact of gate-tunneling leakage in the MOS capacitor on the PLL perfor-mance, the loop filter (C1, C2, and R1) in the second-order PLL is simulated with ideal capacitor and resistor in Table II as a reference. The C1 and C2capacitors of the low-pass loop filter in the PLL, as shown in Fig. 2, are replaced by the MOS capacitors with different oxide thickness to investigate the impact of gate-tunneling leakage on the PLL performance. The capacitances of the different MOS capacitors C1 and C2 are 85.172 and 8.782 pF, respectively, under the gate voltage of
Fig. 4. Simulated transition waveforms of control voltage (VCTRL) to find
the locked time under the MOS capacitors with different oxide thickness in the second-order PLL.
0.492 V. Fig. 4 shows the simulated transition waveforms of the control voltage (VCTRL) to find the locked time under the MOS capacitors with different oxide thickness in the second-order PLL. The PLL design with thin-oxide MOS capacitors (1-V NMOS and PMOS) has longer locked time and larger ripple voltage Vr than that with thick-oxide MOS capacitor (1.8-V
NMOS). The simulated static phase error Δt under the MOS capacitors with different oxide thickness in the second-order PLL is shown in Fig. 5. The thin-oxide MOS capacitors (1-V NMOS and PMOS) cause larger static phase error Δt than that with thick-oxide MOS capacitor (1.8-V NMOS) in the second-order PLL. The simulated voltage waveforms to find the jitter under the MOS capacitors with different oxide thicknesses in the second-order PLL is shown in Fig. 6. The thin-oxide MOS capacitors (1-V NMOS and PMOS) cause larger jitter than that with thick-oxide MOS capacitor (1.8-V NMOS) in the second-order PLL, due to the large ripple voltage at the VCTRLnode. The dependence of the different input-signal frequencies on the jitter and ripple voltage under the MOS capacitor with different oxide thickness in the second-order PLL is shown in Fig. 7.
Fig. 5. Simulated static phase error Δt under the MOS capacitors with different oxide thickness in the second-order PLL.
Fig. 6. Simulated voltage waveforms to find the jitter under the MOS capacitors with different oxide thicknesses in the second-order PLL.
Fig. 7. Dependence of different input-signal frequencies on the jitter and ripple voltage under the MOS capacitors with different oxide thickness in the second-order PLL.
The higher input-signal frequency FREFhas a smaller jitter in the second-order PLL due to the gate-tunneling leakage.
IV. DISCUSSION
In general, the capacitance of the MOS capacitor C1is larger than that of the MOS capacitor C2 in the second-order PLL design, as shown in Fig. 1. Because the capacitance of the MOS capacitor is proportional to the device size and oxide thickness, the gate-tunneling leakage of the MOS capacitor C1 is larger than that of the capacitor C2. The circuit schematic of Fig. 1 can be simplified to that of Fig. 8, where the current ICPis the CP current, and the current IGTL,LFis the total gate-tunneling leakage of the MOS capacitors C1 and C2. The CP current ICP, which is controlled by the phase difference between FREF and FBACK signals through the PFD, is working as a con-stant current source. The effective charge current IC through
MOS capacitors C1 and C2 in the second-order PLL can be expressed as
IC= ICP− IGTL,LF. (2) To reach the locked state (phase difference between FREF and FBACKis constant), the second-order PLL needs a setting time for system stability. The gate-tunneling leakage reduces the effective charge current IC, therefore, the PLL needs more
charge time to make the control voltage VCTRL into the static state for controlling the VCO oscillation at the correct fre-quency. The locked time of the second-order PLL is increased due to the gate-tunneling leakage of the MOS capacitor.
In the locked state, the dependence of gate-tunneling leakage on the ripple voltage Vr in the second-order PLL can be
written as
ΔVr=
IGTL,LF× TREF C1
(3) where TREFis the period of input signal FREF. The amount of ripple voltage Vris proportional to the gate-tunneling leakage.
The large gate-tunneling current of the MOS capacitor will cause a large ripple voltage at the VCTRL node in the second-order PLL. In (3), the ripple voltage Vris also proportional to
the period of input signal FREF, Therefore, the higher input-signal frequency causes a smaller ripple voltage in the second-order PLL, as shown in Fig. 7. According to (3), the dependence of gate-tunneling leakage on the jitter of the second-order PLL can be expressed as
Jitter∝ ΔVr× KVCO=
IGTL,LF× KVCO
fREF× C1 (4) where the KVCO(Hz/V) is the gain of the VCO, and fREFis the input frequency of input signal FREF. The large ripple voltage ΔVrand the low input frequency of FREF cause large jitter in the second-order PLL. Therefore, the gate-tunneling leakage of the MOS capacitor in the loop filter has serious impact on the PLL performance. To reduce the impact from the gate-tunneling leakage of the MOS capacitor in the loop filter on the PLL performance, the PLL should be designed with small KVCO gain in the VCO.
When the PLL is operating in the locked state, the feedback clock signal (FBACK) compares with the reference clock signal (FREF) via the CP to generate loop voltage (VCTRL) for
controlling the VCO frequency. The CP has always supplied the current pulses to compensate the gate-tunneling leakage of the MOS capacitor. The dependence of gate-tunneling leakage on the static phase error Δt of the second-order PLL can be expressed as
Δt∝IGTL,TL
ICP × TREF. (5)
To reduce the static phase error in the second-order PLL, the CP should be designed with a large constant current.
The different layout structures will also influence the gate-tunneling leakage of the MOS transistor in the nanoscale CMOS process. When the equivalent gate-oxide resistance is also reduced due to the oxide thickness scaling down, the gate resistor (poly resistance) may lead to an effective gate-bias drop resulting in the decrease of drain current and tunneling leakage. As a result, the threshold voltage of a thin-oxide device is apparently increased by the voltage drop on gate poly resistor and fluctuates due to the gate-tunneling leakage [19]. Because the gate-tunneling leakage of the MOSFET is proportional to the voltage drop through the gate oxide, the MOS capacitor should be drawn in the layout with fewer gate fingers to reduce the negative impact of gate-tunneling leakage on the PLL performance.
V. CONCLUSION
The influence from the gate-tunneling leakage of the MOS capacitor on the circuit performance in the second-order PLL has been analyzed and investigated in a 90-nm 1-V CMOS process. The locked time, static phase error, and jitter of the second-order PLL were degraded by the gate-tunneling leakage of the MOS capacitor in the loop filter. The higher input-signal frequency can be used to reduce the negative impact of gate-tunneling leakage on the performance of the second-order PLL in nanoscale CMOS technology. The PMOS device with high threshold voltage and thick oxide thickness can be used to realize the MOS capacitor in the loop filter for achieving the second-order PLL with low-jitter performance.
ACKNOWLEDGMENT
The authors would like to thank Editor C.-Y. Lu and his reviewers for their valuable suggestions to improve this manuscript.
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Jung-Sheng Chen received the B.S. degree from
the Department of Electronics Engineering, Na-tional Taiwan University of Science and Technology, Taipei, Taiwan, in 2000, the M.S. degree in engi-neering and system science from National Tsing-Hua University, Hsinchu, Taiwan, in 2002, and the Ph.D. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, in 2007.
He is currently a Circuit Design Engineer with Power Conversion Taiwan, Fairchild Semiconductor Corporation, Hsinchu. His research interests include reliability design of analog circuits as well as power management integrated circuits and systems.
Ming-Dou Ker (S’92–M’94–SM’97–F’08) received
the Ph.D. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1993.
He was a Department Manager with the VLSI Design Division, Computer and Communication Re-search Laboratories, Industrial Technology ReRe-search Institute, Hsinchu. Since 2004, he has been a Full Professor with the Department of Electronics En-gineering, National Chiao-Tung University, where from 2006 to 2008, he served as the Director of the master’s degree program of the College of Electrical Engineering and Computer Science, as well as the Associate Executive Director of National Science and Technology Program on System-on-Chip in Taiwan. Since 2008, he has been the Chair Professor and Vice-President of I-Shou University, Kaohsiung, Taiwan. In the field of reliability and quality design for circuits and systems in CMOS technology, he has published over 360 technical papers in international journals and conferences. He is the inventor/co-inventor of 144 U.S. and 144 Taiwan patents after his many proposed inventions to improve the reliability and quality of integrated circuits (ICs). He had been invited to teach and/or to con-sult on the reliability and quality design for IC products by hundreds of design houses and semiconductor companies in the worldwide IC industry. His current research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, on-glass circuits for system-on-panel applications, and biomimetic circuits and systems for intelligent prosthesis.
Prof. Ker has served as a member of the Technical Program Committee and the session chair of numerous international conferences. He has served as Associate Editor for the IEEE TRANSACTIONS ONVERYLARGESCALE
INTEGRATION(VLSI) SYSTEMS. He was selected as distinguished lecturer in the IEEE Circuits and Systems Society (2006–2007) and in the IEEE Electron Devices Society (2008–2009). He was the president of Foundation in Taiwan ESD Association. In 2008, he was elevated to IEEE Fellow with the citation of “for contributions to electrostatic protection in integrated circuits and performance optimization of VLSI microsystems.” In 2009, he was awarded as one of the top ten Distinguished Inventors in Taiwan, and he is one of the top hundred Distinguished Inventors in China.
